A 100000-A series high-precision on-site calibration device for measuring high direct current of a magnetic modulation comparator type is presented. The device can be used in an industrial system for online calibration and measurement. Testing of the comparator shows that its accuracy for measuring current ratio is 5*10/sup .5/ and for measuring voltage with a standard resistance is 3*10/sup .4/ (on-site calibration), 5*10/sup .4/ (accurate measurement), or 1*10/sup .3/ (on-site measurement). The error in repeatability for measuring open-loop cores is 2*10/sup .5/, and its antimagnetic ability with respect to the external magnetic field is 1*10/sup .2/ Tesla. The author discusses the principle of operation and characteristics of the comparator, the antimagnetic principle, and the analysis of comparator errors.<>
{"title":"A 100000-ampere series high precision on-site measurement calibration device for heavy direct current","authors":"S. Ren","doi":"10.1109/IMTC.1989.36827","DOIUrl":"https://doi.org/10.1109/IMTC.1989.36827","url":null,"abstract":"A 100000-A series high-precision on-site calibration device for measuring high direct current of a magnetic modulation comparator type is presented. The device can be used in an industrial system for online calibration and measurement. Testing of the comparator shows that its accuracy for measuring current ratio is 5*10/sup .5/ and for measuring voltage with a standard resistance is 3*10/sup .4/ (on-site calibration), 5*10/sup .4/ (accurate measurement), or 1*10/sup .3/ (on-site measurement). The error in repeatability for measuring open-loop cores is 2*10/sup .5/, and its antimagnetic ability with respect to the external magnetic field is 1*10/sup .2/ Tesla. The author discusses the principle of operation and characteristics of the comparator, the antimagnetic principle, and the analysis of comparator errors.<<ETX>>","PeriodicalId":298343,"journal":{"name":"6th IEEE Conference Record., Instrumentation and Measurement Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128270003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
For pt.II see IEEE Transactions on Instrumentation and Measurement, vol.37, no.3 (Sept. 1988). The author presents an algorithm for estimating the sampling time offsets of the parallel sampling paths of an ultra-high-speed waveform digitizing system that is realized by interleaving many sample-and-hold and A/D (analog/digital) converter modules. One obvious application of this algorithm is to feed these estimates back to adjustable delay units in all the sampling paths to compensate the sampling time offsets. Simulation results indicate that with an 8-bit quantizer the residual timing error can be reduced to just about 0.05% of the sampling period.<>
{"title":"Digital spectra of non-uniformly sampled signals: theories and applications. III. A robust sampling time offset estimation algorithm for ultra high speed waveform digitizers using interleaving","authors":"Y. Jenq","doi":"10.1109/IMTC.1989.36855","DOIUrl":"https://doi.org/10.1109/IMTC.1989.36855","url":null,"abstract":"For pt.II see IEEE Transactions on Instrumentation and Measurement, vol.37, no.3 (Sept. 1988). The author presents an algorithm for estimating the sampling time offsets of the parallel sampling paths of an ultra-high-speed waveform digitizing system that is realized by interleaving many sample-and-hold and A/D (analog/digital) converter modules. One obvious application of this algorithm is to feed these estimates back to adjustable delay units in all the sampling paths to compensate the sampling time offsets. Simulation results indicate that with an 8-bit quantizer the residual timing error can be reduced to just about 0.05% of the sampling period.<<ETX>>","PeriodicalId":298343,"journal":{"name":"6th IEEE Conference Record., Instrumentation and Measurement Technology Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132429287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An analog-to-digital converter consisting of a switched-capacitor integrator, comparator, and control circuit is presented. The conversion process consists of voltage-to-frequency conversion to determine the upper M bits of an N-bit representation of an input analog voltage and subsequent voltage-to-time conversion to determine the remaining lower N-M bits. The total clock cycle required for N-bit resolution is 2/sup M/+2/sup N-M/ at most. The circuits for the two conversions have most of their components in common and thus can be implemented with minimum component count. Error analysis shows that a conversion accuracy higher than 12 bits can be expected from a CMOS monolithic realization. Prototype converters built using discrete components have confirmed the principles of operation.<>
{"title":"An integration-type high speed analog-to-digital converter","authors":"K. Kondo, K. Watanabe","doi":"10.1109/IMTC.1989.36809","DOIUrl":"https://doi.org/10.1109/IMTC.1989.36809","url":null,"abstract":"An analog-to-digital converter consisting of a switched-capacitor integrator, comparator, and control circuit is presented. The conversion process consists of voltage-to-frequency conversion to determine the upper M bits of an N-bit representation of an input analog voltage and subsequent voltage-to-time conversion to determine the remaining lower N-M bits. The total clock cycle required for N-bit resolution is 2/sup M/+2/sup N-M/ at most. The circuits for the two conversions have most of their components in common and thus can be implemented with minimum component count. Error analysis shows that a conversion accuracy higher than 12 bits can be expected from a CMOS monolithic realization. Prototype converters built using discrete components have confirmed the principles of operation.<<ETX>>","PeriodicalId":298343,"journal":{"name":"6th IEEE Conference Record., Instrumentation and Measurement Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129377431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A method for generating a controlled number of pulses randomly within a specified time is presented. The number of random pulses is presettable by an external device. The theory of maximal-length pseudorandom binary sequences is used as the basis of the method. An example of such a random generator is given, and it is implemented in a single VLSI chip using 3- mu m double-layer CMOS technology. This method of producing a controlled probability random generator has been proved to be simple and can be implemented in a single chip of not more than 500 gates.<>
{"title":"A controlled probability random pulse generator suitable for VLSI implementation","authors":"A. Al-Khalili, D. Al-Khalili","doi":"10.1109/IMTC.1989.36863","DOIUrl":"https://doi.org/10.1109/IMTC.1989.36863","url":null,"abstract":"A method for generating a controlled number of pulses randomly within a specified time is presented. The number of random pulses is presettable by an external device. The theory of maximal-length pseudorandom binary sequences is used as the basis of the method. An example of such a random generator is given, and it is implemented in a single VLSI chip using 3- mu m double-layer CMOS technology. This method of producing a controlled probability random generator has been proved to be simple and can be implemented in a single chip of not more than 500 gates.<<ETX>>","PeriodicalId":298343,"journal":{"name":"6th IEEE Conference Record., Instrumentation and Measurement Technology Conference","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124898857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An efficient approach is presented for functional testing and parameter estimation of analog circuits in the time domain. The test equations are based on the sensitivity matrix, which can be obtained simultaneously with the nominal solution vector. Two examples (an amplifier-attenuator network and a bandpass filter) are given, with results based on actual measurement data. Practical considerations, including the effects of ambiguity groups, measurement errors, and time skew, are covered. The approach can be directly extended to nonlinear circuits.<>
{"title":"Time domain testing strategies and fault diagnosis for analog systems","authors":"H. Dai, T. Souders","doi":"10.1109/IMTC.1989.36873","DOIUrl":"https://doi.org/10.1109/IMTC.1989.36873","url":null,"abstract":"An efficient approach is presented for functional testing and parameter estimation of analog circuits in the time domain. The test equations are based on the sensitivity matrix, which can be obtained simultaneously with the nominal solution vector. Two examples (an amplifier-attenuator network and a bandpass filter) are given, with results based on actual measurement data. Practical considerations, including the effects of ambiguity groups, measurement errors, and time skew, are covered. The approach can be directly extended to nonlinear circuits.<<ETX>>","PeriodicalId":298343,"journal":{"name":"6th IEEE Conference Record., Instrumentation and Measurement Technology Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125203377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The author reviews the HP 54111D oscilloscope and describes the digitizers, which sample at up to 1 GSPS (gigasample per second) with 6 bits of resolution and greater than 1-GHz bandwidth. Four interleaved silicon bipolar 6-bit ADCs (analog/digital converters) form the heart of the acquisition system. A GaAs track-and-hold IC uses a dual rank sampling architecture as it fans out the signal to the ADCs. A GaAs clock-control IC accepts the sample clock from the timebase and generates the required track-and-hold clocks and ADC clocks for the system. Four silicon NMOS ICs each accept digital data at 250 MSPS (million samples per second) and provide a total memory depth of 8 K samples.<>
{"title":"The 1 GSPS digitizer in the HP 54111D oscilloscope","authors":"A. Montijo","doi":"10.1109/IMTC.1989.36842","DOIUrl":"https://doi.org/10.1109/IMTC.1989.36842","url":null,"abstract":"The author reviews the HP 54111D oscilloscope and describes the digitizers, which sample at up to 1 GSPS (gigasample per second) with 6 bits of resolution and greater than 1-GHz bandwidth. Four interleaved silicon bipolar 6-bit ADCs (analog/digital converters) form the heart of the acquisition system. A GaAs track-and-hold IC uses a dual rank sampling architecture as it fans out the signal to the ADCs. A GaAs clock-control IC accepts the sample clock from the timebase and generates the required track-and-hold clocks and ADC clocks for the system. Four silicon NMOS ICs each accept digital data at 250 MSPS (million samples per second) and provide a total memory depth of 8 K samples.<<ETX>>","PeriodicalId":298343,"journal":{"name":"6th IEEE Conference Record., Instrumentation and Measurement Technology Conference","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125229532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Methods are presented that allow high-resolution (better than +or-0.5 m degrees ) relative and absolute phase measurements between sine waves to be made at, or in the vicinity, of angles of 0 degrees , 60 degrees , 90 degrees , and 180 degrees . Three of these methods appear to be completely independent of each other. They involve the use of 180 degrees phase verification bridges, the use of a sine wave as a zero-degree intrinsic standard of phase, and the use of quadrature phase meters, respectively. A representative sampling of data comparing the different approaches is presented.<>
{"title":"Phase measurement, traceability, and verification theory and practice","authors":"K. Clarke, D. Hess","doi":"10.1109/IMTC.1989.36856","DOIUrl":"https://doi.org/10.1109/IMTC.1989.36856","url":null,"abstract":"Methods are presented that allow high-resolution (better than +or-0.5 m degrees ) relative and absolute phase measurements between sine waves to be made at, or in the vicinity, of angles of 0 degrees , 60 degrees , 90 degrees , and 180 degrees . Three of these methods appear to be completely independent of each other. They involve the use of 180 degrees phase verification bridges, the use of a sine wave as a zero-degree intrinsic standard of phase, and the use of quadrature phase meters, respectively. A representative sampling of data comparing the different approaches is presented.<<ETX>>","PeriodicalId":298343,"journal":{"name":"6th IEEE Conference Record., Instrumentation and Measurement Technology Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129609199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Rectangular, steplike waveforms, occurring in many physical systems, are passed through sensors or signal conditioners having, in many cases, low-pass filter characteristics. The filtered waveforms are sampled by A/D (analog/digital) converters and the average or RMS (root-mean-square) values calculated. The author describes the effects of the low-pass filter characteristics on the average and RMS values of the waveforms and the analysis method used to determine the effects. It is shown that once the data-acquisition-system component under consideration has been modeled by an s-domain transfer function and the input waveform is known, the solution process is mechanical. By the way of example, the method is applied to a measurement problem and the results provided. The effects of assuming unit step excitation rather than physically realizable exponential step inputs are also discussed.<>
{"title":"RMS and average errors resulting from low pass filter characteristics in instrumentation systems","authors":"D. Destefan","doi":"10.1109/IMTC.1989.36823","DOIUrl":"https://doi.org/10.1109/IMTC.1989.36823","url":null,"abstract":"Rectangular, steplike waveforms, occurring in many physical systems, are passed through sensors or signal conditioners having, in many cases, low-pass filter characteristics. The filtered waveforms are sampled by A/D (analog/digital) converters and the average or RMS (root-mean-square) values calculated. The author describes the effects of the low-pass filter characteristics on the average and RMS values of the waveforms and the analysis method used to determine the effects. It is shown that once the data-acquisition-system component under consideration has been modeled by an s-domain transfer function and the input waveform is known, the solution process is mechanical. By the way of example, the method is applied to a measurement problem and the results provided. The effects of assuming unit step excitation rather than physically realizable exponential step inputs are also discussed.<<ETX>>","PeriodicalId":298343,"journal":{"name":"6th IEEE Conference Record., Instrumentation and Measurement Technology Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117329191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A vector-space interpretation of FAF (fast adaptive filter) algorithms is presented. These algorithms are shown to be different from the least-mean-square (LMS) algorithms or other stochastic gradient algorithms. The impulse response and convergence behavior of the FAF are faster than those of the adaptive noise canceller for the same input and initial condition. Thus the FAF is suitable for use in process detection and automation systems. Through realistic testing a structure based on FAF algorithms, intended to achieve additional reduction in computational requirements, was subjected to realistic testing. Improvements in numerical stability, tradeoffs in initialization, and fast convergence were achieved.<>
{"title":"Fast adaptive filter (FAF) use in process instrumentation and automation systems","authors":"Lin-Zhang Zhu, Jian-bo Meng, Zhao-Hui Zhang","doi":"10.1109/IMTC.1989.36880","DOIUrl":"https://doi.org/10.1109/IMTC.1989.36880","url":null,"abstract":"A vector-space interpretation of FAF (fast adaptive filter) algorithms is presented. These algorithms are shown to be different from the least-mean-square (LMS) algorithms or other stochastic gradient algorithms. The impulse response and convergence behavior of the FAF are faster than those of the adaptive noise canceller for the same input and initial condition. Thus the FAF is suitable for use in process detection and automation systems. Through realistic testing a structure based on FAF algorithms, intended to achieve additional reduction in computational requirements, was subjected to realistic testing. Improvements in numerical stability, tradeoffs in initialization, and fast convergence were achieved.<<ETX>>","PeriodicalId":298343,"journal":{"name":"6th IEEE Conference Record., Instrumentation and Measurement Technology Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127216968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A novel remote transducer telemetry system utilizing an optical link for electrical isolation and EMI (electromagnetic interference) immunity has been developed. This echo sensor telemetry system encodes information by a variable-pulse-width technique. The time between two echo pulses is proportional to, or a function of, the parameters being measured. At the sensing end the relatively intense incoming optical pulse (or series of pulses) is converted to a voltage by an array of photovoltaic cells. The cells power the electronics at the sensing end. The system is capable of interfacing resistance-, capacitance-, and voltage-type sensors. The power converter unit, micropower circuit, optical subsystem, and command and processing unit making up the system are detailed. An overall system accuracy of 1% and repetition rate between 500 and 1 kHz have been obtained experimentally. Using a 5-mW laser diode as a source, approximately 300 mu W of electrical power is available at the output of photovoltaic cells. The encoder circuit developed consumed less than 30 mu W of power. Additionally, a high-peak-intensity light transmitter operated at 1-V supply. Based on this single-echo sensor system, extension to a sensor network is outlined.<>
{"title":"Optically powered sensor signal telemetry system","authors":"Y. Trisno, P. Hsieh, D. Wobschall","doi":"10.1109/IMTC.1989.36898","DOIUrl":"https://doi.org/10.1109/IMTC.1989.36898","url":null,"abstract":"A novel remote transducer telemetry system utilizing an optical link for electrical isolation and EMI (electromagnetic interference) immunity has been developed. This echo sensor telemetry system encodes information by a variable-pulse-width technique. The time between two echo pulses is proportional to, or a function of, the parameters being measured. At the sensing end the relatively intense incoming optical pulse (or series of pulses) is converted to a voltage by an array of photovoltaic cells. The cells power the electronics at the sensing end. The system is capable of interfacing resistance-, capacitance-, and voltage-type sensors. The power converter unit, micropower circuit, optical subsystem, and command and processing unit making up the system are detailed. An overall system accuracy of 1% and repetition rate between 500 and 1 kHz have been obtained experimentally. Using a 5-mW laser diode as a source, approximately 300 mu W of electrical power is available at the output of photovoltaic cells. The encoder circuit developed consumed less than 30 mu W of power. Additionally, a high-peak-intensity light transmitter operated at 1-V supply. Based on this single-echo sensor system, extension to a sensor network is outlined.<<ETX>>","PeriodicalId":298343,"journal":{"name":"6th IEEE Conference Record., Instrumentation and Measurement Technology Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125612432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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