A 135000-transistor single-chip Reed-Solomon encoder-decoder is presented. The chip can process data at up to 10 Mb/s and uses a (255, 223) block code which is able to correct up to 16 symbol errors. This code is the worldwide standard for telemetry space transmission. A 9-month turnaround, from design to test, was obtained with efficient IA-based CAD (computer-aided design) tools and a fast prototyping electron-beam direct writing process.<>
{"title":"A 10 MHz (255, 223) Reed-Solomon decoder","authors":"N. Demassieux, F. Jutand, M. Muller","doi":"10.1109/CICC.1988.20889","DOIUrl":"https://doi.org/10.1109/CICC.1988.20889","url":null,"abstract":"A 135000-transistor single-chip Reed-Solomon encoder-decoder is presented. The chip can process data at up to 10 Mb/s and uses a (255, 223) block code which is able to correct up to 16 symbol errors. This code is the worldwide standard for telemetry space transmission. A 9-month turnaround, from design to test, was obtained with efficient IA-based CAD (computer-aided design) tools and a fast prototyping electron-beam direct writing process.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128183975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A 240-gate silicon bipolar array is described. The array is manufactured by a state-of-the-art 0.6- mu m bipolar process. A typical gate delay is 80 ps for a fanout of two, and the maximum D-type toggle rate is 3.6 GHz. The array is intended for applications with data I/O rates up to 6 Gb/s.<>
{"title":"An ultra-high speed gate array based on 0.6 mu m silicon bipolar technology","authors":"M. Cooke, M. Golder, D. Taylor","doi":"10.1109/CICC.1988.20903","DOIUrl":"https://doi.org/10.1109/CICC.1988.20903","url":null,"abstract":"A 240-gate silicon bipolar array is described. The array is manufactured by a state-of-the-art 0.6- mu m bipolar process. A typical gate delay is 80 ps for a fanout of two, and the maximum D-type toggle rate is 3.6 GHz. The array is intended for applications with data I/O rates up to 6 Gb/s.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134338241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The authors discuss the issues related to implementing an adaptive control algorithm for robots. The requirements of this application lead to different architectural choices than what is typically done in general-purpose DSPs (digital signal processors). Based on this analysis, they have designed a dedicated chip whose important features are efficient implementation of control flow operations such as branches, loops, etc., and a practical strategy for testability. The layout generation of the custom circuit is facilitated by integrating a structural description of the processor inside a silicon compiler environment. With this scheme, customized versions of processor can be quickly generated for different applications.<>
{"title":"A custom DSP chip to implement a robot motion controller","authors":"S. K. Azim, R. Brodersen","doi":"10.1109/CICC.1988.20827","DOIUrl":"https://doi.org/10.1109/CICC.1988.20827","url":null,"abstract":"The authors discuss the issues related to implementing an adaptive control algorithm for robots. The requirements of this application lead to different architectural choices than what is typically done in general-purpose DSPs (digital signal processors). Based on this analysis, they have designed a dedicated chip whose important features are efficient implementation of control flow operations such as branches, loops, etc., and a practical strategy for testability. The layout generation of the custom circuit is facilitated by integrating a structural description of the processor inside a silicon compiler environment. With this scheme, customized versions of processor can be quickly generated for different applications.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132518437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Tsubone, T. Osumi, T. Ishizaki, M. Shinohara, M. Suzuki, K. Matsumi, K. Akahane
A smart BiCMOS (bipolar complementary metal-oxide semiconductor) driver for 400 DPI (dot/inch) thermal printing heads has been developed using a dot-history-control circuit, a high-voltage BiCMOS process, and solder-bump electrode bonding. Thermal printing heads with a printing speed of 1000 line/s, resolution of 400 DPI, and a substrate only 12.7 mm wide have been realized.<>
{"title":"A smart BiCMOS driver for 400 DPI thermal printing heads","authors":"K. Tsubone, T. Osumi, T. Ishizaki, M. Shinohara, M. Suzuki, K. Matsumi, K. Akahane","doi":"10.1109/CICC.1988.20802","DOIUrl":"https://doi.org/10.1109/CICC.1988.20802","url":null,"abstract":"A smart BiCMOS (bipolar complementary metal-oxide semiconductor) driver for 400 DPI (dot/inch) thermal printing heads has been developed using a dot-history-control circuit, a high-voltage BiCMOS process, and solder-bump electrode bonding. Thermal printing heads with a printing speed of 1000 line/s, resolution of 400 DPI, and a substrate only 12.7 mm wide have been realized.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129318586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Analog VLSI implementations of adaptive systems, either of the traditional variety or the more complex types frequently found in neural network models of learning, require variable analog weights which are compact and have substantial resolution. The authors have designed a chip in ordinary 1.25- mu m CMOS which stores analog weights as charge on MOS capacitors. The weights, of which there are 1104 per chip, can be updated in parallel along a vector in weight space, allowing for efficient implementations of gradient descent algorithms. The chips are organized as 46*24 matrix multipliers with voltage inputs and current outputs.<>
自适应系统的模拟VLSI实现，无论是传统的品种还是更复杂的类型，经常在神经网络学习模型中发现，都需要可变的模拟权重，这些模拟权重紧凑且具有很高的分辨率。在普通的1.25 μ m CMOS中设计了一种将模拟量作为电荷存储在MOS电容上的芯片。每个芯片有1104个权重，可以沿着权重空间中的向量并行更新，从而允许有效地实现梯度下降算法。芯片组织为46*24矩阵乘法器，具有电压输入和电流输出
{"title":"A programmable analog neural network chip","authors":"D. B. Schwartz, R. Howard","doi":"10.1109/CICC.1988.20837","DOIUrl":"https://doi.org/10.1109/CICC.1988.20837","url":null,"abstract":"Analog VLSI implementations of adaptive systems, either of the traditional variety or the more complex types frequently found in neural network models of learning, require variable analog weights which are compact and have substantial resolution. The authors have designed a chip in ordinary 1.25- mu m CMOS which stores analog weights as charge on MOS capacitors. The weights, of which there are 1104 per chip, can be updated in parallel along a vector in weight space, allowing for efficient implementations of gradient descent algorithms. The chips are organized as 46*24 matrix multipliers with voltage inputs and current outputs.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129690619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J.L. Bouknight, S. Leibiger, K.S. Yakabu, H.K. Hingarh
A description is given of an integrated empirical modeling methodology which has been successfully applied in modeling the ASPECT process (Advanced Single Poly Emitter Coupled Technology) to ensure manufacturable circuit designs. The accuracy which has been achieved with this degree of modeling has contributed significantly to realizing 'right the first time' designs on a number of standard cell VLSI ECL (emitter-coupled logic) designs. A comprehensive test chip was used to construct a database composed of both single-point and multipoint measurements along with capacitance voltage behavior, f/sub T/ characteristics, and ring-oscillator large-signal characteristics over a broad speed range of power-switching currents. These were analyzed with and without capacitance loads. Corner file models formulated from this characterization in the design of circuits which were manufacturable and achieved correctness on first-pass design of a number of VLSI standard-cell ECL circuits.<>
{"title":"Modeling modern bipolar technologies to insure design for manufacturability","authors":"J.L. Bouknight, S. Leibiger, K.S. Yakabu, H.K. Hingarh","doi":"10.1109/CICC.1988.20861","DOIUrl":"https://doi.org/10.1109/CICC.1988.20861","url":null,"abstract":"A description is given of an integrated empirical modeling methodology which has been successfully applied in modeling the ASPECT process (Advanced Single Poly Emitter Coupled Technology) to ensure manufacturable circuit designs. The accuracy which has been achieved with this degree of modeling has contributed significantly to realizing 'right the first time' designs on a number of standard cell VLSI ECL (emitter-coupled logic) designs. A comprehensive test chip was used to construct a database composed of both single-point and multipoint measurements along with capacitance voltage behavior, f/sub T/ characteristics, and ring-oscillator large-signal characteristics over a broad speed range of power-switching currents. These were analyzed with and without capacitance loads. Corner file models formulated from this characterization in the design of circuits which were manufacturable and achieved correctness on first-pass design of a number of VLSI standard-cell ECL circuits.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"234 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132354423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The coupling of signals between sensitive nets by signals from digital and large-swing analog nets and effects of unwanted parasitic capacitances due to overlapping nets are a concern in the design of analogue VLSI circuits. A two-layer, detailed channel-routing algorithm for mixed analog and digital signal nets has been developed to address these problems. The algorithm accounts for capacitive coupling between nets on the same layer and on adjacent layers. It has been implemented in the C programming language.<>
{"title":"A two-layer channel routing algorithm for mixed analog and digital signal nets","authors":"J. Jeen, R.S. Gyurcsik, W. Liu","doi":"10.1109/CICC.1988.20847","DOIUrl":"https://doi.org/10.1109/CICC.1988.20847","url":null,"abstract":"The coupling of signals between sensitive nets by signals from digital and large-swing analog nets and effects of unwanted parasitic capacitances due to overlapping nets are a concern in the design of analogue VLSI circuits. A two-layer, detailed channel-routing algorithm for mixed analog and digital signal nets has been developed to address these problems. The algorithm accounts for capacitive coupling between nets on the same layer and on adjacent layers. It has been implemented in the C programming language.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117189001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Schmiesing, K. Chang, F. Pintchovski, J. Klein, K. Baker, C. Meyer, S. Lai, D. Hoang, D. Tang
An advanced triple-level metal CMOS technology (TRIM), which uses a twin-well approach to achieve optimal device performance, is described in detail with emphasis on novel process like borophosphosilicate glass wet/dry etch, barrier metal, and boron-doped silica glass. Degradation of device reliability due to the triple-level metal (TLM) is also discussed. A 100 K gate array has been successfully manufactured utilizing this technology. NAND gate delays of 250 ps at V/sub dd/ of 5 V have been demonstrated. The Motorola automatic routing tool can achieve a very high gate utilization efficiency of 80% as a result of the use of the third-level metal.<>
{"title":"An advanced triple level metal CMOS technology for ASIC applications","authors":"J. Schmiesing, K. Chang, F. Pintchovski, J. Klein, K. Baker, C. Meyer, S. Lai, D. Hoang, D. Tang","doi":"10.1109/CICC.1988.20932","DOIUrl":"https://doi.org/10.1109/CICC.1988.20932","url":null,"abstract":"An advanced triple-level metal CMOS technology (TRIM), which uses a twin-well approach to achieve optimal device performance, is described in detail with emphasis on novel process like borophosphosilicate glass wet/dry etch, barrier metal, and boron-doped silica glass. Degradation of device reliability due to the triple-level metal (TLM) is also discussed. A 100 K gate array has been successfully manufactured utilizing this technology. NAND gate delays of 250 ps at V/sub dd/ of 5 V have been demonstrated. The Motorola automatic routing tool can achieve a very high gate utilization efficiency of 80% as a result of the use of the third-level metal.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122224564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An on-chip power supply conversion circuit which converts 5 V to 3 V has been investigated. An output voltage stabilization of +or-10% has been achieved over supply voltage, temperature, and current variations, at a standby current below 25 mu A. The output voltage remains above 2.5 V at a switching current of 100 mA/15 ns. The conversion circuit can thus even be used for memory circuits.<>
{"title":"All MOS on-chip power supply conversion","authors":"M. Paul, R. Kraus, K. Hoffmann, J. Harter","doi":"10.1109/CICC.1988.20807","DOIUrl":"https://doi.org/10.1109/CICC.1988.20807","url":null,"abstract":"An on-chip power supply conversion circuit which converts 5 V to 3 V has been investigated. An output voltage stabilization of +or-10% has been achieved over supply voltage, temperature, and current variations, at a standby current below 25 mu A. The output voltage remains above 2.5 V at a switching current of 100 mA/15 ns. The conversion circuit can thus even be used for memory circuits.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124436151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A description is given of a building block router which performs routing in two stages, symbolic routing and compaction. It provides many needed features to support the stringent area and performance requirements of the full custom IC layout. In addition to channel routing, fast and effective switch-box routing made possible by the symbolic environment solves the cyclic constraint problem and improves the routing quality. The ability to honor pre-existing routing provides the flexibility for unlimited customization. In addition, it establishes the foundation for algorithms with different focuses to work together. The success of the router in working with various types of designs and technologies proves it to be a useful production tool.<>
{"title":"Building block routing-a symbolic approach","authors":"Nir Chen","doi":"10.1109/CICC.1988.20844","DOIUrl":"https://doi.org/10.1109/CICC.1988.20844","url":null,"abstract":"A description is given of a building block router which performs routing in two stages, symbolic routing and compaction. It provides many needed features to support the stringent area and performance requirements of the full custom IC layout. In addition to channel routing, fast and effective switch-box routing made possible by the symbolic environment solves the cyclic constraint problem and improves the routing quality. The ability to honor pre-existing routing provides the flexibility for unlimited customization. In addition, it establishes the foundation for algorithms with different focuses to work together. The success of the router in working with various types of designs and technologies proves it to be a useful production tool.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115989279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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