A discussion is presented as to why special-purpose chips are needed for useful implementations of algorithms in such applications as pattern recognition and classification. The authors describe one design in particular, the key feature of which is simple arithmetic processors distributed among data storage to minimize data movement. The algorithm performed by the chip is mapped exactly into the silicon and is tailored to the application in a tradeoff of flexibility for speed. The mapping of the algorithm is such that there are never bus conflicts or memory sharing; this allows every computing element to operate at maximum efficiency.<>
{"title":"A digital implementation of a best match classifier","authors":"S. Mackie, J. Denker","doi":"10.1109/CICC.1988.20839","DOIUrl":"https://doi.org/10.1109/CICC.1988.20839","url":null,"abstract":"A discussion is presented as to why special-purpose chips are needed for useful implementations of algorithms in such applications as pattern recognition and classification. The authors describe one design in particular, the key feature of which is simple arithmetic processors distributed among data storage to minimize data movement. The algorithm performed by the chip is mapped exactly into the silicon and is tailored to the application in a tradeoff of flexibility for speed. The mapping of the algorithm is such that there are never bus conflicts or memory sharing; this allows every computing element to operate at maximum efficiency.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"244 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128749857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In mixed analog/digital circuits, op-amp noise, aliased noise, crosstalk from digital circuits, and distortion limit the dynamic range available. Op-amp design, gain partitioning and layout are the key in achieving >25-dB signal-to-noise ratios in an analog path containing 25 op amps. The authors present methods used to maximize dynamic range and measured results obtained from ASIC (application-specific integrated-circuit) devices.<>
{"title":"Noise, crosstalk and distortion in mixed analog/digital integrated circuits","authors":"G. Warren, C. Jungo","doi":"10.1109/CICC.1988.20849","DOIUrl":"https://doi.org/10.1109/CICC.1988.20849","url":null,"abstract":"In mixed analog/digital circuits, op-amp noise, aliased noise, crosstalk from digital circuits, and distortion limit the dynamic range available. Op-amp design, gain partitioning and layout are the key in achieving >25-dB signal-to-noise ratios in an analog path containing 25 op amps. The authors present methods used to maximize dynamic range and measured results obtained from ASIC (application-specific integrated-circuit) devices.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122982776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A description is given of the implementation of a low-power, high-performance telephone headset amplifier, using switched-capacitor techniques. Total power consumption is 3.5 mW with a single 5-V supply. Output noise level of -95 dBV has been achieved in both its receiver and transmitter channels. With a single 5-V supply the average area and power consumption per pole of filtering is 510 square mils and 120 mu W, respectively.<>
{"title":"A low power, high performance, phone headset amplifier in CMOS technology","authors":"M. Negahban-Hagh, R. Stolaruk, V. Kraz","doi":"10.1109/CICC.1988.20937","DOIUrl":"https://doi.org/10.1109/CICC.1988.20937","url":null,"abstract":"A description is given of the implementation of a low-power, high-performance telephone headset amplifier, using switched-capacitor techniques. Total power consumption is 3.5 mW with a single 5-V supply. Output noise level of -95 dBV has been achieved in both its receiver and transmitter channels. With a single 5-V supply the average area and power consumption per pole of filtering is 510 square mils and 120 mu W, respectively.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126144775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A description is given of the impact of card wiring nets on signals generated by CMOS chips. Card nets driven by CMOS circuits are treated as transmission lines with lumped capacitances attached at points along the line, representing connections to other CMOS chips. Evaluation of overvoltage and undervoltage conditions, available noise margin, and reflection settling time is discussed. Allowable net length, effect of waveform rise and fall time, and of receiver loading on delays for typical net types is described.<>
{"title":"Generalized wiring rules for CMOS circuits","authors":"J. J. Tomczak","doi":"10.1109/CICC.1988.20921","DOIUrl":"https://doi.org/10.1109/CICC.1988.20921","url":null,"abstract":"A description is given of the impact of card wiring nets on signals generated by CMOS chips. Card nets driven by CMOS circuits are treated as transmission lines with lumped capacitances attached at points along the line, representing connections to other CMOS chips. Evaluation of overvoltage and undervoltage conditions, available noise margin, and reflection settling time is discussed. Allowable net length, effect of waveform rise and fall time, and of receiver loading on delays for typical net types is described.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126208349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A high-speed, compact three-way dynamically reconfigurable 32-bit CMOS adder is reported. The design of this adder uses an enhanced organization for 32-bit carry lookahead and uses an area-speed efficient dynamic circuit technique, called multiple-output domino logic. The reconfigurability is achieved without significant overhead on the basis of these combined techniques. The 248*1454- mu m/sup 2/ adder, fabricated in a standard 0.9- mu m two-level metal CMOS technology, has demonstrated 32-bit addition times of 8.0 ns at 25 degrees C with V/sub DD/=5.0 V.<>
{"title":"A high-speed dynamically reconfigurable 32-bit CMOS adder","authors":"I. Hwang, P.S. Magarschack","doi":"10.1109/CICC.1988.20888","DOIUrl":"https://doi.org/10.1109/CICC.1988.20888","url":null,"abstract":"A high-speed, compact three-way dynamically reconfigurable 32-bit CMOS adder is reported. The design of this adder uses an enhanced organization for 32-bit carry lookahead and uses an area-speed efficient dynamic circuit technique, called multiple-output domino logic. The reconfigurability is achieved without significant overhead on the basis of these combined techniques. The 248*1454- mu m/sup 2/ adder, fabricated in a standard 0.9- mu m two-level metal CMOS technology, has demonstrated 32-bit addition times of 8.0 ns at 25 degrees C with V/sub DD/=5.0 V.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128414419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A 5-V only, variable-size EEPROM (electrically erasable programmable read-only memory) is discussed. A test chip providing 256*8-bit memory is described, as well as the methodology used to implement it. Certain special nonvolatile memory circuits are investigated. Application areas, manufacturing issues, and testing techniques are also considered.<>
{"title":"Configurable EEPROMS for ASICS","authors":"B. Carney, E. Lucero, R. Mendel, H. Reiter","doi":"10.1109/CICC.1988.20795","DOIUrl":"https://doi.org/10.1109/CICC.1988.20795","url":null,"abstract":"A 5-V only, variable-size EEPROM (electrically erasable programmable read-only memory) is discussed. A test chip providing 256*8-bit memory is described, as well as the methodology used to implement it. Certain special nonvolatile memory circuits are investigated. Application areas, manufacturing issues, and testing techniques are also considered.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116849680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Sawada, T. Sakurai, K. Nogami, T. Iizuka, Y. Uchino, Y. Tanaka, T. Kobayashi, K. Kawagai, E. Ban, Y. Shiotari, Y. Itabashi, S. Kohyama
A 1-Mb DRAM (dynamic random-access memory) is embedded in a 72-K-raw-gates channelless gate array fabricated in 1.0- mu m HC/sup 2/MOS twin-well technology. The DRAM design is optimized for embedding, such as the adaptation of no substrated bias design and p-well protected n-channel memory cells. The typical delay time of the gate array is 0.4 ns, and the worst-case access time of the DRAM is 60 ns.<>
采用1.0 μ m HC/sup 2/MOS双孔技术，将1mb DRAM(动态随机存取存储器)嵌入72k原始门无通道门阵列中。该DRAM设计针对嵌入进行了优化，例如适应无衬底偏置设计和p阱保护的n通道存储单元。门阵列的典型延迟时间为0.4 ns, DRAM的最坏存取时间为60 ns.>
{"title":"A 72 K CMOS channellers gate array with embedded 1 Mbit dynamic RAM","authors":"K. Sawada, T. Sakurai, K. Nogami, T. Iizuka, Y. Uchino, Y. Tanaka, T. Kobayashi, K. Kawagai, E. Ban, Y. Shiotari, Y. Itabashi, S. Kohyama","doi":"10.1109/CICC.1988.20898","DOIUrl":"https://doi.org/10.1109/CICC.1988.20898","url":null,"abstract":"A 1-Mb DRAM (dynamic random-access memory) is embedded in a 72-K-raw-gates channelless gate array fabricated in 1.0- mu m HC/sup 2/MOS twin-well technology. The DRAM design is optimized for embedding, such as the adaptation of no substrated bias design and p-well protected n-channel memory cells. The typical delay time of the gate array is 0.4 ns, and the worst-case access time of the DRAM is 60 ns.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117202676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A description is given of the aspects of mixed analog and digital physical assembly relevant to analog silicon compilation. The approach addresses system-level analog design automation through silicon compilation; currently this consists of the synthesis of analog and predesigned digital blocks. The compilation is based on successive decompositions of high-level specifications and physical assembly requirements into those of lower level subblocks and devices. The driving applications are high-voltage application-specific integrated circuits (ASICs). Details of analog and system level physical assembly to satisfy a set of mixed analog, digital, and high-voltage requirements are presented together with the results from an implementation of the compiler.<>
{"title":"Physical assembly for analog compilation of high voltage ICs","authors":"E. Berkcan, M. d'Abreu","doi":"10.1109/CICC.1988.20865","DOIUrl":"https://doi.org/10.1109/CICC.1988.20865","url":null,"abstract":"A description is given of the aspects of mixed analog and digital physical assembly relevant to analog silicon compilation. The approach addresses system-level analog design automation through silicon compilation; currently this consists of the synthesis of analog and predesigned digital blocks. The compilation is based on successive decompositions of high-level specifications and physical assembly requirements into those of lower level subblocks and devices. The driving applications are high-voltage application-specific integrated circuits (ASICs). Details of analog and system level physical assembly to satisfy a set of mixed analog, digital, and high-voltage requirements are presented together with the results from an implementation of the compiler.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114167580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A description is presented of a single-chip, microcomputer-based pacemaker system in which high-level analog functions are integrated on the same IC as a 8-bit microcomputer and a DC-DC converter. Low voltage and low current techniques are used, as well as circuitry to compensate for any long-term drift of transistor characteristics. Each functional block is programmable and can therefore be used in a variety of other implantable, biomedical applications.<>
{"title":"An 8-bit microcomputer with analog subsystems for implantable biomedical applications","authors":"L. Stotts, K.R. Infinger","doi":"10.1109/CICC.1988.20799","DOIUrl":"https://doi.org/10.1109/CICC.1988.20799","url":null,"abstract":"A description is presented of a single-chip, microcomputer-based pacemaker system in which high-level analog functions are integrated on the same IC as a 8-bit microcomputer and a DC-DC converter. Low voltage and low current techniques are used, as well as circuitry to compensate for any long-term drift of transistor characteristics. Each functional block is programmable and can therefore be used in a variety of other implantable, biomedical applications.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114202614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Kobayshi, T. Aoki, Y. Tanaka, M. Nakahara, Y. Itabashi, E. Hamada, S. Kohyama
A double-level metal/triple-level metal compatible large-scale channelless gate array, 173 K gates on a chip, has been developed by utilizing a 1.0- mu m twin-well HC/sup 2/MOS process and a novel planarization technique for multilevel metallization. Two-input NAND propagation delay time measures 400 ps and 350 ps for DLM and TLM, respectively. A novel place-and-route algorithm achieved 40-60% gate utilization for DLM, i.e. over 100 K gates usable. In the case of TLM, utilization goes up to 60-85%, and even higher with larger macros such as memory modules, reaching around 150 k gates.<>
{"title":"DLM/TLM compatible 1.0 mu m gate array with over 100 K usable gates","authors":"T. Kobayshi, T. Aoki, Y. Tanaka, M. Nakahara, Y. Itabashi, E. Hamada, S. Kohyama","doi":"10.1109/CICC.1988.20904","DOIUrl":"https://doi.org/10.1109/CICC.1988.20904","url":null,"abstract":"A double-level metal/triple-level metal compatible large-scale channelless gate array, 173 K gates on a chip, has been developed by utilizing a 1.0- mu m twin-well HC/sup 2/MOS process and a novel planarization technique for multilevel metallization. Two-input NAND propagation delay time measures 400 ps and 350 ps for DLM and TLM, respectively. A novel place-and-route algorithm achieved 40-60% gate utilization for DLM, i.e. over 100 K gates usable. In the case of TLM, utilization goes up to 60-85%, and even higher with larger macros such as memory modules, reaching around 150 k gates.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126884205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：