A 50-MIPS (million-instruction-per-second) 90000-transistor CMOS multiprocessor chip is described. It has been designed as a building block for orthogonal transforms of TV images in a bandwidth-reduction system. 64 processing elements (serial parallel multipliers) are assembled in a systolic-like architecture. Because of its modularity, the chip can be used for matrix products of arbitrary size.<>
{"title":"A 50 MIPS multiprocessor chip for image processing","authors":"T. Denayer, E. Vanzieleghem, P. Jespers","doi":"10.1109/CICC.1988.20823","DOIUrl":"https://doi.org/10.1109/CICC.1988.20823","url":null,"abstract":"A 50-MIPS (million-instruction-per-second) 90000-transistor CMOS multiprocessor chip is described. It has been designed as a building block for orthogonal transforms of TV images in a bandwidth-reduction system. 64 processing elements (serial parallel multipliers) are assembled in a systolic-like architecture. Because of its modularity, the chip can be used for matrix products of arbitrary size.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132759103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Rijmenants, T. Schwarz, J. Litsios, R. Zinszner
A description is given of ILAC (Interactive Layout of Analog CMOS Circuits), a CAD (computer-aided design) tool that automatically generates geometrical layout for analog CMOS leaf cells from netlist information and user-specified constraints on cell bounds and input/output locations. ILAC is the companion tool of IDAC, a design tool that sizes analog CMOS circuits from a library of proven schematics given a set of functional specifications and technological parameters. Unlike existing analog silicon compilers that use some predefined placement for a specific type of circuit, ILAC determines an optimal layout for any circuit and any set of input parameters.<>
{"title":"ILAC: an automated layout tool for analog CMOS circuits","authors":"J. Rijmenants, T. Schwarz, J. Litsios, R. Zinszner","doi":"10.1109/CICC.1988.20820","DOIUrl":"https://doi.org/10.1109/CICC.1988.20820","url":null,"abstract":"A description is given of ILAC (Interactive Layout of Analog CMOS Circuits), a CAD (computer-aided design) tool that automatically generates geometrical layout for analog CMOS leaf cells from netlist information and user-specified constraints on cell bounds and input/output locations. ILAC is the companion tool of IDAC, a design tool that sizes analog CMOS circuits from a library of proven schematics given a set of functional specifications and technological parameters. Unlike existing analog silicon compilers that use some predefined placement for a specific type of circuit, ILAC determines an optimal layout for any circuit and any set of input parameters.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133499877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A 13-bit 80-kHz baseband analog-to-digital converter suitable for use in applications such as the ISDN U-interface is described. Two-stage third-order noise shaping permits the use of asampling frequency of only 2.56 MHz. The circuit has been implemented using conventional single-ended switched-capacitor techniques in a 1.5- mu m CMOS process.<>
介绍了一种适用于ISDN u接口等应用的13位80 khz基带模数转换器。两级三阶噪声整形允许使用采样频率仅为2.56 MHz。该电路采用传统的单端开关电容技术在1.5 μ m CMOS工艺中实现。
{"title":"A 13 bit ISDN-band oversampled ADC using two-stage third order noise shaping","authors":"L. Longo, M. Copeland","doi":"10.1109/CICC.1988.20906","DOIUrl":"https://doi.org/10.1109/CICC.1988.20906","url":null,"abstract":"A 13-bit 80-kHz baseband analog-to-digital converter suitable for use in applications such as the ISDN U-interface is described. Two-stage third-order noise shaping permits the use of asampling frequency of only 2.56 MHz. The circuit has been implemented using conventional single-ended switched-capacitor techniques in a 1.5- mu m CMOS process.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133375072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Pathak, S. Douglass, D. Vider, T. Mulder, J. Arreola, S. Mehta
A 20-ns, 600-mW, programmable logic device (PLD) using 0.8- mu m, two-layer metal, n-well CMOS EPROM technology is described. This PLD's architecture is optimized for asynchronous applications. It is a 28-pin device with 13 inputs, 12 I/Os, one V/sub CC/ and two V/sub SS/ pins. Each I/O pin has a macrocell which includes an input and an output register, and control muxes for output enable and feedback to the array. Product terms generate set, reset, and clock for each register independently. A product term input to the XOR gate can configure the D register into a JK, RS or T flip-flop. The sense amplifier is optimized for speed and power and is compensated for process, temperature, and pattern variations. The device uses substrate bias generator to improve performance and latchup immunity.<>
{"title":"A 20 NS CMOS programmable logic device for asynchronous applications","authors":"J. Pathak, S. Douglass, D. Vider, T. Mulder, J. Arreola, S. Mehta","doi":"10.1109/CICC.1988.20870","DOIUrl":"https://doi.org/10.1109/CICC.1988.20870","url":null,"abstract":"A 20-ns, 600-mW, programmable logic device (PLD) using 0.8- mu m, two-layer metal, n-well CMOS EPROM technology is described. This PLD's architecture is optimized for asynchronous applications. It is a 28-pin device with 13 inputs, 12 I/Os, one V/sub CC/ and two V/sub SS/ pins. Each I/O pin has a macrocell which includes an input and an output register, and control muxes for output enable and feedback to the array. Product terms generate set, reset, and clock for each register independently. A product term input to the XOR gate can configure the D register into a JK, RS or T flip-flop. The sense amplifier is optimized for speed and power and is compensated for process, temperature, and pattern variations. The device uses substrate bias generator to improve performance and latchup immunity.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133827000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Furuyama, T. Ohsawa, Y. Nagahama, H. Tanaka, Y. Watanabe, T. Kimura, K. Muraoka, K. Natori
A novel multiple-level storage DRAM (dynamic random-access memory) technique which obtains fairly fast access time is presented. The RAM area, especially the cell-array area, which is highly defect-sensitive, is reduced with this technique. Reasonable yield can thus be achieved. An experimental 1-Mb DRAM has been fabricated, and the 2-bit/cell storage technique has been verified to be suitable for macro-cell or memory-on-logic application.<>
{"title":"An experimental 2-bit/cell storage DRAM for macro cell or memory-on-logic application","authors":"T. Furuyama, T. Ohsawa, Y. Nagahama, H. Tanaka, Y. Watanabe, T. Kimura, K. Muraoka, K. Natori","doi":"10.1109/CICC.1988.20797","DOIUrl":"https://doi.org/10.1109/CICC.1988.20797","url":null,"abstract":"A novel multiple-level storage DRAM (dynamic random-access memory) technique which obtains fairly fast access time is presented. The RAM area, especially the cell-array area, which is highly defect-sensitive, is reduced with this technique. Reasonable yield can thus be achieved. An experimental 1-Mb DRAM has been fabricated, and the 2-bit/cell storage technique has been verified to be suitable for macro-cell or memory-on-logic application.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125328540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Chang, S. Cheng, Ko-Min Chang, J. Chalmers, C. Swift, J. Yeargain
An advanced high-voltage CMOS process has been developed for custom products with on-chip electrically erasable programmable read-only memory (EEPROM). The minimum feature size is 1.2 mu m. Process adjustments to achieve >18-V high-voltage operation are explained in detail. Performance of short-channel transistors with L/sub eff/<1.0 mu m is also described. The Motorola FETMOS EEPROM cell characteristics and reliability are discussed. Microprocessor chips with up to 68K bits of EEPROM have been fabricated using this process.<>
{"title":"An advanced high voltage CMOS process for custom logic circuits with embedded EEPROM","authors":"K. Chang, S. Cheng, Ko-Min Chang, J. Chalmers, C. Swift, J. Yeargain","doi":"10.1109/CICC.1988.20934","DOIUrl":"https://doi.org/10.1109/CICC.1988.20934","url":null,"abstract":"An advanced high-voltage CMOS process has been developed for custom products with on-chip electrically erasable programmable read-only memory (EEPROM). The minimum feature size is 1.2 mu m. Process adjustments to achieve >18-V high-voltage operation are explained in detail. Performance of short-channel transistors with L/sub eff/<1.0 mu m is also described. The Motorola FETMOS EEPROM cell characteristics and reliability are discussed. Microprocessor chips with up to 68K bits of EEPROM have been fabricated using this process.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134278643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Daubert, D. Green, J. Khoury, J. M. Trosino, E. Zimany, J. Barner, J. Plany, M. Tompsett
A description is given of a mixed analog/digital chip that forms the core of a low-speed modem for use over standard telephone lines. It meets CCITT and AT&T requirements for data transmission at 1200 and 2400 b/s and the AT&T requirements for 300-b/s operation. The chip is implemented in a 1.75- mu m analog CMOS process and occupies 32.4 mm/sup 2/. The device is powered by a single +or-5-V supply and consumes less than 115 mW. The architecture and circuit implementation are described, and experimental results are given.<>
{"title":"A single-supply CMOS V.22bis modem analog processor","authors":"S. Daubert, D. Green, J. Khoury, J. M. Trosino, E. Zimany, J. Barner, J. Plany, M. Tompsett","doi":"10.1109/CICC.1988.20940","DOIUrl":"https://doi.org/10.1109/CICC.1988.20940","url":null,"abstract":"A description is given of a mixed analog/digital chip that forms the core of a low-speed modem for use over standard telephone lines. It meets CCITT and AT&T requirements for data transmission at 1200 and 2400 b/s and the AT&T requirements for 300-b/s operation. The chip is implemented in a 1.75- mu m analog CMOS process and occupies 32.4 mm/sup 2/. The device is powered by a single +or-5-V supply and consumes less than 115 mW. The architecture and circuit implementation are described, and experimental results are given.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131570313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The problem of power distribution for WSI has been investigated, using SPICE simulations of distribution strategies for a number of wafer sizes under conditions of varying rail dimensions and processor size. Simulations concentrate on strategies used in an earlier, more specific report, involving grid arrangements in double-layer metal. Results support the suggestion that rails must be several hundred square micrometers in cross section to guarantee integrity of the supply. Large processors are seen to be only fractionally more attractive and a decision regarding this would therefore be dominated in practice by yield consideration. A prospective scheme is proposed which involves continuous metal surfaces for power and ground. This promises attractive performance if a practical realization is possible.<>
{"title":"Investigation of power distribution strategies for wafer scale integration (WSI)","authors":"T. York","doi":"10.1109/CICC.1988.20923","DOIUrl":"https://doi.org/10.1109/CICC.1988.20923","url":null,"abstract":"The problem of power distribution for WSI has been investigated, using SPICE simulations of distribution strategies for a number of wafer sizes under conditions of varying rail dimensions and processor size. Simulations concentrate on strategies used in an earlier, more specific report, involving grid arrangements in double-layer metal. Results support the suggestion that rails must be several hundred square micrometers in cross section to guarantee integrity of the supply. Large processors are seen to be only fractionally more attractive and a decision regarding this would therefore be dominated in practice by yield consideration. A prospective scheme is proposed which involves continuous metal surfaces for power and ground. This promises attractive performance if a practical realization is possible.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114977455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A CMOS erasable programmable logic device (EPLD) optimized for microprocessor peripheral and bus control applications is described. In addition to a general-purpose EPLD core and 52 user-configurable registers, the dedicated peripheral I/O logic can be programmed by the control macrocells to interface directly to all known microprocessor families. An I/O bus port with 24-mA drive capability allows direct connection to a microprocessor bus.<>
{"title":"Bus I/O register intensive user-configurable microprocessor peripheral","authors":"C. Hung, Yiu-Fai Chan","doi":"10.1109/CICC.1988.20874","DOIUrl":"https://doi.org/10.1109/CICC.1988.20874","url":null,"abstract":"A CMOS erasable programmable logic device (EPLD) optimized for microprocessor peripheral and bus control applications is described. In addition to a general-purpose EPLD core and 52 user-configurable registers, the dedicated peripheral I/O logic can be programmed by the control macrocells to interface directly to all known microprocessor families. An I/O bus port with 24-mA drive capability allows direct connection to a microprocessor bus.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116732627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
RELIANT is a CAD (computer-aided design) tool which predicts the failure rate of integrated circuit conductors. Circuit layout, device models, and electromigration process data are inputs to RELIANT. The interconnect patterns in a Caltech Intermediate Format (CIF) file are fractured into a number of characteristic segment types. An equivalent circuit is extracted and SPICE is used to determine the transient currents in each segment. Using parametric models for electromigration damage, the failure rate of the system is computed. RELIANT provides designers with feedback on the reliability hazards of a design. Results show the application of the tool to a standard-cell CMOS component. For modeling large VLSI interconnect systems, the incorporation of a switch-level simulator is discussed.<>
{"title":"RELIANT: a reliability analysis tool for VLSI interconnects","authors":"D. F. Frost, K. F. Poole, D. Haeussler","doi":"10.1109/CICC.1988.20949","DOIUrl":"https://doi.org/10.1109/CICC.1988.20949","url":null,"abstract":"RELIANT is a CAD (computer-aided design) tool which predicts the failure rate of integrated circuit conductors. Circuit layout, device models, and electromigration process data are inputs to RELIANT. The interconnect patterns in a Caltech Intermediate Format (CIF) file are fractured into a number of characteristic segment types. An equivalent circuit is extracted and SPICE is used to determine the transient currents in each segment. Using parametric models for electromigration damage, the failure rate of the system is computed. RELIANT provides designers with feedback on the reliability hazards of a design. Results show the application of the tool to a standard-cell CMOS component. For modeling large VLSI interconnect systems, the incorporation of a switch-level simulator is discussed.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121194672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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