The authors present two methods that are capable of computing the steady-state response of a circuit directly: harmonic balance, which is a frequency-domain method, and the finite-difference method, which is based in the time domain. Both of these methods are suitable for use on nonlinear circuits that contain distributed devices and that exhibit either periodic or quasiperiodic steady-state solutions.<>
{"title":"Finding the steady-state response of analog and microwave circuits","authors":"K. Kundert, A. Sangiovanni-Vincentelli","doi":"10.1109/CICC.1988.20808","DOIUrl":"https://doi.org/10.1109/CICC.1988.20808","url":null,"abstract":"The authors present two methods that are capable of computing the steady-state response of a circuit directly: harmonic balance, which is a frequency-domain method, and the finite-difference method, which is based in the time domain. Both of these methods are suitable for use on nonlinear circuits that contain distributed devices and that exhibit either periodic or quasiperiodic steady-state solutions.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"209 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114394943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Cacouris, R. Krchnavek, G. Scelsi, R. Scarmozzino, R. Osgood
The authors present a recently developed technique for direct writing of high-quality aluminium conductors for the purposes of prototyping and customizing integrated circuits. This laser-driven process is a one-step technique to accomplish the customizing metallization step that avoids the use of conventional lithography and allows for rapid turnaround of small quantities of semicustom ICs. This is demonstrated by wiring a CMOS gate-array using this technique and comparing it to the more common laser technique of ablating preexisting interconnects. The process thus provides a complement to laser ablation and allows for greater flexibility in customization.<>
{"title":"Laser customization by direct writing of aluminum interconnects","authors":"T. Cacouris, R. Krchnavek, G. Scelsi, R. Scarmozzino, R. Osgood","doi":"10.1109/CICC.1988.20916","DOIUrl":"https://doi.org/10.1109/CICC.1988.20916","url":null,"abstract":"The authors present a recently developed technique for direct writing of high-quality aluminium conductors for the purposes of prototyping and customizing integrated circuits. This laser-driven process is a one-step technique to accomplish the customizing metallization step that avoids the use of conventional lithography and allows for rapid turnaround of small quantities of semicustom ICs. This is demonstrated by wiring a CMOS gate-array using this technique and comparing it to the more common laser technique of ablating preexisting interconnects. The process thus provides a complement to laser ablation and allows for greater flexibility in customization.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114817565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A novel technique for realizing very large time constant switched-capacitor integrators is presented. The integrators are area-efficient and are insensitive to parasitic capacitances. A 60-Hz notch filter working from a 128-kHz clock has been designed using these integrators and implemented in a 1.5 mu m CMOS technology.<>
提出了一种实现超大时间常数开关电容积分器的新技术。积分器面积高效，对寄生电容不敏感。使用这些积分器设计了一个工作于128 khz时钟的60 hz陷波滤波器，并在1.5 μ m CMOS技术中实现。
{"title":"A novel parasitic insensitive switched-capacitor technique for realizing very large time constants","authors":"K. Nagaraj","doi":"10.1109/CICC.1988.20852","DOIUrl":"https://doi.org/10.1109/CICC.1988.20852","url":null,"abstract":"A novel technique for realizing very large time constant switched-capacitor integrators is presented. The integrators are area-efficient and are insensitive to parasitic capacitances. A 60-Hz notch filter working from a 128-kHz clock has been designed using these integrators and implemented in a 1.5 mu m CMOS technology.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114805970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An integrated processor dedicated to the computation of spectral distances and dynamic programming equations for speech recognition systems has been designed. Its 10-MIPS (million-instructions-per-second) power allows real-time recognition of 1000 isolated words and 300 connected words with a fully optimal method. Its flexibility makes it useful for a wide variety of dynamic time-warping algorithms. The chip has been processed in a 2- mu m CMOS technology, includes 127,309 transistors in a 60 mm/sup 2/ area, runs with a 20-MHz clock, and is delivered in a 84-pin PGA (pin-grid array) package. The design includes a fully optimized layout for the data-path and the clock generator, a standard-cell approach for the control logic block and the padring, and a compiled RAM.<>
设计了一种用于语音识别系统频谱距离和动态规划方程计算的集成处理器。其10-MIPS(每秒百万指令)的能力允许以完全优化的方法实时识别1000个孤立单词和300个连接单词。它的灵活性使其适用于各种动态时间规整算法。该芯片采用2 μ m CMOS技术进行加工，包括127,309个晶体管，面积为60 mm/sup 2/，运行20 mhz时钟，采用84引脚PGA(引脚网格阵列)封装。该设计包括数据路径和时钟发生器的完全优化布局，控制逻辑块和填充的标准单元方法，以及编译的RAM
{"title":"A dynamic programming processor for speech recognition","authors":"G. Quénot, J. Gauvain, J. Gangolf, J. Mariani","doi":"10.1109/CICC.1988.20840","DOIUrl":"https://doi.org/10.1109/CICC.1988.20840","url":null,"abstract":"An integrated processor dedicated to the computation of spectral distances and dynamic programming equations for speech recognition systems has been designed. Its 10-MIPS (million-instructions-per-second) power allows real-time recognition of 1000 isolated words and 300 connected words with a fully optimal method. Its flexibility makes it useful for a wide variety of dynamic time-warping algorithms. The chip has been processed in a 2- mu m CMOS technology, includes 127,309 transistors in a 60 mm/sup 2/ area, runs with a 20-MHz clock, and is delivered in a 84-pin PGA (pin-grid array) package. The design includes a fully optimized layout for the data-path and the clock generator, a standard-cell approach for the control logic block and the padring, and a compiled RAM.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132181306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Four floorplanning algorithms for full-custom ICs are compared. They are the min-cut algorithm, the force-directed algorithm, simulated annealing, and the sequence heuristic. Experimental results are shown. The discussion is restricted to the class of floorplans with a slicing structure. Experimental results are shown.<>
{"title":"Comparison of floorplanning algorithms for full custom ICs","authors":"H. Cai, J. Hegge","doi":"10.1109/CICC.1988.20816","DOIUrl":"https://doi.org/10.1109/CICC.1988.20816","url":null,"abstract":"Four floorplanning algorithms for full-custom ICs are compared. They are the min-cut algorithm, the force-directed algorithm, simulated annealing, and the sequence heuristic. Experimental results are shown. The discussion is restricted to the class of floorplans with a slicing structure. Experimental results are shown.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133613295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The authors formulate necessary conditions for predictive process simulation: physically-based models and tuning to manufacturing data, which are essential for CAM (computer-aided manufacturing) applications. They illustrate these predictive capabilities by applying the statistically based IC fabrication simulator FABRICS to the outcome of an industrial, scaled-down CMOS fabrication process. From the accuracy of the results, it is evident that the process simulation system based on physical models can be tuned to a desired accuracy.<>
{"title":"Statistical process simulation for CAD/CAM","authors":"P. K. Mozumder, A. Strojwas, D. Bell","doi":"10.1109/CICC.1988.20860","DOIUrl":"https://doi.org/10.1109/CICC.1988.20860","url":null,"abstract":"The authors formulate necessary conditions for predictive process simulation: physically-based models and tuning to manufacturing data, which are essential for CAM (computer-aided manufacturing) applications. They illustrate these predictive capabilities by applying the statistically based IC fabrication simulator FABRICS to the outcome of an industrial, scaled-down CMOS fabrication process. From the accuracy of the results, it is evident that the process simulation system based on physical models can be tuned to a desired accuracy.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133636865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Yamaguchi, Y. Yu, E. Lane, J. Lee, E. Patton, R. D. Herman, D. Ahrendt, V. Drobny, V. Garuts
A high-speed self-aligned double-polysilicon emitter/base bipolar technology has been developed by using boron and arsenic diffusions through an emitter polysilicon film (borosenic-poly process) combined with a coupling-base boron implantation. Use of the borosenic-poly process produces a transistor base width of less than 100 AA and an emitter-to-base reverse leakage current of approximately 70 pA. The coupling-base boron implant significantly improves a wide variation in emitter-to-collector periphery punchthrough voltage without degrading the emitter-to-base breakdown voltage, current gain, cutoff frequency, and the ECL (emitter-coupled logic) gate delay time. A deep trench isolation 4 mu m deep and 1.2 mu m wide reduces the collector-to-substrate capacitance to 9 fF, while maintaining a transistor-to-transistor isolation voltage of greater than 25 V. The ECL gate delay time is 70 ps for a fan-out of one and 93 ps for a fan-out of three at a gate current of 400 mu A. Diagnostic 4-bit and 5-bit A-D (analog-to-digital) converters demonstrate sampling rate of 1.5 GS/s and 1.0 GS/s, respectively, without using a sample-and-hold circuit.<>
{"title":"70 ps ECL gate Si bipolar technology using Borosenic-poly process with coupling-base implant","authors":"T. Yamaguchi, Y. Yu, E. Lane, J. Lee, E. Patton, R. D. Herman, D. Ahrendt, V. Drobny, V. Garuts","doi":"10.1109/CICC.1988.20914","DOIUrl":"https://doi.org/10.1109/CICC.1988.20914","url":null,"abstract":"A high-speed self-aligned double-polysilicon emitter/base bipolar technology has been developed by using boron and arsenic diffusions through an emitter polysilicon film (borosenic-poly process) combined with a coupling-base boron implantation. Use of the borosenic-poly process produces a transistor base width of less than 100 AA and an emitter-to-base reverse leakage current of approximately 70 pA. The coupling-base boron implant significantly improves a wide variation in emitter-to-collector periphery punchthrough voltage without degrading the emitter-to-base breakdown voltage, current gain, cutoff frequency, and the ECL (emitter-coupled logic) gate delay time. A deep trench isolation 4 mu m deep and 1.2 mu m wide reduces the collector-to-substrate capacitance to 9 fF, while maintaining a transistor-to-transistor isolation voltage of greater than 25 V. The ECL gate delay time is 70 ps for a fan-out of one and 93 ps for a fan-out of three at a gate current of 400 mu A. Diagnostic 4-bit and 5-bit A-D (analog-to-digital) converters demonstrate sampling rate of 1.5 GS/s and 1.0 GS/s, respectively, without using a sample-and-hold circuit.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133796188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Three electrostatic discharge (ESD) models are examined: the human body model, the charged-device model, and the machine model. Basic principles and operation of integrated circuit device protection are presented. The three common ESD failure mechanisms, conductor fusing, junction spiking, and dielectric breakdown are described. Protection structure requirements are discussed, and an optimized structure for CMOS is presented.<>
{"title":"ESD protection structure issues and design for custom integrated circuits","authors":"L. Avery","doi":"10.1109/CICC.1988.20942","DOIUrl":"https://doi.org/10.1109/CICC.1988.20942","url":null,"abstract":"Three electrostatic discharge (ESD) models are examined: the human body model, the charged-device model, and the machine model. Basic principles and operation of integrated circuit device protection are presented. The three common ESD failure mechanisms, conductor fusing, junction spiking, and dielectric breakdown are described. Protection structure requirements are discussed, and an optimized structure for CMOS is presented.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133984166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Presents a highly automated design process for the prelayout phase of ASIC (application-specific integrated circuit) system development. The process is divided into four major activities: design capture, design for testability, design verification, and test generation. The authors cover each of these in turn, discussing the reasons for their approach, the role of automation in each activity, and gains realized in several production developments.<>
{"title":"A highly automated design system for rapid development from architecture to ASICs","authors":"D. A. Pierce, C. Stroud","doi":"10.1109/CICC.1988.20783","DOIUrl":"https://doi.org/10.1109/CICC.1988.20783","url":null,"abstract":"Presents a highly automated design process for the prelayout phase of ASIC (application-specific integrated circuit) system development. The process is divided into four major activities: design capture, design for testability, design verification, and test generation. The authors cover each of these in turn, discussing the reasons for their approach, the role of automation in each activity, and gains realized in several production developments.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132715871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Sumi, N. Kai, S. Tanaka, T. Minagawa, I. Nagashima, T. Hamai, J. Mori
A graphic processor, featuring 320-Mb/s bit BLT (bit boundary block transfer) speed, was developed using a novel memory cycle scheme. The key to the system design is a C/Unix-based RTL simulator program, which replaced breadboard hardware. The authors describe the BMCP architecture, the design step, and the design methodology.<>
{"title":"Bit map control processor (BMCP) design","authors":"M. Sumi, N. Kai, S. Tanaka, T. Minagawa, I. Nagashima, T. Hamai, J. Mori","doi":"10.1109/CICC.1988.20826","DOIUrl":"https://doi.org/10.1109/CICC.1988.20826","url":null,"abstract":"A graphic processor, featuring 320-Mb/s bit BLT (bit boundary block transfer) speed, was developed using a novel memory cycle scheme. The key to the system design is a C/Unix-based RTL simulator program, which replaced breadboard hardware. The authors describe the BMCP architecture, the design step, and the design methodology.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133273501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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