H. Yamada, Y. Murata, T. Maeda, R. Ikeda, K. Motohashi, K. Takahashi
A string search engine for real-time address filtering (SSEAF) LSI is developed for 800-Mb/s local area networks (LANs). The SSEAF LSI contains a 16-kb (64-bit*256-word) content-addressable memory (CAM) which can store 256 workstation addresses. Simultaneously carried out within 80 ns in the CAM are both a comparison of a 64-bit destination address in an incoming data bucket with 256 stored addresses and the generation of any matched addresses. About 243 K MOSFETs are integrated on an 8.36-mm*8.5-mm chip using a double-metal 1.3- mu m CMOS fabrication process.<>
针对800mb /s的局域网，开发了一种用于实时地址过滤的字符串搜索引擎LSI (SSEAF)。SSEAF LSI包含一个16 kb(64位*256字)内容可寻址存储器(CAM)，可存储256个工作站地址。在80ns内CAM中同时执行的是传入数据桶中具有256个存储地址的64位目的地址的比较和任何匹配地址的生成。采用双金属1.3 μ m CMOS制造工艺，在8.36 mm*8.5 mm芯片上集成了约243 K mosfet。
{"title":"Real-time string search engine LSI for 800-Mbit/sec LANs","authors":"H. Yamada, Y. Murata, T. Maeda, R. Ikeda, K. Motohashi, K. Takahashi","doi":"10.1109/CICC.1988.20910","DOIUrl":"https://doi.org/10.1109/CICC.1988.20910","url":null,"abstract":"A string search engine for real-time address filtering (SSEAF) LSI is developed for 800-Mb/s local area networks (LANs). The SSEAF LSI contains a 16-kb (64-bit*256-word) content-addressable memory (CAM) which can store 256 workstation addresses. Simultaneously carried out within 80 ns in the CAM are both a comparison of a 64-bit destination address in an incoming data bucket with 256 stored addresses and the generation of any matched addresses. About 243 K MOSFETs are integrated on an 8.36-mm*8.5-mm chip using a double-metal 1.3- mu m CMOS fabrication process.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127493725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Hui, A. Wong, R. Szeto, S. Yeh, C. Kao, D. Wong, Y. Tse
A family of third-generation compacted arrays with up to 237 K gates has been developed using a channelless architecture. 1- mu m HCMOS (high-speed complementary metal-oxide semiconductor) technology with 0.75- mu m effective channel length was used to fabricate the device. Complex designs with up to 100 K utilized gates can be implemented on a single chip using this technology. Switching performance of 400 ps is achieved on two input NAND gates with typical loading.<>
{"title":"A sub half-ns 237 K gate CMOS compacted array","authors":"A. Hui, A. Wong, R. Szeto, S. Yeh, C. Kao, D. Wong, Y. Tse","doi":"10.1109/CICC.1988.20899","DOIUrl":"https://doi.org/10.1109/CICC.1988.20899","url":null,"abstract":"A family of third-generation compacted arrays with up to 237 K gates has been developed using a channelless architecture. 1- mu m HCMOS (high-speed complementary metal-oxide semiconductor) technology with 0.75- mu m effective channel length was used to fabricate the device. Complex designs with up to 100 K utilized gates can be implemented on a single chip using this technology. Switching performance of 400 ps is achieved on two input NAND gates with typical loading.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125010394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A novel charge-based intrinsic capacitance model of short-channel MOSFETs is proposed. Two-dimensional field-induced mobility degradation, velocity saturation, and short-channel effects are included in the model. The simulation results clearly show the importance of the field-induced effects. The method can be used to link a device simulator and a circuit simulator for accurate timing calculation in both digital and analogue MOS circuits.<>
{"title":"An accurate two-dimensional intrinsic capacitance model of short channel MOSFETs","authors":"S. Chung","doi":"10.1109/CICC.1988.20857","DOIUrl":"https://doi.org/10.1109/CICC.1988.20857","url":null,"abstract":"A novel charge-based intrinsic capacitance model of short-channel MOSFETs is proposed. Two-dimensional field-induced mobility degradation, velocity saturation, and short-channel effects are included in the model. The simulation results clearly show the importance of the field-induced effects. The method can be used to link a device simulator and a circuit simulator for accurate timing calculation in both digital and analogue MOS circuits.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121126244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A novel pipeline digital-to-analog converter (DAC) configuration is described which is based on switched-capacitor techniques. The circuit needs only n+1 capacitors and 4n+1 capacitors and 4n+2 switches for n-bit D/A (digital-to-analog) conversion. The configuration is fast and accurate and requires a small chip area. An experimental 10-bit DAC prototype has been fabricated using a 3- mu m CMOS process. The results show that it can achieve high-speed and high-accuracy operation without any trimming.<>
介绍了一种基于开关电容技术的新型流水线数模转换器(DAC)结构。该电路只需要n+1个电容器和4n+1个电容器和4n+2个开关进行n位D/A(数模)转换。配置快速、准确，芯片面积小。采用3 μ m CMOS工艺制作了一个10位DAC的实验样机。实验结果表明，该系统可以实现高速、高精度的运行，不需要任何修边
{"title":"A quasi-passive CMOS pipeline D/A converter","authors":"F.-J. Wang, G. Temes, S. Law","doi":"10.1109/CICC.1988.20890","DOIUrl":"https://doi.org/10.1109/CICC.1988.20890","url":null,"abstract":"A novel pipeline digital-to-analog converter (DAC) configuration is described which is based on switched-capacitor techniques. The circuit needs only n+1 capacitors and 4n+1 capacitors and 4n+2 switches for n-bit D/A (digital-to-analog) conversion. The configuration is fast and accurate and requires a small chip area. An experimental 10-bit DAC prototype has been fabricated using a 3- mu m CMOS process. The results show that it can achieve high-speed and high-accuracy operation without any trimming.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129942532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Leung, M. Chen, W. Cochran, M. Thoma, B. Grugett, T. Yang, D. R. Stone, N. Tsai
A fifth-generation, high-performance twin-tub, two-level metal, submicrometer CMOS technology has been developed for 5-V custom VLSI applications. This technology utilizes fabrication techniques of high-pressure oxidation (HIPOX) lightly doped drain (LDD) for both n and p channels, titanium self-aligned silicide (SALICIDE), and plasma-enhanced low-temperature oxide for intermetal dielectrics. The authors review the front-end process and elaborate on techniques involved in titanium salicide formation, the two-level metal process, and the temperature sensitivity of device parameters. In addition, high-performance circuits developed with this technology are demonstrated.<>
{"title":"A high performance submicron twin tub V technology for custom VLSI applications","authors":"C. Leung, M. Chen, W. Cochran, M. Thoma, B. Grugett, T. Yang, D. R. Stone, N. Tsai","doi":"10.1109/CICC.1988.20930","DOIUrl":"https://doi.org/10.1109/CICC.1988.20930","url":null,"abstract":"A fifth-generation, high-performance twin-tub, two-level metal, submicrometer CMOS technology has been developed for 5-V custom VLSI applications. This technology utilizes fabrication techniques of high-pressure oxidation (HIPOX) lightly doped drain (LDD) for both n and p channels, titanium self-aligned silicide (SALICIDE), and plasma-enhanced low-temperature oxide for intermetal dielectrics. The authors review the front-end process and elaborate on techniques involved in titanium salicide formation, the two-level metal process, and the temperature sensitivity of device parameters. In addition, high-performance circuits developed with this technology are demonstrated.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134452046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A novel method is presented for building high-performance pin electronics circuitry using conventional CMOS technology. To demonstrate the feasibility of these circuit techniques, a prototype processing-element chip consisting of four I/O channels was designed in a 2- mu m double-metal CMOS technology. It contains 13 K transistors in a die size of 3.9 mm*5.3 mm. Running at 33 Mvectors/s, the chip dissipates 125 mW with a 5-V supply. The authors feel that it is possible to build practical integrated pin electronics for functional VLSI testers with a technology only as good as that of the design under test.<>
{"title":"Integrated pin electronics for VLSI functional testers","authors":"J. Gasbarro, M. Horowitz","doi":"10.1109/CICC.1988.20878","DOIUrl":"https://doi.org/10.1109/CICC.1988.20878","url":null,"abstract":"A novel method is presented for building high-performance pin electronics circuitry using conventional CMOS technology. To demonstrate the feasibility of these circuit techniques, a prototype processing-element chip consisting of four I/O channels was designed in a 2- mu m double-metal CMOS technology. It contains 13 K transistors in a die size of 3.9 mm*5.3 mm. Running at 33 Mvectors/s, the chip dissipates 125 mW with a 5-V supply. The authors feel that it is possible to build practical integrated pin electronics for functional VLSI testers with a technology only as good as that of the design under test.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131007333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A novel reliability simulator and its associated circuit-level degradation models with automated parameter extraction procedures for VLSI circuits have been developed. This circuit reliability modeling and simulation environment can serve as a bridge between the system and device reliability. Performance and lifetime of digital and analog ICs can be optimized through the usage of this reliability simulator.<>
{"title":"RELY: a reliability simulator for VLSI circuits","authors":"Wen-Jay Hsu, C. Shih, B. Sheu","doi":"10.1109/CICC.1988.20945","DOIUrl":"https://doi.org/10.1109/CICC.1988.20945","url":null,"abstract":"A novel reliability simulator and its associated circuit-level degradation models with automated parameter extraction procedures for VLSI circuits have been developed. This circuit reliability modeling and simulation environment can serve as a bridge between the system and device reliability. Performance and lifetime of digital and analog ICs can be optimized through the usage of this reliability simulator.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133731138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Semiconductor packaging is being driven in two major directions by the demand for increased system operating speeds and higher functional density. Most prominent is the trend toward higher functional integration on the die, resulting in both a larger die size and decreased feature size. The other major trend is the mechanical integration of multiple devices in a single package. These trends require improved package-design methods that include electrical and thermomechanical modeling, improved data on material properties that drive package reliability, and novel methods of reliability testing to meet the very low defect levels that will be required in next-generation electronic equipment.<>
{"title":"Trends in semiconductor packaging, a merchant house view","authors":"H. Test","doi":"10.1109/CICC.1988.20919","DOIUrl":"https://doi.org/10.1109/CICC.1988.20919","url":null,"abstract":"Semiconductor packaging is being driven in two major directions by the demand for increased system operating speeds and higher functional density. Most prominent is the trend toward higher functional integration on the die, resulting in both a larger die size and decreased feature size. The other major trend is the mechanical integration of multiple devices in a single package. These trends require improved package-design methods that include electrical and thermomechanical modeling, improved data on material properties that drive package reliability, and novel methods of reliability testing to meet the very low defect levels that will be required in next-generation electronic equipment.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129429296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. McGlinchey, S. Pietkiewicz, R. Frank, P. Schmidt-Andersen, F. Hansen
A medical data acquisition system chip has been integrated using a BiMOS (bipolar metal-oxide semiconductor) process. This chip integrates a low-noise bipolar instrumentation amplifier, a programmable switched-capacitor notch filter, an 11-bit ADC (analog-to-digital converter), a 7-bit DAC, and an asynchronous serial interface. Biomedical signals such as ECG (electrocardiogram), EEG (electroencephalogram), invasive blood pressure, temperature, respiration, and cardiac output are picked up by transducers, probes, and electrodes. Typical signal levels are 50 mu Vp-p for the EEG and 1 mV p-p for the ECG. These low level biological signals are converted into voltages or currents.<>
{"title":"A programmable medical data acquisition system chip","authors":"G. McGlinchey, S. Pietkiewicz, R. Frank, P. Schmidt-Andersen, F. Hansen","doi":"10.1109/CICC.1988.20832","DOIUrl":"https://doi.org/10.1109/CICC.1988.20832","url":null,"abstract":"A medical data acquisition system chip has been integrated using a BiMOS (bipolar metal-oxide semiconductor) process. This chip integrates a low-noise bipolar instrumentation amplifier, a programmable switched-capacitor notch filter, an 11-bit ADC (analog-to-digital converter), a 7-bit DAC, and an asynchronous serial interface. Biomedical signals such as ECG (electrocardiogram), EEG (electroencephalogram), invasive blood pressure, temperature, respiration, and cardiac output are picked up by transducers, probes, and electrodes. Typical signal levels are 50 mu Vp-p for the EEG and 1 mV p-p for the ECG. These low level biological signals are converted into voltages or currents.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133006825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An analog interface circuit (AIC) is described that can be used with a digital signal-processing element to implement high-speed (up to 14-kHz) modems. It includes receive/transmit functions, an auxiliary DAC (digital-to-analog converter), audio monitoring, call progress tone detection, loopbacks, and a hybrid function. The chip is fabricated using a 3- mu m double-polysilicon CMOS n-well process. It is housed in a 28-pin package and the die size measures 225 mils*238 mils. It uses +or-5.0+or-0.5 V power supply and consumes 150 mW of power at 10 V. The transmit and receive filters have a PSRR (power supply rejection ratio) of 35 dB at 1 kHz and the idle channel noise (measured by grounding the filter input) of 10 dBrnCo.<>
{"title":"An analog interface circuit (AIC) for high-speed modems","authors":"S. Wong, K. Titizer, B. Fotouhi, R. Gregorian","doi":"10.1109/CICC.1988.20939","DOIUrl":"https://doi.org/10.1109/CICC.1988.20939","url":null,"abstract":"An analog interface circuit (AIC) is described that can be used with a digital signal-processing element to implement high-speed (up to 14-kHz) modems. It includes receive/transmit functions, an auxiliary DAC (digital-to-analog converter), audio monitoring, call progress tone detection, loopbacks, and a hybrid function. The chip is fabricated using a 3- mu m double-polysilicon CMOS n-well process. It is housed in a 28-pin package and the die size measures 225 mils*238 mils. It uses +or-5.0+or-0.5 V power supply and consumes 150 mW of power at 10 V. The transmit and receive filters have a PSRR (power supply rejection ratio) of 35 dB at 1 kHz and the idle channel noise (measured by grounding the filter input) of 10 dBrnCo.<<ETX>>","PeriodicalId":313270,"journal":{"name":"Proceedings of the IEEE 1988 Custom Integrated Circuits Conference","volume":"113 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130145570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：