Pub Date : 2011-01-25DOI: 10.1109/ASPDAC.2011.5722316
Yu-Han Yuan, Wei-Ming Chen, Hsi-Pin Ma
An efficient and practicable MIMO transceiver in which transmitter antenna selection is applied to geometric mean decomposition (GMD) which is combined with Tomlinson-Harashima Precoder (THP) in TDD system is implemented. The proposed work can save more than 60% computational complexity at the handset compared with that of the GMD scheme is comparable to the conventional linear transceiver schemes. From the simulation results, the proposed transceiver can achieve about 7 dB SNR improvement over the open-loop VBLAST counterparts under i.i.d. channel. Finally, a MIMO joint transceiver is implemented on a SoC platform which is realized to do the hardware/software (HW/SW) co-verification strategy to debug the proposed architecture. In this paper, which introduces the figure file to be the transmission media. Designer could verify the decoded results in various environment by liquid crystal display (LCD) panel.
{"title":"Design and implementation of a high performance closed-loop MIMO communications with ultra low complexity handset","authors":"Yu-Han Yuan, Wei-Ming Chen, Hsi-Pin Ma","doi":"10.1109/ASPDAC.2011.5722316","DOIUrl":"https://doi.org/10.1109/ASPDAC.2011.5722316","url":null,"abstract":"An efficient and practicable MIMO transceiver in which transmitter antenna selection is applied to geometric mean decomposition (GMD) which is combined with Tomlinson-Harashima Precoder (THP) in TDD system is implemented. The proposed work can save more than 60% computational complexity at the handset compared with that of the GMD scheme is comparable to the conventional linear transceiver schemes. From the simulation results, the proposed transceiver can achieve about 7 dB SNR improvement over the open-loop VBLAST counterparts under i.i.d. channel. Finally, a MIMO joint transceiver is implemented on a SoC platform which is realized to do the hardware/software (HW/SW) co-verification strategy to debug the proposed architecture. In this paper, which introduces the figure file to be the transmission media. Designer could verify the decoded results in various environment by liquid crystal display (LCD) panel.","PeriodicalId":316253,"journal":{"name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","volume":"345 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121658471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-01-25DOI: 10.1109/ASPDAC.2011.5722172
Xuexin Liu, Hao Yu, Jacob Relles, S. Tan
The recent multi/many-core CPUs or GPUs have provided an ideal parallel computing platform to accelerate the time-consuming analysis of radio-frequency/millimeter-wave (RF/ MM) integrated circuit (IC). This paper develops a structured shooting algorithm that can fully take advantage of parallelism in periodic steady state (PSS) analysis. Utilizing periodic structure of the state matrix of RF/ MM-IC simulation, a cyclic-block-structured shooting-Newton method has been parallelized and mapped onto recent GPU platforms. We first present the formulation of the parallel cyclic-block-structured shooting-Newton algorithm, called periodic Arnoldi shooting method. Then we will present its parallel implementation details on GPU. Results from several industrial examples show that the structured parallel shooting-Newton method on Tesla's GPU can lead to speedups of more than 20× compared to the state-of-the-art implicit GMRES methods under the same accuracy on the CPU.
{"title":"A structured parallel periodic Arnoldi shooting algorithm for RF-PSS analysis based on GPU platforms","authors":"Xuexin Liu, Hao Yu, Jacob Relles, S. Tan","doi":"10.1109/ASPDAC.2011.5722172","DOIUrl":"https://doi.org/10.1109/ASPDAC.2011.5722172","url":null,"abstract":"The recent multi/many-core CPUs or GPUs have provided an ideal parallel computing platform to accelerate the time-consuming analysis of radio-frequency/millimeter-wave (RF/ MM) integrated circuit (IC). This paper develops a structured shooting algorithm that can fully take advantage of parallelism in periodic steady state (PSS) analysis. Utilizing periodic structure of the state matrix of RF/ MM-IC simulation, a cyclic-block-structured shooting-Newton method has been parallelized and mapped onto recent GPU platforms. We first present the formulation of the parallel cyclic-block-structured shooting-Newton algorithm, called periodic Arnoldi shooting method. Then we will present its parallel implementation details on GPU. Results from several industrial examples show that the structured parallel shooting-Newton method on Tesla's GPU can lead to speedups of more than 20× compared to the state-of-the-art implicit GMRES methods under the same accuracy on the CPU.","PeriodicalId":316253,"journal":{"name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128013644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-01-25DOI: 10.1109/ASPDAC.2011.5722304
Kuan-Yu Lin, Hong-Ting Lin, Tsung-Yi Ho
Power consumption is known to be a crucial issue in current IC designs. To tackle this problem, multiple dynamic supply voltage (MDSV) designs are proposed as an efficient solution in modern IC designs. However, the increasing variability of clock skew during the switching of power modes leads to an increase in the complication of clock skew reduction in MDSV designs. In this paper, we propose a tunable clock tree structure by adopting the adjustable delay buffers (ADBs). The ADBs can be used to produce additional delays, hence the clock latencies and skew become tunable in a clock tree. Importing a buffered clock tree, the ADBs with delay value assignments are inserted to reduce clock skew in MDSV designs. An efficient algorithm of ADB insertion for the minimization of clock skew, area, and runtime in MDSV designs has been presented. Comparing with the state-of-the-art algorithm, experimental results show maximum 42.40% area overhead improvement and 117.84× runtime speedup.
{"title":"An efficient algorithm of adjustable delay buffer insertion for clock skew minimization in multiple dynamic supply voltage designs","authors":"Kuan-Yu Lin, Hong-Ting Lin, Tsung-Yi Ho","doi":"10.1109/ASPDAC.2011.5722304","DOIUrl":"https://doi.org/10.1109/ASPDAC.2011.5722304","url":null,"abstract":"Power consumption is known to be a crucial issue in current IC designs. To tackle this problem, multiple dynamic supply voltage (MDSV) designs are proposed as an efficient solution in modern IC designs. However, the increasing variability of clock skew during the switching of power modes leads to an increase in the complication of clock skew reduction in MDSV designs. In this paper, we propose a tunable clock tree structure by adopting the adjustable delay buffers (ADBs). The ADBs can be used to produce additional delays, hence the clock latencies and skew become tunable in a clock tree. Importing a buffered clock tree, the ADBs with delay value assignments are inserted to reduce clock skew in MDSV designs. An efficient algorithm of ADB insertion for the minimization of clock skew, area, and runtime in MDSV designs has been presented. Comparing with the state-of-the-art algorithm, experimental results show maximum 42.40% area overhead improvement and 117.84× runtime speedup.","PeriodicalId":316253,"journal":{"name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","volume":"200 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115577440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-01-25DOI: 10.1109/ASPDAC.2011.5722163
Wen Fan, O. Choy
Robust, efficient and low complexity design methodologies for high speed multi-band orthogonal frequency division multiplexing ultra-wideband (MB-OFDM UWB) is presented. The proposed design is implemented in 0.13μm CMOS technology with the core area of 2.66mm × 0.94mm. Operating at 132MHz clock frequency, the estimated power consumption is 170mW.
{"title":"Robust and efficient baseband receiver design for MB-OFDM UWB system","authors":"Wen Fan, O. Choy","doi":"10.1109/ASPDAC.2011.5722163","DOIUrl":"https://doi.org/10.1109/ASPDAC.2011.5722163","url":null,"abstract":"Robust, efficient and low complexity design methodologies for high speed multi-band orthogonal frequency division multiplexing ultra-wideband (MB-OFDM UWB) is presented. The proposed design is implemented in 0.13μm CMOS technology with the core area of 2.66mm × 0.94mm. Operating at 132MHz clock frequency, the estimated power consumption is 170mW.","PeriodicalId":316253,"journal":{"name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114315343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-01-25DOI: 10.1109/ASPDAC.2011.5722203
M. Fujita
Due to the highly complicated control structures of modern processors as well as ASICs, some of the logical bugs may easily escape from the pre-silicon verification processes and remain into the silicon. Those bugs can only be found after the chip has been fabricated and used in the systems. So post-silicon debugging is becoming a essential part of the design flows for complicated and large system designs. This paper summarizes our research activities targeting post-silicon debugging for highly complicated pipeline processors as well as large ASICs. We have been working on the following three topics: 1) Translation of chip level error traces to high and abstracted level so that more efficient simulation as well as formal analysis become possible, 2) Utilize experiences on formal verification and debugging processes for pipelined processors for debugging and in-fields rectification of chips, and 3) Apply incremental high level synthesis for efficient in-fields rectifications of ASIC designs. Our approaches utilize high level or abstracted design information as much as possible to make things more efficient and effective. In this paper we briefly present the techniques for the first two topics.
{"title":"Utilizing high level design information to speed up post-silicon debugging","authors":"M. Fujita","doi":"10.1109/ASPDAC.2011.5722203","DOIUrl":"https://doi.org/10.1109/ASPDAC.2011.5722203","url":null,"abstract":"Due to the highly complicated control structures of modern processors as well as ASICs, some of the logical bugs may easily escape from the pre-silicon verification processes and remain into the silicon. Those bugs can only be found after the chip has been fabricated and used in the systems. So post-silicon debugging is becoming a essential part of the design flows for complicated and large system designs. This paper summarizes our research activities targeting post-silicon debugging for highly complicated pipeline processors as well as large ASICs. We have been working on the following three topics: 1) Translation of chip level error traces to high and abstracted level so that more efficient simulation as well as formal analysis become possible, 2) Utilize experiences on formal verification and debugging processes for pipelined processors for debugging and in-fields rectification of chips, and 3) Apply incremental high level synthesis for efficient in-fields rectifications of ASIC designs. Our approaches utilize high level or abstracted design information as much as possible to make things more efficient and effective. In this paper we briefly present the techniques for the first two topics.","PeriodicalId":316253,"journal":{"name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114644031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-01-25DOI: 10.1109/ASPDAC.2011.5722191
M. Rawlins, A. Gordon-Ross
Even though much previous work explores varying instruction cache optimization techniques individually, little work explores the combined effects of these techniques (i.e., do they complement or obviate each other). In this paper we explore the interaction of three optimizations: loop caching, cache tuning, and code compression. Results show that loop caching increases energy savings by as much as 26% compared to cache tuning alone and reduces decompression energy by as much as 73%.
{"title":"On the interplay of loop caching, code compression, and cache configuration","authors":"M. Rawlins, A. Gordon-Ross","doi":"10.1109/ASPDAC.2011.5722191","DOIUrl":"https://doi.org/10.1109/ASPDAC.2011.5722191","url":null,"abstract":"Even though much previous work explores varying instruction cache optimization techniques individually, little work explores the combined effects of these techniques (i.e., do they complement or obviate each other). In this paper we explore the interaction of three optimizations: loop caching, cache tuning, and code compression. Results show that loop caching increases energy savings by as much as 26% compared to cache tuning alone and reduces decompression energy by as much as 73%.","PeriodicalId":316253,"journal":{"name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123285847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-01-25DOI: 10.1109/ASPDAC.2011.5722169
M. Hafiz, N. Sasaki, K. Kimoto, T. Kikkawa
A simple non-coherent solution to UWB-IR communication has been presented here. An all digital differential transmitter, developed in a 65 nm CMOS technology and a simple receiver, developed in a 180 nm CMOS technology, for detecting the received differential signal are demonstrated in the work. Though the transmitter and the receiver have been developed in two different technologies, the main objective of this paper is to show the effectiveness of such a non-coherent solution for BPSK modulated UWB-IR communication.
{"title":"A simple non-coherent solution to the UWB-IR communication","authors":"M. Hafiz, N. Sasaki, K. Kimoto, T. Kikkawa","doi":"10.1109/ASPDAC.2011.5722169","DOIUrl":"https://doi.org/10.1109/ASPDAC.2011.5722169","url":null,"abstract":"A simple non-coherent solution to UWB-IR communication has been presented here. An all digital differential transmitter, developed in a 65 nm CMOS technology and a simple receiver, developed in a 180 nm CMOS technology, for detecting the received differential signal are demonstrated in the work. Though the transmitter and the receiver have been developed in two different technologies, the main objective of this paper is to show the effectiveness of such a non-coherent solution for BPSK modulated UWB-IR communication.","PeriodicalId":316253,"journal":{"name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124250363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-01-25DOI: 10.1109/ASPDAC.2011.5722295
Jen-Yi Wuu, F. Pikus, A. Torres, M. Marek-Sadowska
Printability of layout objects becomes increasingly dependent on neighboring shapes within a larger and larger context window. In this paper, we propose a two-level hotspot pattern classification methodology that examines both central and peripheral patterns. Accuracy and runtime enhancement techniques are proposed, making our detection methodology robust and efficient as a fast physical verification tool that can be applied during early design stages to large-scale designs. We position our method as an approximate detection solution, similar to pattern matching-based tools widely adopted by the industry. In addition, our analyses of classification results reveal that the majority of non-hotspots falsely predicted as hotspots have printed CD barely over the minimum allowable CD threshold. Our method is verified on several 45 nm and 32 nm industrial designs.
{"title":"Rapid layout pattern classification","authors":"Jen-Yi Wuu, F. Pikus, A. Torres, M. Marek-Sadowska","doi":"10.1109/ASPDAC.2011.5722295","DOIUrl":"https://doi.org/10.1109/ASPDAC.2011.5722295","url":null,"abstract":"Printability of layout objects becomes increasingly dependent on neighboring shapes within a larger and larger context window. In this paper, we propose a two-level hotspot pattern classification methodology that examines both central and peripheral patterns. Accuracy and runtime enhancement techniques are proposed, making our detection methodology robust and efficient as a fast physical verification tool that can be applied during early design stages to large-scale designs. We position our method as an approximate detection solution, similar to pattern matching-based tools widely adopted by the industry. In addition, our analyses of classification results reveal that the majority of non-hotspots falsely predicted as hotspots have printed CD barely over the minimum allowable CD threshold. Our method is verified on several 45 nm and 32 nm industrial designs.","PeriodicalId":316253,"journal":{"name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129276134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-01-25DOI: 10.1109/ASPDAC.2011.5722166
Chenchang Zhan, W. Ki
An output-capacitor-free adaptively biased low-dropout regulator with transient enhancement (ABTE LDR) is proposed. Techniques of Q-reduction compensation, adaptive biasing, and transient enhancement achieve low-voltage high-precision regulation with low quiescent current consumption while significantly improving the line and load transient responses and power supply rejections. The features of the ABTE LDR are experimentally verified by a 0.35-μm CMOS prototype.
{"title":"An adaptively biased low-dropout regulator with transient enhancement","authors":"Chenchang Zhan, W. Ki","doi":"10.1109/ASPDAC.2011.5722166","DOIUrl":"https://doi.org/10.1109/ASPDAC.2011.5722166","url":null,"abstract":"An output-capacitor-free adaptively biased low-dropout regulator with transient enhancement (ABTE LDR) is proposed. Techniques of Q-reduction compensation, adaptive biasing, and transient enhancement achieve low-voltage high-precision regulation with low quiescent current consumption while significantly improving the line and load transient responses and power supply rejections. The features of the ABTE LDR are experimentally verified by a 0.35-μm CMOS prototype.","PeriodicalId":316253,"journal":{"name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129384694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-01-25DOI: 10.1109/ASPDAC.2011.5722209
Chia-Jen Chang, Pao-Jen Huang, Tai-Chen Chen, C. Liu
The 3D IC is an emerging technology. The primary emphasis on 3D-IC routing is the interface issues across dies. To handle the interface issue of connections, the inter-die routing, which uses micro bumps and two single-layer RDLs (Re-Distribution Layers) to achieve the connection between adjacent dies, is adopted. In this paper, we present an inter-die routing algorithm for 3D ICs with a pre-defined netlist. Our algorithm is based on integer linear programming (ILP) and adopts a two-stage technique of micro-bump assignment followed by non-regular RDL routing. First, the micro-bump assignment selects suitable micro-bumps for the pre-defined netlist such that no crossing problem exists inside the bounding boxes of each net. After the micro-bump assignment, the netlist is divided into two sub-netlists, one is for the upper RDL and the other is for the lower RDL. Second, the non-regular RDL routing determines minimum and non-crossing global paths for sub-netlists in the upper and lower RDLs individually. Experimental results show that our approach can obtain optimal wirelength and achieve 100% routability under reasonable CPU times.
{"title":"ILP-based inter-die routing for 3D ICs","authors":"Chia-Jen Chang, Pao-Jen Huang, Tai-Chen Chen, C. Liu","doi":"10.1109/ASPDAC.2011.5722209","DOIUrl":"https://doi.org/10.1109/ASPDAC.2011.5722209","url":null,"abstract":"The 3D IC is an emerging technology. The primary emphasis on 3D-IC routing is the interface issues across dies. To handle the interface issue of connections, the inter-die routing, which uses micro bumps and two single-layer RDLs (Re-Distribution Layers) to achieve the connection between adjacent dies, is adopted. In this paper, we present an inter-die routing algorithm for 3D ICs with a pre-defined netlist. Our algorithm is based on integer linear programming (ILP) and adopts a two-stage technique of micro-bump assignment followed by non-regular RDL routing. First, the micro-bump assignment selects suitable micro-bumps for the pre-defined netlist such that no crossing problem exists inside the bounding boxes of each net. After the micro-bump assignment, the netlist is divided into two sub-netlists, one is for the upper RDL and the other is for the lower RDL. Second, the non-regular RDL routing determines minimum and non-crossing global paths for sub-netlists in the upper and lower RDLs individually. Experimental results show that our approach can obtain optimal wirelength and achieve 100% routability under reasonable CPU times.","PeriodicalId":316253,"journal":{"name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129467837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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