Pub Date : 2011-01-25DOI: 10.1109/ASPDAC.2011.5722316
Yu-Han Yuan, Wei-Ming Chen, Hsi-Pin Ma
An efficient and practicable MIMO transceiver in which transmitter antenna selection is applied to geometric mean decomposition (GMD) which is combined with Tomlinson-Harashima Precoder (THP) in TDD system is implemented. The proposed work can save more than 60% computational complexity at the handset compared with that of the GMD scheme is comparable to the conventional linear transceiver schemes. From the simulation results, the proposed transceiver can achieve about 7 dB SNR improvement over the open-loop VBLAST counterparts under i.i.d. channel. Finally, a MIMO joint transceiver is implemented on a SoC platform which is realized to do the hardware/software (HW/SW) co-verification strategy to debug the proposed architecture. In this paper, which introduces the figure file to be the transmission media. Designer could verify the decoded results in various environment by liquid crystal display (LCD) panel.
{"title":"Design and implementation of a high performance closed-loop MIMO communications with ultra low complexity handset","authors":"Yu-Han Yuan, Wei-Ming Chen, Hsi-Pin Ma","doi":"10.1109/ASPDAC.2011.5722316","DOIUrl":"https://doi.org/10.1109/ASPDAC.2011.5722316","url":null,"abstract":"An efficient and practicable MIMO transceiver in which transmitter antenna selection is applied to geometric mean decomposition (GMD) which is combined with Tomlinson-Harashima Precoder (THP) in TDD system is implemented. The proposed work can save more than 60% computational complexity at the handset compared with that of the GMD scheme is comparable to the conventional linear transceiver schemes. From the simulation results, the proposed transceiver can achieve about 7 dB SNR improvement over the open-loop VBLAST counterparts under i.i.d. channel. Finally, a MIMO joint transceiver is implemented on a SoC platform which is realized to do the hardware/software (HW/SW) co-verification strategy to debug the proposed architecture. In this paper, which introduces the figure file to be the transmission media. Designer could verify the decoded results in various environment by liquid crystal display (LCD) panel.","PeriodicalId":316253,"journal":{"name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","volume":"345 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121658471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-01-25DOI: 10.1109/ASPDAC.2011.5722172
Xuexin Liu, Hao Yu, Jacob Relles, S. Tan
The recent multi/many-core CPUs or GPUs have provided an ideal parallel computing platform to accelerate the time-consuming analysis of radio-frequency/millimeter-wave (RF/ MM) integrated circuit (IC). This paper develops a structured shooting algorithm that can fully take advantage of parallelism in periodic steady state (PSS) analysis. Utilizing periodic structure of the state matrix of RF/ MM-IC simulation, a cyclic-block-structured shooting-Newton method has been parallelized and mapped onto recent GPU platforms. We first present the formulation of the parallel cyclic-block-structured shooting-Newton algorithm, called periodic Arnoldi shooting method. Then we will present its parallel implementation details on GPU. Results from several industrial examples show that the structured parallel shooting-Newton method on Tesla's GPU can lead to speedups of more than 20× compared to the state-of-the-art implicit GMRES methods under the same accuracy on the CPU.
{"title":"A structured parallel periodic Arnoldi shooting algorithm for RF-PSS analysis based on GPU platforms","authors":"Xuexin Liu, Hao Yu, Jacob Relles, S. Tan","doi":"10.1109/ASPDAC.2011.5722172","DOIUrl":"https://doi.org/10.1109/ASPDAC.2011.5722172","url":null,"abstract":"The recent multi/many-core CPUs or GPUs have provided an ideal parallel computing platform to accelerate the time-consuming analysis of radio-frequency/millimeter-wave (RF/ MM) integrated circuit (IC). This paper develops a structured shooting algorithm that can fully take advantage of parallelism in periodic steady state (PSS) analysis. Utilizing periodic structure of the state matrix of RF/ MM-IC simulation, a cyclic-block-structured shooting-Newton method has been parallelized and mapped onto recent GPU platforms. We first present the formulation of the parallel cyclic-block-structured shooting-Newton algorithm, called periodic Arnoldi shooting method. Then we will present its parallel implementation details on GPU. Results from several industrial examples show that the structured parallel shooting-Newton method on Tesla's GPU can lead to speedups of more than 20× compared to the state-of-the-art implicit GMRES methods under the same accuracy on the CPU.","PeriodicalId":316253,"journal":{"name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128013644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-01-25DOI: 10.1109/ASPDAC.2011.5722169
M. Hafiz, N. Sasaki, K. Kimoto, T. Kikkawa
A simple non-coherent solution to UWB-IR communication has been presented here. An all digital differential transmitter, developed in a 65 nm CMOS technology and a simple receiver, developed in a 180 nm CMOS technology, for detecting the received differential signal are demonstrated in the work. Though the transmitter and the receiver have been developed in two different technologies, the main objective of this paper is to show the effectiveness of such a non-coherent solution for BPSK modulated UWB-IR communication.
{"title":"A simple non-coherent solution to the UWB-IR communication","authors":"M. Hafiz, N. Sasaki, K. Kimoto, T. Kikkawa","doi":"10.1109/ASPDAC.2011.5722169","DOIUrl":"https://doi.org/10.1109/ASPDAC.2011.5722169","url":null,"abstract":"A simple non-coherent solution to UWB-IR communication has been presented here. An all digital differential transmitter, developed in a 65 nm CMOS technology and a simple receiver, developed in a 180 nm CMOS technology, for detecting the received differential signal are demonstrated in the work. Though the transmitter and the receiver have been developed in two different technologies, the main objective of this paper is to show the effectiveness of such a non-coherent solution for BPSK modulated UWB-IR communication.","PeriodicalId":316253,"journal":{"name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124250363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-01-25DOI: 10.1109/ASPDAC.2011.5722283
Junhe Gan, F. Gruian, P. Pop, J. Madsen
This paper presents an approach to the synthesis of low-power fault-tolerant hard real-time applications mapped on distributed heterogeneous embedded systems. Our synthesis approach decides the mapping of tasks to processing elements, as well as the voltage and frequency levels for executing each task, such that transient faults are tolerated, the timing constraints of the application are satisfied, and the energy consumed is minimized. Tasks are scheduled using fixed-priority preemptive scheduling, while replication is used for recovery from multiple transient faults. Addressing energy and reliability simultaneously is especially challenging, since lowering the voltage to reduce the energy consumption has been shown to increase the transient fault rate. We presented a Tabu Search-based approach which uses an energy/reliability trade-off model to find reliable and schedulable implementations with limited energy and hardware resources. We evaluated the algorithm proposed using several synthetic and reallife benchmarks.
{"title":"Energy/reliability trade-offs in fault-tolerant event-triggered distributed embedded systems","authors":"Junhe Gan, F. Gruian, P. Pop, J. Madsen","doi":"10.1109/ASPDAC.2011.5722283","DOIUrl":"https://doi.org/10.1109/ASPDAC.2011.5722283","url":null,"abstract":"This paper presents an approach to the synthesis of low-power fault-tolerant hard real-time applications mapped on distributed heterogeneous embedded systems. Our synthesis approach decides the mapping of tasks to processing elements, as well as the voltage and frequency levels for executing each task, such that transient faults are tolerated, the timing constraints of the application are satisfied, and the energy consumed is minimized. Tasks are scheduled using fixed-priority preemptive scheduling, while replication is used for recovery from multiple transient faults. Addressing energy and reliability simultaneously is especially challenging, since lowering the voltage to reduce the energy consumption has been shown to increase the transient fault rate. We presented a Tabu Search-based approach which uses an energy/reliability trade-off model to find reliable and schedulable implementations with limited energy and hardware resources. We evaluated the algorithm proposed using several synthetic and reallife benchmarks.","PeriodicalId":316253,"journal":{"name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134498936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-01-25DOI: 10.1109/ASPDAC.2011.5722297
Jaehyun Jeong, T. Iizuka, T. Nakura, M. Ikeda, K. Asada
This paper presents an all-digital PMOS and NMOS process variability monitor which utilizes a simple buffer ring with a pulse counter. The proposed circuit monitors the process variability according to a count number of a single pulse which propagates on the buffer ring and a fixed logic level after the pulse vanishes. The proposed circuit has been fabricated in 65nm CMOS process and the measurement results demonstrate that we can monitor the PMOS and NMOS variabilities independently using the proposed monitoring circuit.
{"title":"All-digital PMOS and NMOS process variability monitor utilizing buffer ring with pulse counter","authors":"Jaehyun Jeong, T. Iizuka, T. Nakura, M. Ikeda, K. Asada","doi":"10.1109/ASPDAC.2011.5722297","DOIUrl":"https://doi.org/10.1109/ASPDAC.2011.5722297","url":null,"abstract":"This paper presents an all-digital PMOS and NMOS process variability monitor which utilizes a simple buffer ring with a pulse counter. The proposed circuit monitors the process variability according to a count number of a single pulse which propagates on the buffer ring and a fixed logic level after the pulse vanishes. The proposed circuit has been fabricated in 65nm CMOS process and the measurement results demonstrate that we can monitor the PMOS and NMOS variabilities independently using the proposed monitoring circuit.","PeriodicalId":316253,"journal":{"name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","volume":"17 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133364894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Q. Ma, Hui Kong, Martin D. F. Wong, Evangeline F. Y. Young
In this paper, we introduce and study the Rectangle Escape Problem (REP), which is motivated by PCB bus escape routing. Given a rectangular region R and a set S of rectangles within R, the REP is to choose a direction for each rectangle to escape to the boundary of R, such that the resultant maximum density over R is minimized. We prove that the REP is NP-Complete, and show that it can be formulated as an Integer Linear Program (ILP). A provably good approximation algorithm for the REP is developed by applying Linear Programming (LP) relaxation and a special rounding technique to the ILP. This approximation algorithm is also shown to work for a more general version of REP with weights (weighted REP). In addition, an iterative refinement procedure is proposed as a postprocessing step to further improve the results. Our approach is tested on a set of industrial PCB bus escape routing problems. Experimental results show that the optimal solution can be obtained within 3 seconds for each of the test cases.
{"title":"A provably good approximation algorithm for Rectangle Escape Problem with application to PCB routing","authors":"Q. Ma, Hui Kong, Martin D. F. Wong, Evangeline F. Y. Young","doi":"10.5555/1950815.1950974","DOIUrl":"https://doi.org/10.5555/1950815.1950974","url":null,"abstract":"In this paper, we introduce and study the Rectangle Escape Problem (REP), which is motivated by PCB bus escape routing. Given a rectangular region R and a set S of rectangles within R, the REP is to choose a direction for each rectangle to escape to the boundary of R, such that the resultant maximum density over R is minimized. We prove that the REP is NP-Complete, and show that it can be formulated as an Integer Linear Program (ILP). A provably good approximation algorithm for the REP is developed by applying Linear Programming (LP) relaxation and a special rounding technique to the ILP. This approximation algorithm is also shown to work for a more general version of REP with weights (weighted REP). In addition, an iterative refinement procedure is proposed as a postprocessing step to further improve the results. Our approach is tested on a set of industrial PCB bus escape routing problems. Experimental results show that the optimal solution can be obtained within 3 seconds for each of the test cases.","PeriodicalId":316253,"journal":{"name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132864989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-01-25DOI: 10.1109/ASPDAC.2011.5722230
Cheng Liu, Lei Zhang, Yinhe Han, Xiaowei Li
Very large scale integrated circuits typically employ Network-on-Chip (NoC) as the backbone for on-chip communication. As technology advances into the nanometer regime, NoCs become more and more susceptible to permanent faults such as manufacturing defects, device wear-out, which hinder the correct operations of the entire system. Therefore, effective fault-tolerant techniques are essential to improve the reliability of NoCs. Prior work mainly focuses on introducing redundancies, which can't achieve satisfactory reliability and also involve large hardware overhead, especially for data path components. In this paper, we propose fine-grained data path salvaging techniques by splitting data path components, i.e., links, input buffers and crossbar into slices, instead of introducing redundancies. As long as there is one fault-free slice for each component, the router can be functional. Experimental results show that the proposed solution achieves quite high reliability with graceful performance degradation even under high fault rate.
{"title":"A resilient on-chip router design through data path salvaging","authors":"Cheng Liu, Lei Zhang, Yinhe Han, Xiaowei Li","doi":"10.1109/ASPDAC.2011.5722230","DOIUrl":"https://doi.org/10.1109/ASPDAC.2011.5722230","url":null,"abstract":"Very large scale integrated circuits typically employ Network-on-Chip (NoC) as the backbone for on-chip communication. As technology advances into the nanometer regime, NoCs become more and more susceptible to permanent faults such as manufacturing defects, device wear-out, which hinder the correct operations of the entire system. Therefore, effective fault-tolerant techniques are essential to improve the reliability of NoCs. Prior work mainly focuses on introducing redundancies, which can't achieve satisfactory reliability and also involve large hardware overhead, especially for data path components. In this paper, we propose fine-grained data path salvaging techniques by splitting data path components, i.e., links, input buffers and crossbar into slices, instead of introducing redundancies. As long as there is one fault-free slice for each component, the router can be functional. Experimental results show that the proposed solution achieves quite high reliability with graceful performance degradation even under high fault rate.","PeriodicalId":316253,"journal":{"name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117038367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-01-25DOI: 10.1109/ASPDAC.2011.5722287
Taka Suzuki
The progress of digital video processing technology and LSI technology have been the driving force behind the creation of 3D systems, and various 3D products for the home were released. 2010 became a historic year for in-home 3D. We developed a suite of system LSIs that was the key to realizing home 3D systems by applying integrated platform for digital CE, the UniPhier (Universal Platform for High-quality Image Enhancing Revolution). The system LSIs for 3D TV deliver high display speeds, and the main system LSI for 3D Blu-ray provides MPEG-4 MVC decoding. This paper describes the 3D technologies, home 3D systems and advanced system LSIs for the consumer market.
{"title":"Advanced system LSIs for home 3D system","authors":"Taka Suzuki","doi":"10.1109/ASPDAC.2011.5722287","DOIUrl":"https://doi.org/10.1109/ASPDAC.2011.5722287","url":null,"abstract":"The progress of digital video processing technology and LSI technology have been the driving force behind the creation of 3D systems, and various 3D products for the home were released. 2010 became a historic year for in-home 3D. We developed a suite of system LSIs that was the key to realizing home 3D systems by applying integrated platform for digital CE, the UniPhier (Universal Platform for High-quality Image Enhancing Revolution). The system LSIs for 3D TV deliver high display speeds, and the main system LSI for 3D Blu-ray provides MPEG-4 MVC decoding. This paper describes the 3D technologies, home 3D systems and advanced system LSIs for the consumer market.","PeriodicalId":316253,"journal":{"name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","volume":"602 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116331767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-01-25DOI: 10.1109/ASPDAC.2011.5722203
M. Fujita
Due to the highly complicated control structures of modern processors as well as ASICs, some of the logical bugs may easily escape from the pre-silicon verification processes and remain into the silicon. Those bugs can only be found after the chip has been fabricated and used in the systems. So post-silicon debugging is becoming a essential part of the design flows for complicated and large system designs. This paper summarizes our research activities targeting post-silicon debugging for highly complicated pipeline processors as well as large ASICs. We have been working on the following three topics: 1) Translation of chip level error traces to high and abstracted level so that more efficient simulation as well as formal analysis become possible, 2) Utilize experiences on formal verification and debugging processes for pipelined processors for debugging and in-fields rectification of chips, and 3) Apply incremental high level synthesis for efficient in-fields rectifications of ASIC designs. Our approaches utilize high level or abstracted design information as much as possible to make things more efficient and effective. In this paper we briefly present the techniques for the first two topics.
{"title":"Utilizing high level design information to speed up post-silicon debugging","authors":"M. Fujita","doi":"10.1109/ASPDAC.2011.5722203","DOIUrl":"https://doi.org/10.1109/ASPDAC.2011.5722203","url":null,"abstract":"Due to the highly complicated control structures of modern processors as well as ASICs, some of the logical bugs may easily escape from the pre-silicon verification processes and remain into the silicon. Those bugs can only be found after the chip has been fabricated and used in the systems. So post-silicon debugging is becoming a essential part of the design flows for complicated and large system designs. This paper summarizes our research activities targeting post-silicon debugging for highly complicated pipeline processors as well as large ASICs. We have been working on the following three topics: 1) Translation of chip level error traces to high and abstracted level so that more efficient simulation as well as formal analysis become possible, 2) Utilize experiences on formal verification and debugging processes for pipelined processors for debugging and in-fields rectification of chips, and 3) Apply incremental high level synthesis for efficient in-fields rectifications of ASIC designs. Our approaches utilize high level or abstracted design information as much as possible to make things more efficient and effective. In this paper we briefly present the techniques for the first two topics.","PeriodicalId":316253,"journal":{"name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114644031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-01-25DOI: 10.1109/ASPDAC.2011.5722304
Kuan-Yu Lin, Hong-Ting Lin, Tsung-Yi Ho
Power consumption is known to be a crucial issue in current IC designs. To tackle this problem, multiple dynamic supply voltage (MDSV) designs are proposed as an efficient solution in modern IC designs. However, the increasing variability of clock skew during the switching of power modes leads to an increase in the complication of clock skew reduction in MDSV designs. In this paper, we propose a tunable clock tree structure by adopting the adjustable delay buffers (ADBs). The ADBs can be used to produce additional delays, hence the clock latencies and skew become tunable in a clock tree. Importing a buffered clock tree, the ADBs with delay value assignments are inserted to reduce clock skew in MDSV designs. An efficient algorithm of ADB insertion for the minimization of clock skew, area, and runtime in MDSV designs has been presented. Comparing with the state-of-the-art algorithm, experimental results show maximum 42.40% area overhead improvement and 117.84× runtime speedup.
{"title":"An efficient algorithm of adjustable delay buffer insertion for clock skew minimization in multiple dynamic supply voltage designs","authors":"Kuan-Yu Lin, Hong-Ting Lin, Tsung-Yi Ho","doi":"10.1109/ASPDAC.2011.5722304","DOIUrl":"https://doi.org/10.1109/ASPDAC.2011.5722304","url":null,"abstract":"Power consumption is known to be a crucial issue in current IC designs. To tackle this problem, multiple dynamic supply voltage (MDSV) designs are proposed as an efficient solution in modern IC designs. However, the increasing variability of clock skew during the switching of power modes leads to an increase in the complication of clock skew reduction in MDSV designs. In this paper, we propose a tunable clock tree structure by adopting the adjustable delay buffers (ADBs). The ADBs can be used to produce additional delays, hence the clock latencies and skew become tunable in a clock tree. Importing a buffered clock tree, the ADBs with delay value assignments are inserted to reduce clock skew in MDSV designs. An efficient algorithm of ADB insertion for the minimization of clock skew, area, and runtime in MDSV designs has been presented. Comparing with the state-of-the-art algorithm, experimental results show maximum 42.40% area overhead improvement and 117.84× runtime speedup.","PeriodicalId":316253,"journal":{"name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","volume":"200 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115577440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：