Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6292028
Siva Sudani, Degang Chen, R. Geiger
Achieving coherent sampling to accurately estimate the spectral characteristics of a signal is a very challenging task. Though the Four point sine wave fitting method can be used to accurately estimate some spectral parameters of a non-coherently sampled signal, not all parameters can be estimated accurately. This paper proposes a method that can be used to accurately estimate ALL the spectral characteristics from the spectrum when a signal is not sampled coherently. The non-coherent fundamental and harmonics are accurately identified and replaced with their corresponding coherent signals to achieve accurate results. Simulation results show the effectiveness and robustness of the method.
{"title":"A method for accurate full spectrum testing without requiring coherency","authors":"Siva Sudani, Degang Chen, R. Geiger","doi":"10.1109/MWSCAS.2012.6292028","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292028","url":null,"abstract":"Achieving coherent sampling to accurately estimate the spectral characteristics of a signal is a very challenging task. Though the Four point sine wave fitting method can be used to accurately estimate some spectral parameters of a non-coherently sampled signal, not all parameters can be estimated accurately. This paper proposes a method that can be used to accurately estimate ALL the spectral characteristics from the spectrum when a signal is not sampled coherently. The non-coherent fundamental and harmonics are accurately identified and replaced with their corresponding coherent signals to achieve accurate results. Simulation results show the effectiveness and robustness of the method.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"227 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128939187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6291976
O. Chen, Kuan-Hsien Lin, Zhe Ming Liu, Shu Chun Wang, Meng-Lin Hsia
This work develops a 2D/3D integrated image sensor that includes photodiodes, pixel circuits, correlated double sampling circuits, sense amplifiers, a multi-channel Time-to-Digital Converter (TDC), a column decoder, a row decoder, a controller and readout circuits. The photodiode of P-diffusion_N-well_P-substrate is used to sense photos at 2D and 3D modes under different biased voltages. At 2D and 3D modes, a charge supply mechanism and a feedback pull-down mechanism in a pixel circuit are adopted to delay the saturation and accelerate the response, respectively. As well as a multi-channel TDC, rapid parallel reading at a 3D mode is accomplished by using a bus-sharing mechanism. Based on the TSMC 0.35μm 2P4M CMOS technology, a 352×288-pixel 2D and 88×72-pixel 3D integrated image sensor was implemented to have a die size of 12mm×12mm. The dynamic range at a 2D mode can reach 110dB and the depth resolution can be around 4cm at a 3D mode. Therefore, the proposed integrated image sensor can effectively switch between 2D and 3D sensing operations for various multimedia capturing applications.
{"title":"2D and 3D integrated image sensor with a bus-sharing mechanism","authors":"O. Chen, Kuan-Hsien Lin, Zhe Ming Liu, Shu Chun Wang, Meng-Lin Hsia","doi":"10.1109/MWSCAS.2012.6291976","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6291976","url":null,"abstract":"This work develops a 2D/3D integrated image sensor that includes photodiodes, pixel circuits, correlated double sampling circuits, sense amplifiers, a multi-channel Time-to-Digital Converter (TDC), a column decoder, a row decoder, a controller and readout circuits. The photodiode of P-diffusion_N-well_P-substrate is used to sense photos at 2D and 3D modes under different biased voltages. At 2D and 3D modes, a charge supply mechanism and a feedback pull-down mechanism in a pixel circuit are adopted to delay the saturation and accelerate the response, respectively. As well as a multi-channel TDC, rapid parallel reading at a 3D mode is accomplished by using a bus-sharing mechanism. Based on the TSMC 0.35μm 2P4M CMOS technology, a 352×288-pixel 2D and 88×72-pixel 3D integrated image sensor was implemented to have a die size of 12mm×12mm. The dynamic range at a 2D mode can reach 110dB and the depth resolution can be around 4cm at a 3D mode. Therefore, the proposed integrated image sensor can effectively switch between 2D and 3D sensing operations for various multimedia capturing applications.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129093788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6292151
Daeyoung Lee, Jong‐Moon Chung, R. Garcia
Machine-to-machine (M2M) communication between devices has significant differences with conventional human-to-human (H2H) communications. From these differences, considerable technical issues of M2M communication arise, which are expected to result in numerous system changes compared to existing H2H communication networks. M2M-based features offer a new paradigm for future communication and network services, and can enable various convergence services in support of ubiquitous businesses and complex manufacturing industries. However, currently one limiting factor is lack of end-to-end M2M network connectivity. Various global standardization groups are conducting standardization on M2M communications. In this paper, a summary on the progress of global M2M standardization is presented. This paper also introduces M2M technical issues and discuss on the necessity of M2M vertical handover (VHO) and technical requirements in support of M2M VHO and fast handover for proxy mobile IPv6 (FPMIPv6) VHO between heterogeneous M2M protocol networks to enable end-to-end M2M network connectivity.
{"title":"Machine-to-machine communication standardization trends and end-to-end service enhancements through vertical handover technology","authors":"Daeyoung Lee, Jong‐Moon Chung, R. Garcia","doi":"10.1109/MWSCAS.2012.6292151","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292151","url":null,"abstract":"Machine-to-machine (M2M) communication between devices has significant differences with conventional human-to-human (H2H) communications. From these differences, considerable technical issues of M2M communication arise, which are expected to result in numerous system changes compared to existing H2H communication networks. M2M-based features offer a new paradigm for future communication and network services, and can enable various convergence services in support of ubiquitous businesses and complex manufacturing industries. However, currently one limiting factor is lack of end-to-end M2M network connectivity. Various global standardization groups are conducting standardization on M2M communications. In this paper, a summary on the progress of global M2M standardization is presented. This paper also introduces M2M technical issues and discuss on the necessity of M2M vertical handover (VHO) and technical requirements in support of M2M VHO and fast handover for proxy mobile IPv6 (FPMIPv6) VHO between heterogeneous M2M protocol networks to enable end-to-end M2M network connectivity.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129095168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6291957
Hooman Rashtian, A. H. M. Shirazi, S. Mirabbasi
This paper presents the application of body biasing to improve linearity performance of CMOS Gilbert-cell mixers. In order to improve the linearity, the bulk bias voltage of the transistors in the local oscillator (LO) stage is adjusted. The improvement in linearity is obtained while the conversion gain and power consumption of the mixer remain virtually intact. A 0.13-μm CMOS proof-of-concept prototype is implemented which operates at radio frequency (RF) of 2.4 GHz with an intermediate frequency (IF) of 50 MHz and draws 2.25 mA from a 1.2-V supply. Based on post-layout simulations, the proposed technique results in a 5-dB improvement in the input-referred third-order intercept point (IIP3) of the prototype mixer.
{"title":"Improving linearity of CMOS Gilbert-cell mixers using body biasing","authors":"Hooman Rashtian, A. H. M. Shirazi, S. Mirabbasi","doi":"10.1109/MWSCAS.2012.6291957","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6291957","url":null,"abstract":"This paper presents the application of body biasing to improve linearity performance of CMOS Gilbert-cell mixers. In order to improve the linearity, the bulk bias voltage of the transistors in the local oscillator (LO) stage is adjusted. The improvement in linearity is obtained while the conversion gain and power consumption of the mixer remain virtually intact. A 0.13-μm CMOS proof-of-concept prototype is implemented which operates at radio frequency (RF) of 2.4 GHz with an intermediate frequency (IF) of 50 MHz and draws 2.25 mA from a 1.2-V supply. Based on post-layout simulations, the proposed technique results in a 5-dB improvement in the input-referred third-order intercept point (IIP3) of the prototype mixer.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130631015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6291952
R. Salmeh
A creative method to reduce the voltage head room requirement in the design of double balanced mixer is introduced. Design of a novel high gain, low noise figure and low power CMOS mixer with fully integrated ESD protection is presented. The mixer was implemented in ST 90nm CMOS technology and was packed in a QFN package. With an operating frequency of 1.575 GHz this mixer was targeted for GPS front-end receiver application.
{"title":"A novel high gain and low noise figure CMOS mixer with fully integrated esd protection","authors":"R. Salmeh","doi":"10.1109/MWSCAS.2012.6291952","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6291952","url":null,"abstract":"A creative method to reduce the voltage head room requirement in the design of double balanced mixer is introduced. Design of a novel high gain, low noise figure and low power CMOS mixer with fully integrated ESD protection is presented. The mixer was implemented in ST 90nm CMOS technology and was packed in a QFN package. With an operating frequency of 1.575 GHz this mixer was targeted for GPS front-end receiver application.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"564 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132042527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6292229
C. Parkey, W. Mikhael, D. Chester
The problem of characterizing transfer functions of Analog to Digital Converters (ADC) for use in compensation of Time Interleaved Analog to Digital Converters (TIADC) is ubiquitous in the area of mismatch correction algorithms. Identifying, classifying, and quantifying the presence of errors in ADCs and TIADCs is fundamental in the pursuit of correcting these errors. This problem, characterization of error effects, is investigated through calculation of higher order cumulants on the error signals of each type of system. The concept of cumulant calculation and interpretation is presented and applied to varying error environments and input signals.
{"title":"Cumulant characterizations of ADC error sources with applications to Time Interleaved ADCs","authors":"C. Parkey, W. Mikhael, D. Chester","doi":"10.1109/MWSCAS.2012.6292229","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292229","url":null,"abstract":"The problem of characterizing transfer functions of Analog to Digital Converters (ADC) for use in compensation of Time Interleaved Analog to Digital Converters (TIADC) is ubiquitous in the area of mismatch correction algorithms. Identifying, classifying, and quantifying the presence of errors in ADCs and TIADCs is fundamental in the pursuit of correcting these errors. This problem, characterization of error effects, is investigated through calculation of higher order cumulants on the error signals of each type of system. The concept of cumulant calculation and interpretation is presented and applied to varying error environments and input signals.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129232860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6291989
A. E. Zadeh
Implantable medical devices such as pacemakers, internal cardi-ac defibrillator (ICD), and cardiac resynchronization therapy (CRT) devices have conducting leads that are used to sense the heart signals and to pace into the heart muscle in order to artificially stimulate it. The sensing system in these devices monitor patient's heart signals continually; therefore, it must always remain powered-up. As a result lower power consumption for this block is very critical. Additionally device sense systems have bandpass anti-aliasing filters with lower-pole frequency at sub-Hz to be able to attenuate unwanted heart-repolarization signal. To be able to implement such a low-frequency pole, today's medical devices use off-chip microfarad-range hybrid capacitors along-with internal integrated circuit resistors. Depending on the device type, often nine to twelve medically-graded off-chip capacitors are placed on the hybrid substrate. These capacitors are major source of four drawbacks: (1) critical reliability, (2) precious real-estate space area (limiting the device size), (3) external spurious noise pickup, and (4) additional cost. This paper presents a continu-ous Gm-C filter that realizes the identical cardiac sense-system anti-aliasing filter transfer function in a fully integrated form with no external capacitors. To realize sub-HZ pole-frequency using pico-Farad (pF) range integrated-circuit capacitors, the circuit combines three techniques to reduce the transconductance of the operational amplifier into pico-Siemens (pS or pA/V) regime: active lineariza-tion, current cancellation, and series-parallel active load. Further-more, because current consumption is a critical performance parame-ter for implantable cardiac device, each filter is designed to consume less than 20nA. Finally effects of amplifier non-idealities such as linearity, noise, offset, and leakage in the filter are addressed. The filter can be fabricated in any mixed-signal 0.18μm process.
{"title":"Fully-integrated Gm-C anti-aliasing filter for sense system of implantable cardiac devices","authors":"A. E. Zadeh","doi":"10.1109/MWSCAS.2012.6291989","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6291989","url":null,"abstract":"Implantable medical devices such as pacemakers, internal cardi-ac defibrillator (ICD), and cardiac resynchronization therapy (CRT) devices have conducting leads that are used to sense the heart signals and to pace into the heart muscle in order to artificially stimulate it. The sensing system in these devices monitor patient's heart signals continually; therefore, it must always remain powered-up. As a result lower power consumption for this block is very critical. Additionally device sense systems have bandpass anti-aliasing filters with lower-pole frequency at sub-Hz to be able to attenuate unwanted heart-repolarization signal. To be able to implement such a low-frequency pole, today's medical devices use off-chip microfarad-range hybrid capacitors along-with internal integrated circuit resistors. Depending on the device type, often nine to twelve medically-graded off-chip capacitors are placed on the hybrid substrate. These capacitors are major source of four drawbacks: (1) critical reliability, (2) precious real-estate space area (limiting the device size), (3) external spurious noise pickup, and (4) additional cost. This paper presents a continu-ous Gm-C filter that realizes the identical cardiac sense-system anti-aliasing filter transfer function in a fully integrated form with no external capacitors. To realize sub-HZ pole-frequency using pico-Farad (pF) range integrated-circuit capacitors, the circuit combines three techniques to reduce the transconductance of the operational amplifier into pico-Siemens (pS or pA/V) regime: active lineariza-tion, current cancellation, and series-parallel active load. Further-more, because current consumption is a critical performance parame-ter for implantable cardiac device, each filter is designed to consume less than 20nA. Finally effects of amplifier non-idealities such as linearity, noise, offset, and leakage in the filter are addressed. The filter can be fabricated in any mixed-signal 0.18μm process.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125496229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6292154
R. Garcia, Jong‐Moon Chung
With the emergence of demands of virtual infrastructure, cloud storage, hyper-computing, semantic search, collective intelligence, and semi-structured mining, the entrepreneur, developer, and everyday consumer would be unrecognizable when viewed by their counterparts even as recent as the beginning of the millennia. Adoption of XaaS (anything-as-a-service) has allowed the ushering of “anytime-anywhere-any-size” with social and entertaining aspects for the consumer, breadth-expansion capabilities for the software developer, and multidimensional marketing/sales channels for the entrepreneur. What is presented here is the dilation of these services through the increased abstraction with yet another layer of web services. One theoretical entry point is the ESB (enterprise service bus) which represents a robust architecture for a wide matrix of web services. Within it, there can exist concentric ESBs that ultimately serve as an XaaS for XaaS itself.
{"title":"XaaS for XaaS: An evolving abstraction of web services for the entrepreneur, developer, and consumer","authors":"R. Garcia, Jong‐Moon Chung","doi":"10.1109/MWSCAS.2012.6292154","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292154","url":null,"abstract":"With the emergence of demands of virtual infrastructure, cloud storage, hyper-computing, semantic search, collective intelligence, and semi-structured mining, the entrepreneur, developer, and everyday consumer would be unrecognizable when viewed by their counterparts even as recent as the beginning of the millennia. Adoption of XaaS (anything-as-a-service) has allowed the ushering of “anytime-anywhere-any-size” with social and entertaining aspects for the consumer, breadth-expansion capabilities for the software developer, and multidimensional marketing/sales channels for the entrepreneur. What is presented here is the dilation of these services through the increased abstraction with yet another layer of web services. One theoretical entry point is the ESB (enterprise service bus) which represents a robust architecture for a wide matrix of web services. Within it, there can exist concentric ESBs that ultimately serve as an XaaS for XaaS itself.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"2 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121551926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6292120
In-Seok Jung, Yong-Bin Kim, F. Lombardi
In this paper, two types of a soft error hardened 10T SRAM cells with high static noise margin (SNM) are proposed for low voltage operation. The proposed NMOS stacked SRAM cell operates normally with higher read SNM near to sub-threshold region compared to prior works. Simulated results using 0.18um standard CMOS process demonstrate that proposed NMOS stacked-10T cell has high read SNM and high soft error resilience of at least 100 times higher than unprotected standard 6T SRAM cell for a single event transient (SET).
{"title":"A novel sort error hardened 10T SRAM cells for low voltage operation","authors":"In-Seok Jung, Yong-Bin Kim, F. Lombardi","doi":"10.1109/MWSCAS.2012.6292120","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292120","url":null,"abstract":"In this paper, two types of a soft error hardened 10T SRAM cells with high static noise margin (SNM) are proposed for low voltage operation. The proposed NMOS stacked SRAM cell operates normally with higher read SNM near to sub-threshold region compared to prior works. Simulated results using 0.18um standard CMOS process demonstrate that proposed NMOS stacked-10T cell has high read SNM and high soft error resilience of at least 100 times higher than unprotected standard 6T SRAM cell for a single event transient (SET).","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122299784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6292099
Keisuke Inoue, M. Kaneko
In the presence of process variation, conventional worst-case timing analysis is no longer able to fully realize the benefit of scaling and integrating. As a result, statistical static timing analysis (SSTA) is essentially needed in high-level synthesis (HLS) stage. This paper presents the first work to develop a design framework of SSTA for HLS based on transparent latches. An integer linear programming-based formal approach is provided to simultaneously solve scheduling and functional unit binding to minimize the scheduling length while meeting the timing-yield requirement. Experiments demonstrate the effectiveness of the proposed approach.
{"title":"Statistical timing-yield driven scheduling and FU binding in latch-based datapath synthesis","authors":"Keisuke Inoue, M. Kaneko","doi":"10.1109/MWSCAS.2012.6292099","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292099","url":null,"abstract":"In the presence of process variation, conventional worst-case timing analysis is no longer able to fully realize the benefit of scaling and integrating. As a result, statistical static timing analysis (SSTA) is essentially needed in high-level synthesis (HLS) stage. This paper presents the first work to develop a design framework of SSTA for HLS based on transparent latches. An integer linear programming-based formal approach is provided to simultaneously solve scheduling and functional unit binding to minimize the scheduling length while meeting the timing-yield requirement. Experiments demonstrate the effectiveness of the proposed approach.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126032903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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