Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6292111
J. Paramesh, Sandipan Kundu, Shadi Saberi
This paper presents low-power design techniques for wideband LNA's and wide-tuning frequency generation circuits operating at mm-wave. Transformer neutralization techniques enable the design of current-reuse and low-voltage LNA's. Transformer-based VCO's with resonance mode switching are introduced to achieve very wide tuning range. The design and characterization of several prototype circuits is presented to validate these concepts.
{"title":"Low-power front-end amplification and frequency generation techniques for ultra-wideband millimeter-wave transceivers","authors":"J. Paramesh, Sandipan Kundu, Shadi Saberi","doi":"10.1109/MWSCAS.2012.6292111","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292111","url":null,"abstract":"This paper presents low-power design techniques for wideband LNA's and wide-tuning frequency generation circuits operating at mm-wave. Transformer neutralization techniques enable the design of current-reuse and low-voltage LNA's. Transformer-based VCO's with resonance mode switching are introduced to achieve very wide tuning range. The design and characterization of several prototype circuits is presented to validate these concepts.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127963833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6292000
B. S. Deepaksubramanyan, C. Chen, A. Nunez
Input/Output Buffer Information Specification (IBIS) behavioral models are widely used for circuit-level signal integrity (SI) analysis due to its fast simulation speed and good accuracy. This work presents a tool to generate models of circuits specified by IBIS models. The model generation tool estimates poles, rise time and fall time of a circuit specified by IBIS models. The method consists of two steps; first regression analysis is performed on IBIS data with Weibull distribution function (WCDF) as the regression function. Based on the estimated parameter values, rise time and fall time values are obtained. The second step involves matching moments of WCDF to circuit moments and obtaining the estimated poles of the system. The method is generic and is scalable in nanometer CMOS. CMOS inverters have been used to demonstrate the methodology.
{"title":"A tool to generate models based on behavioral IBIS models","authors":"B. S. Deepaksubramanyan, C. Chen, A. Nunez","doi":"10.1109/MWSCAS.2012.6292000","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292000","url":null,"abstract":"Input/Output Buffer Information Specification (IBIS) behavioral models are widely used for circuit-level signal integrity (SI) analysis due to its fast simulation speed and good accuracy. This work presents a tool to generate models of circuits specified by IBIS models. The model generation tool estimates poles, rise time and fall time of a circuit specified by IBIS models. The method consists of two steps; first regression analysis is performed on IBIS data with Weibull distribution function (WCDF) as the regression function. Based on the estimated parameter values, rise time and fall time values are obtained. The second step involves matching moments of WCDF to circuit moments and obtaining the estimated poles of the system. The method is generic and is scalable in nanometer CMOS. CMOS inverters have been used to demonstrate the methodology.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128973544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6292064
H. Okazaki, Kaoru Yashikida, H. Mizutani
The problem of constructing one dimensional map model based on time series data, especially the one dimensional map exactly reproducing the time series data is considered. A new method that employs a piecewise linear canonical representing function and implements the one dimensional map as MATLAB vectrized M-files, is proposed. The application of this method is illustrated by examples of time series data such as a Nikkei Stock Average, an exchange rate, and an EEG.
{"title":"A one dimensional mapping method for time series data","authors":"H. Okazaki, Kaoru Yashikida, H. Mizutani","doi":"10.1109/MWSCAS.2012.6292064","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292064","url":null,"abstract":"The problem of constructing one dimensional map model based on time series data, especially the one dimensional map exactly reproducing the time series data is considered. A new method that employs a piecewise linear canonical representing function and implements the one dimensional map as MATLAB vectrized M-files, is proposed. The application of this method is illustrated by examples of time series data such as a Nikkei Stock Average, an exchange rate, and an EEG.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116219033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6292193
A. Mesgarani, S. Ay
This paper presents a new asynchronous binary search analog to digital converter (ADC). Proposed asynchronous binary search ADC enables higher speed operation of binary search algorithm by resolving two bits in each step. Using two bit flash quantizers in each stage of the proposed binary search ADC the conversion speed improves by two times compared with conventional binary search ADC architectures. New sampling scheme and dynamic offset cancellation technique for the comparator have been adapted to realize a low power and high speed converter. The proposed single channel 6-bit 1GS/s ADC was designed in 65nm CMOS process. Simulation results show that the ADC reaches a peak SNDR of 36.12dB consuming 1.35mW from a single 1.2V power supply. It achieves of 29fJ/conv.code FoM.
{"title":"A 6-Bit 1GS/s asynchronous binary search ADC with 2 bit flash quantizers","authors":"A. Mesgarani, S. Ay","doi":"10.1109/MWSCAS.2012.6292193","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292193","url":null,"abstract":"This paper presents a new asynchronous binary search analog to digital converter (ADC). Proposed asynchronous binary search ADC enables higher speed operation of binary search algorithm by resolving two bits in each step. Using two bit flash quantizers in each stage of the proposed binary search ADC the conversion speed improves by two times compared with conventional binary search ADC architectures. New sampling scheme and dynamic offset cancellation technique for the comparator have been adapted to realize a low power and high speed converter. The proposed single channel 6-bit 1GS/s ADC was designed in 65nm CMOS process. Simulation results show that the ADC reaches a peak SNDR of 36.12dB consuming 1.35mW from a single 1.2V power supply. It achieves of 29fJ/conv.code FoM.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127169562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6292195
Jinlong Gu, N. Mcfarlane
We show the design of a current mode ramp analog to digital converter (ADC) in standard 0.13 μm, 1 poly, 8 metal CMOS process. The ADC is a low-power and area-saving solution for multi-frequency cell impedance measurement. It uses two-step conversion to boost the conversion time by a factor of 32, while keeping a constant practical clock frequency. The ramp ADC samples current signals at different frequencies and converts them into digital signals simultaneously. The main blocks of the ADC are current-mode ramp generator, current comparator, a delay locked loop (DLL) and a gray-code counter.
{"title":"Low power current mode ramp ADC for multi-frequency cell impedance measurement","authors":"Jinlong Gu, N. Mcfarlane","doi":"10.1109/MWSCAS.2012.6292195","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292195","url":null,"abstract":"We show the design of a current mode ramp analog to digital converter (ADC) in standard 0.13 μm, 1 poly, 8 metal CMOS process. The ADC is a low-power and area-saving solution for multi-frequency cell impedance measurement. It uses two-step conversion to boost the conversion time by a factor of 32, while keeping a constant practical clock frequency. The ramp ADC samples current signals at different frequencies and converts them into digital signals simultaneously. The main blocks of the ADC are current-mode ramp generator, current comparator, a delay locked loop (DLL) and a gray-code counter.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124145154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6292228
M. Allén, Jaakko Marttila, M. Valkama
Emerging wireless communications concepts, such as cognitive radio, bring various challenges in the implementation of radio receivers. One of the concerns is the dynamic range of the receiver front-end, which might be insufficient in certain situations, e.g., if strong blocker signals are present concurrently with weaker interesting signals. Overdrive of the receiver front-end causes signal clipping and therefore considerable amount of nonlinear distortion is created. This paper derives a general parametric clipping model using time-dependent Fourier series and analyses the model in different clipping scenarios. The paper also proposes a method to exploit the derived model in a radio receiver for digital post-processing in order to mitigate unwanted clipping distortion.
{"title":"General clipping modeling and DSP-based mitigation for wideband A/D interface and RF front-end of emerging radio receivers","authors":"M. Allén, Jaakko Marttila, M. Valkama","doi":"10.1109/MWSCAS.2012.6292228","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292228","url":null,"abstract":"Emerging wireless communications concepts, such as cognitive radio, bring various challenges in the implementation of radio receivers. One of the concerns is the dynamic range of the receiver front-end, which might be insufficient in certain situations, e.g., if strong blocker signals are present concurrently with weaker interesting signals. Overdrive of the receiver front-end causes signal clipping and therefore considerable amount of nonlinear distortion is created. This paper derives a general parametric clipping model using time-dependent Fourier series and analyses the model in different clipping scenarios. The paper also proposes a method to exploit the derived model in a radio receiver for digital post-processing in order to mitigate unwanted clipping distortion.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123610442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6292045
S. Chang, C. Wey
This paper presents a novel multiplexer-based carry-skip algorithm for hybrid adder design based on the parallel-prefix computation technique. The hybrid adder combines both carry-lookahead and multiplexer-based carry-skip architectures to speed up the performance. The driving capability of the critical path is enhanced to boost the speed, while optimizing both area and power in the non-critical paths. Experimental results show that the proposed 64-bit hybrid adder achieves low cost (46 × 210 um2), low power (2.82 mW), and high speed (246.5 ps), where the UMC 90 nm CMOS process is simulated with 1.0V supply voltage.
{"title":"A Fast 64-bit hybrid adder design in 90nm CMOS process","authors":"S. Chang, C. Wey","doi":"10.1109/MWSCAS.2012.6292045","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292045","url":null,"abstract":"This paper presents a novel multiplexer-based carry-skip algorithm for hybrid adder design based on the parallel-prefix computation technique. The hybrid adder combines both carry-lookahead and multiplexer-based carry-skip architectures to speed up the performance. The driving capability of the critical path is enhanced to boost the speed, while optimizing both area and power in the non-critical paths. Experimental results show that the proposed 64-bit hybrid adder achieves low cost (46 × 210 um2), low power (2.82 mW), and high speed (246.5 ps), where the UMC 90 nm CMOS process is simulated with 1.0V supply voltage.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124986899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6292089
Li Wang, R. Ma, Albert Z. H. Wang, Xin Wang, B. Zhao, X. S. Wang, P. Yue, Zitao Shi, Yuhua Cheng
This paper presents an overview of the co-design technique for broadband RF ESD protection circuit designs. The unique mixed-mode ESD simulation design methodology allows full-chip design optimization and prediction of broadband RF ICs with full low-parasitic ESD protection, which were validated experimentally using ultra wideband (UWB) RF ICs and RF switch circuits in CMOS technologies.
{"title":"A design technique overview on broadband RF ESD protection circuit designs","authors":"Li Wang, R. Ma, Albert Z. H. Wang, Xin Wang, B. Zhao, X. S. Wang, P. Yue, Zitao Shi, Yuhua Cheng","doi":"10.1109/MWSCAS.2012.6292089","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292089","url":null,"abstract":"This paper presents an overview of the co-design technique for broadband RF ESD protection circuit designs. The unique mixed-mode ESD simulation design methodology allows full-chip design optimization and prediction of broadband RF ICs with full low-parasitic ESD protection, which were validated experimentally using ultra wideband (UWB) RF ICs and RF switch circuits in CMOS technologies.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131331987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6292049
Karthik Sangaiah, P. Nagvajara
This paper describes a design for a variable fractional delay (VFD) FIR filter implemented on reconfigurable hardware. Fractionally delayed signals are required for several audio-based applications, including echo cancellation and musical signal analysis. Traditionally, VFD FIR filters are implemented using a complex, fixed structure based upon the order of the filter. This fixed structure restricts the range of valid fractional delay values permitted by the filter. The proposed design in this paper implements an order-scalable FIR filter, permitting fractionally delayed signals of widely varying integer sizes. This design builds upon the traditional Lagrange interpolator FIR filter using either a software-based or hardware-based Lagrange coefficient computational unit. Using today's (2012) low-cost high performance reconfigurable hardware FIR coefficients can be computed fast enough for real-time variable fractional delay applications. The resulting real-time VFD FIR filter is tested using the Xilinx System Generator toolkit as well as Xilinx ISE and ModelSim. The proposed filter was functionally verified using ModelSim and System Generator.
本文介绍了一种在可重构硬件上实现可变分数延迟(VFD) FIR滤波器的设计。一些基于音频的应用需要分数延迟信号，包括回声消除和音乐信号分析。传统上，VFD FIR滤波器使用基于滤波器顺序的复杂固定结构来实现。这个固定的结构限制了滤波器允许的有效分数延迟值的范围。本文提出的设计实现了一个阶可伸缩的FIR滤波器，允许广泛变化的整数大小的分数延迟信号。本设计基于传统的拉格朗日插值FIR滤波器，使用基于软件或基于硬件的拉格朗日系数计算单元。使用今天(2012)的低成本高性能可重构硬件FIR系数可以计算足够快的实时可变分数延迟应用。所得到的实时VFD FIR滤波器使用Xilinx System Generator工具包以及Xilinx ISE和ModelSim进行测试。使用ModelSim和System Generator对所提出的滤波器进行了功能验证。
{"title":"Variable fractional digital delay filter on reconfigurable hardware","authors":"Karthik Sangaiah, P. Nagvajara","doi":"10.1109/MWSCAS.2012.6292049","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292049","url":null,"abstract":"This paper describes a design for a variable fractional delay (VFD) FIR filter implemented on reconfigurable hardware. Fractionally delayed signals are required for several audio-based applications, including echo cancellation and musical signal analysis. Traditionally, VFD FIR filters are implemented using a complex, fixed structure based upon the order of the filter. This fixed structure restricts the range of valid fractional delay values permitted by the filter. The proposed design in this paper implements an order-scalable FIR filter, permitting fractionally delayed signals of widely varying integer sizes. This design builds upon the traditional Lagrange interpolator FIR filter using either a software-based or hardware-based Lagrange coefficient computational unit. Using today's (2012) low-cost high performance reconfigurable hardware FIR coefficients can be computed fast enough for real-time variable fractional delay applications. The resulting real-time VFD FIR filter is tested using the Xilinx System Generator toolkit as well as Xilinx ISE and ModelSim. The proposed filter was functionally verified using ModelSim and System Generator.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131363548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6292233
S. Chandrasekaran, K. Ragavan
The performance of Active Power Filter (APF) is decided by the reference current estimation technique. This estimation is not straightforward in practice due to the distorted and unbalanced supply; non-linear and unbalanced load. To address such practical situations, a new Sliding Discrete Fourier Transform (SDFT) based technique involving instantaneous symmetrical components and p-q theory is proposed. With this method, the harmonic, fundamental frequency unbalanced and reactive current components are determined. The feature that the SDFT could provide the 90-degree shifted signal together with the symmetrical components is utilized for the purpose of determining the unbalanced current component. Fundamental reactive current is obtained using the widely used instantaneous p-q theory. The effectiveness of the proposed technique is demonstrated through the simulation results pertaining to three phase system with distorted and unbalanced supply.
{"title":"Sliding DFT assisted instantaneous symmetrical components method for estimating reference current to Active Power Filter","authors":"S. Chandrasekaran, K. Ragavan","doi":"10.1109/MWSCAS.2012.6292233","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292233","url":null,"abstract":"The performance of Active Power Filter (APF) is decided by the reference current estimation technique. This estimation is not straightforward in practice due to the distorted and unbalanced supply; non-linear and unbalanced load. To address such practical situations, a new Sliding Discrete Fourier Transform (SDFT) based technique involving instantaneous symmetrical components and p-q theory is proposed. With this method, the harmonic, fundamental frequency unbalanced and reactive current components are determined. The feature that the SDFT could provide the 90-degree shifted signal together with the symmetrical components is utilized for the purpose of determining the unbalanced current component. Fundamental reactive current is obtained using the widely used instantaneous p-q theory. The effectiveness of the proposed technique is demonstrated through the simulation results pertaining to three phase system with distorted and unbalanced supply.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124666031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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