Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6292178
Dalei Wu, Weiping Zhu, M. Swamy
The conventional soft-decision based noise estimation algorithms normally assume that noise exists, only when speech is absent. Consequently, the estimated noise spectra are not updated in the segments of speech presence, but only in those of speech absence. This assumption often results in several problems such as delay and bias of noise spectrum estimates. In this paper, we propose a solution by using speech enhancement residue (SER) to compensate the estimation bias in the presence of speech. The proposed method can be naturally combined with the improved minimum controlled averaging (IMCRA) method to consistently update noise spectra. The experimental results show that the SER-based IMCRA can reduce the relative segmental estimation errors for various types of noise at different SNR levels, especially for car internal noise.
{"title":"Noise spectrum estimation with improved minimum controlled recursive averaging based on speech enhancement residue","authors":"Dalei Wu, Weiping Zhu, M. Swamy","doi":"10.1109/MWSCAS.2012.6292178","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292178","url":null,"abstract":"The conventional soft-decision based noise estimation algorithms normally assume that noise exists, only when speech is absent. Consequently, the estimated noise spectra are not updated in the segments of speech presence, but only in those of speech absence. This assumption often results in several problems such as delay and bias of noise spectrum estimates. In this paper, we propose a solution by using speech enhancement residue (SER) to compensate the estimation bias in the presence of speech. The proposed method can be naturally combined with the improved minimum controlled averaging (IMCRA) method to consistently update noise spectra. The experimental results show that the SER-based IMCRA can reduce the relative segmental estimation errors for various types of noise at different SNR levels, especially for car internal noise.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124513199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6291953
J. Fritzin, B. Mesgarzadeh, A. Alvandpour
This paper presents a Class-D stage with 3rd harmonic suppression operating at 2VDD(i.e., twice the nominal supply voltage). A DLL-based phase generator is used to generate the phases of the driving signals and by modifying the driver stage 5th harmonic suppression is also possible. The output stage and drivers are based on inverters only, where the short-circuit current is eliminated in the output stage. Operating at 1 GHz, the simulated output power is +19.4 dBm utilizing a 1-V supply and a 5-Ω load, with Drain Efficiency (DE) and Power-Added Efficiency (PAE) of 72% and 52%, respectively, including power dissipation in the DLL-based phase generator and drivers. The 3rd harmonic is suppressed 23 dB (-33 dBc) compared to a conventional Class-D stage.
本文提出了一种工作在2VDD(即2VDD)时具有三次谐波抑制的d类级。(额定电源电压的两倍)。基于dll的相位发生器用于产生驱动信号的相位，并且通过修改驱动级也可以抑制5次谐波。输出级和驱动器仅基于逆变器，其中在输出级消除了短路电流。在1 GHz工作时，模拟输出功率为+19.4 dBm，使用1 v电源和5-Ω负载，漏极效率(DE)和功率附加效率(PAE)分别为72%和52%，其中包括基于dll的相位发生器和驱动器的功耗。与传统的d类级相比，三次谐波被抑制23 dB (-33 dBc)。
{"title":"A Class-D stage with harmonic suppression and DLL-based phase generation","authors":"J. Fritzin, B. Mesgarzadeh, A. Alvandpour","doi":"10.1109/MWSCAS.2012.6291953","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6291953","url":null,"abstract":"This paper presents a Class-D stage with 3rd harmonic suppression operating at 2VDD(i.e., twice the nominal supply voltage). A DLL-based phase generator is used to generate the phases of the driving signals and by modifying the driver stage 5th harmonic suppression is also possible. The output stage and drivers are based on inverters only, where the short-circuit current is eliminated in the output stage. Operating at 1 GHz, the simulated output power is +19.4 dBm utilizing a 1-V supply and a 5-Ω load, with Drain Efficiency (DE) and Power-Added Efficiency (PAE) of 72% and 52%, respectively, including power dissipation in the DLL-based phase generator and drivers. The 3rd harmonic is suppressed 23 dB (-33 dBc) compared to a conventional Class-D stage.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128174417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6291967
Martin Wiessflecker, G. Hofer, G. Holweg, W. Pribyl
This paper presents a successive approximation analog to digital converter with a configurable resolution of 8 or 11 bit. The resolutions are achieved by combining an 8 bit split capacitor array with a 3 bit resistive ladder allowing for a simpler layout and good power efficiency. Configurable buffers are included and enable a wide range of operation frequencies. Sample rates between 300S/s and 80kS/s were tested where at the lower frequency a total current consumption of just 8.4nA was measured. A configurable time domain comparator is employed to adapt the noise requirement to the desired resolution. The circuit is developed in a 130nm CMOS technology and occupies an active area of 0.0664mm2.
{"title":"An 11 bit SAR ADC combining a split capacitor array with a resistive ladder and a configurable noise time domain comparator","authors":"Martin Wiessflecker, G. Hofer, G. Holweg, W. Pribyl","doi":"10.1109/MWSCAS.2012.6291967","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6291967","url":null,"abstract":"This paper presents a successive approximation analog to digital converter with a configurable resolution of 8 or 11 bit. The resolutions are achieved by combining an 8 bit split capacitor array with a 3 bit resistive ladder allowing for a simpler layout and good power efficiency. Configurable buffers are included and enable a wide range of operation frequencies. Sample rates between 300S/s and 80kS/s were tested where at the lower frequency a total current consumption of just 8.4nA was measured. A configurable time domain comparator is employed to adapt the noise requirement to the desired resolution. The circuit is developed in a 130nm CMOS technology and occupies an active area of 0.0664mm2.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125993403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6292127
A. Ochoa
Loopgain has long been a defining function in determining stability properties of analog designs. It has surprisingly been ill defined leaving questions on loading and feedforward effects unanswered. In this article I generate a direct method for producing a unique and complete loop gain function using driving point impedance and signal flow graph techniques. In this approach loading and signal paths, feedback and feed forward paths in the amplifier as well as in the feedback net are included. Full feedback is described using two loops, the normal loop-forward amplifier-reverse feedback net loop and a reverse loop in the opposite direction, a symmetrical result.
{"title":"Loop gain in analog design—A new and complete approach","authors":"A. Ochoa","doi":"10.1109/MWSCAS.2012.6292127","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292127","url":null,"abstract":"Loopgain has long been a defining function in determining stability properties of analog designs. It has surprisingly been ill defined leaving questions on loading and feedforward effects unanswered. In this article I generate a direct method for producing a unique and complete loop gain function using driving point impedance and signal flow graph techniques. In this approach loading and signal paths, feedback and feed forward paths in the amplifier as well as in the feedback net are included. Full feedback is described using two loops, the normal loop-forward amplifier-reverse feedback net loop and a reverse loop in the opposite direction, a symmetrical result.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115884223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6292163
D. Sova, C. Radhakrishnan, W. Jenkins, A. D. Salvia
Fault Tolerant Adaptive Filters (FTAFs) rely on inherent learning capabilities of the adaptive process to compensate for transient (soft) or permanent (hard) errors in hardware implementations. This paper investigates fault tolerant transform domain adaptive noise canceling filters to cancel noise from corrupted speech signals. Two transform domain adaptive FIR architectures are compared, one based on the conventional FFT and one on the Modified Discrete Fourier Transform (MDFT), both without zero padding. Results support the fact that the MDFT- based FTAF architecture is able to overcome certain fault conditions that cannot be properly handled with a conventional FFT-based FTAF architecture.
{"title":"Fault tolerant transform domain adaptive noise Canceling from Corrupted Speech Signals","authors":"D. Sova, C. Radhakrishnan, W. Jenkins, A. D. Salvia","doi":"10.1109/MWSCAS.2012.6292163","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292163","url":null,"abstract":"Fault Tolerant Adaptive Filters (FTAFs) rely on inherent learning capabilities of the adaptive process to compensate for transient (soft) or permanent (hard) errors in hardware implementations. This paper investigates fault tolerant transform domain adaptive noise canceling filters to cancel noise from corrupted speech signals. Two transform domain adaptive FIR architectures are compared, one based on the conventional FFT and one on the Modified Discrete Fourier Transform (MDFT), both without zero padding. Results support the fact that the MDFT- based FTAF architecture is able to overcome certain fault conditions that cannot be properly handled with a conventional FFT-based FTAF architecture.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132226466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6292096
Yulong Shi, Degang Chen
Motivated by emerging meandering winding magnetometer (MWM) array based Non-Destructive Evaluation (NDE) applications, this paper presents a new approach for on-chip inductive impedance measurement to enable MWM-array applications to be happened in field, in real-time, and during targets' operation. Different from state of art solutions which rely on high precision analog processing functions to achieve high accuracy, the proposed approach innovatively incorporate bridge circuit, feedback, and resonance concepts to achieve impedance measurement on a single chip. Behavior level simulation demonstrated the measurement algorithm and feasibility of the proposed method.
{"title":"An on-chip inductive impedance measurement method with adaptive measurement range control for MWM-array based NDE applications","authors":"Yulong Shi, Degang Chen","doi":"10.1109/MWSCAS.2012.6292096","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292096","url":null,"abstract":"Motivated by emerging meandering winding magnetometer (MWM) array based Non-Destructive Evaluation (NDE) applications, this paper presents a new approach for on-chip inductive impedance measurement to enable MWM-array applications to be happened in field, in real-time, and during targets' operation. Different from state of art solutions which rely on high precision analog processing functions to achieve high accuracy, the proposed approach innovatively incorporate bridge circuit, feedback, and resonance concepts to achieve impedance measurement on a single chip. Behavior level simulation demonstrated the measurement algorithm and feasibility of the proposed method.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"177 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129981860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6292087
J. Chang, T. Ge, E. Sánchez-Sinencio
Printed electronics is an emerging technology that would likely complement conventional silicon-based electronics in numerous applications. In this paper, we review the different printing/patterning technologies for realizing printed electronics, and the major challenges thereof are delineated. We discuss why printed electronics based on Additive processing (fully-printed) has higher potential for ubiquity than Subtractive processes (non-fully printed). We present our printing process based on fully-printed screen printing, and the characteristics of the ensuing printed transistors and an op-amp. Of specific interest, to the best of our knowledge, the carrier mobility of our fully-printed transistor is the fastest of all reported full-printed transistors, and the fully-printed op-amp is the first fully-printed op-amp.
{"title":"Challenges of printed electronics on flexible substrates","authors":"J. Chang, T. Ge, E. Sánchez-Sinencio","doi":"10.1109/MWSCAS.2012.6292087","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292087","url":null,"abstract":"Printed electronics is an emerging technology that would likely complement conventional silicon-based electronics in numerous applications. In this paper, we review the different printing/patterning technologies for realizing printed electronics, and the major challenges thereof are delineated. We discuss why printed electronics based on Additive processing (fully-printed) has higher potential for ubiquity than Subtractive processes (non-fully printed). We present our printing process based on fully-printed screen printing, and the characteristics of the ensuing printed transistors and an op-amp. Of specific interest, to the best of our knowledge, the carrier mobility of our fully-printed transistor is the fastest of all reported full-printed transistors, and the fully-printed op-amp is the first fully-printed op-amp.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130047738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6292054
M. Sadeghian, J. Stine
This paper presents a method for computing elementary function using optimized number of most significant bits of coefficients along with truncated multipliers for designing linear and quadratic interpolators. The method proposed optimizes the initial coefficient values, which leads to minimize the maximum absolute error of the interpolator output by using a Chebyshev series approximation. The resulting designs can be utilized for any approximation for functions up and beyond 32-bits (IEEE single precision) of precision with smaller requirements for table lookup sizes. Designs for linear and quadratic interpolators that implement f (x) = 1/x are presented and analyzed, although the method can be extended to other functions. This paper demonstrates that optimal coefficient values with high precision and smaller lookup table sizes can be optimally compared to standard coefficients for interpolators.
{"title":"Elementary function approximation using optimized most significant bits of Chebyshev coefficients and truncated multipliers","authors":"M. Sadeghian, J. Stine","doi":"10.1109/MWSCAS.2012.6292054","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292054","url":null,"abstract":"This paper presents a method for computing elementary function using optimized number of most significant bits of coefficients along with truncated multipliers for designing linear and quadratic interpolators. The method proposed optimizes the initial coefficient values, which leads to minimize the maximum absolute error of the interpolator output by using a Chebyshev series approximation. The resulting designs can be utilized for any approximation for functions up and beyond 32-bits (IEEE single precision) of precision with smaller requirements for table lookup sizes. Designs for linear and quadratic interpolators that implement f (x) = 1/x are presented and analyzed, although the method can be extended to other functions. This paper demonstrates that optimal coefficient values with high precision and smaller lookup table sizes can be optimally compared to standard coefficients for interpolators.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131844896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6291949
Myeongwoon Jeon, Sungkyu Chung, Beomju Shin, Jungwoo Lee
NAND multi-level cell (MLC) flash memories are widely used due to low cost and high capacity. However the increased number of levels in MLC results in larger interference and errors. The errors in MLC flash memories tend to be asymmetric and with limited-magnitude. To take advantage of the characteristics, we propose limited-magnitude parity check codes, which can reduce errors more effectively. A key advantage of the proposed method is that it has low complexity for encoding and decoding. Another useful feature of the proposed method is that the code rate and the block size can be chosen almost continuously unlike conventional error correcting codes.
{"title":"Limited magnitude error locating parity check codes for flash memories","authors":"Myeongwoon Jeon, Sungkyu Chung, Beomju Shin, Jungwoo Lee","doi":"10.1109/MWSCAS.2012.6291949","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6291949","url":null,"abstract":"NAND multi-level cell (MLC) flash memories are widely used due to low cost and high capacity. However the increased number of levels in MLC results in larger interference and errors. The errors in MLC flash memories tend to be asymmetric and with limited-magnitude. To take advantage of the characteristics, we propose limited-magnitude parity check codes, which can reduce errors more effectively. A key advantage of the proposed method is that it has low complexity for encoding and decoding. Another useful feature of the proposed method is that the code rate and the block size can be chosen almost continuously unlike conventional error correcting codes.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130698101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-05DOI: 10.1109/MWSCAS.2012.6292022
J. Pons, Jean-Jules Brault, Y. Savaria
For several applications, such as those with low duty-cycles or event-driven activity, for which power consumption is a concern, asynchronous circuit design is very appealing. The main advantages are decreased power consumption and reduced electromagnetic interference (EMI). The NULL Convention Logic™ (NCL) paradigm provides an interesting way to design such circuits. This paper demonstrates that resources usage could be diminished by removing the state-holding capability of the 27 NCL gates. In this paper, we propose and discuss an effective means to obtain such reduced complexity circuits. The modified protocol proposed and validated in this paper leads to a substantial reduction, as high as 50%, of the resources required in a reported example. Moreover, by decreasing the number of gates, energy efficiency as well as operating frequency may be improved.
{"title":"State-holding free NULL Convention Logic™","authors":"J. Pons, Jean-Jules Brault, Y. Savaria","doi":"10.1109/MWSCAS.2012.6292022","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292022","url":null,"abstract":"For several applications, such as those with low duty-cycles or event-driven activity, for which power consumption is a concern, asynchronous circuit design is very appealing. The main advantages are decreased power consumption and reduced electromagnetic interference (EMI). The NULL Convention Logic™ (NCL) paradigm provides an interesting way to design such circuits. This paper demonstrates that resources usage could be diminished by removing the state-holding capability of the 27 NCL gates. In this paper, we propose and discuss an effective means to obtain such reduced complexity circuits. The modified protocol proposed and validated in this paper leads to a substantial reduction, as high as 50%, of the resources required in a reported example. Moreover, by decreasing the number of gates, energy efficiency as well as operating frequency may be improved.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131052337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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