Pub Date : 2020-04-01DOI: 10.1109/VTS48691.2020.9107591
Somayeh Sadeghi Kohan, S. Hellebrand
In today’s system-on-chips, interconnect has an important role and affects the system’s reliability more than in conventional technologies. Interconnects suffer from crosstalk defects that result in delay and glitch faults. Furthermore, fab-induced variations lead to different sizes of crosstalk defects. The largest crosstalk defects are detected by conventional interconnect test methods, while the smaller ones do not change the system behavior and are left without detection. In this paper, we show that even smaller crosstalk defects have an inevitable impact on electro-migration (EM) degradation. They increase the current that conveys through the wire and consequently result in more EM degradation and shorter mean time to failure of the system. Simulation results show that in the worst case the EM degradation increases up to 90%, however, even in the normal situation 7.2% degradation can be observed for the PARSEC 2000 benchmark Because these Hidden Interconnect Defects cause different small delay sizes, we propose a multi-frequency test method to detect them properly. Our experimental results for 8000 different 32-bit interconnect layouts show that, on average, 6 frequencies and 81 test patterns are required for finding hidden interconnect defects.
{"title":"Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects","authors":"Somayeh Sadeghi Kohan, S. Hellebrand","doi":"10.1109/VTS48691.2020.9107591","DOIUrl":"https://doi.org/10.1109/VTS48691.2020.9107591","url":null,"abstract":"In today’s system-on-chips, interconnect has an important role and affects the system’s reliability more than in conventional technologies. Interconnects suffer from crosstalk defects that result in delay and glitch faults. Furthermore, fab-induced variations lead to different sizes of crosstalk defects. The largest crosstalk defects are detected by conventional interconnect test methods, while the smaller ones do not change the system behavior and are left without detection. In this paper, we show that even smaller crosstalk defects have an inevitable impact on electro-migration (EM) degradation. They increase the current that conveys through the wire and consequently result in more EM degradation and shorter mean time to failure of the system. Simulation results show that in the worst case the EM degradation increases up to 90%, however, even in the normal situation 7.2% degradation can be observed for the PARSEC 2000 benchmark Because these Hidden Interconnect Defects cause different small delay sizes, we propose a multi-frequency test method to detect them properly. Our experimental results for 8000 different 32-bit interconnect layouts show that, on average, 6 frequencies and 81 test patterns are required for finding hidden interconnect defects.","PeriodicalId":326132,"journal":{"name":"2020 IEEE 38th VLSI Test Symposium (VTS)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116257090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/VTS48691.2020.9107625
Jhon Gomez, Nektar Xama, Anthony Coyette, Ronny Vanhooren, Wim Dobbelaere, G. Gielen
Test detection of lifetime failures due to latent defects is a necessity to reach the tightening quality requirements of automotive systems. This paper presents a pinhole latent defect model, together with a simulation workflow, that can be used to develop defect-oriented analog test approaches for pinhole latent defects. This work also defines the latent defect coverage and activation coverage, providing the means to compare different test methods under the same rules. Furthermore, a circuit taken from an industrial mixed-signal IC is used as case study. The results show that the typically applied specification tests are insufficient to detect latent defects. It is demonstrated that the coverage can be increased by adding well-selected tests in combination with voltage stress techniques. Doing so, the coverage for the case study is increased by 15x.
{"title":"Pinhole Latent Defect Modeling and Simulation for Defect-Oriented Analog/Mixed-Signal Testing","authors":"Jhon Gomez, Nektar Xama, Anthony Coyette, Ronny Vanhooren, Wim Dobbelaere, G. Gielen","doi":"10.1109/VTS48691.2020.9107625","DOIUrl":"https://doi.org/10.1109/VTS48691.2020.9107625","url":null,"abstract":"Test detection of lifetime failures due to latent defects is a necessity to reach the tightening quality requirements of automotive systems. This paper presents a pinhole latent defect model, together with a simulation workflow, that can be used to develop defect-oriented analog test approaches for pinhole latent defects. This work also defines the latent defect coverage and activation coverage, providing the means to compare different test methods under the same rules. Furthermore, a circuit taken from an industrial mixed-signal IC is used as case study. The results show that the typically applied specification tests are insufficient to detect latent defects. It is demonstrated that the coverage can be increased by adding well-selected tests in combination with voltage stress techniques. Doing so, the coverage for the case study is increased by 15x.","PeriodicalId":326132,"journal":{"name":"2020 IEEE 38th VLSI Test Symposium (VTS)","volume":"41 6 Suppl 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116498783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/VTS48691.2020.9107565
Tong-Yu Hsieh, Pin-Xuan Wu, Chun-Chao Cheng
Images are essential data for many artificial intelligence (AI) systems such as pedestrian detection. However, image processing circuits or image storage devices may produce erroneous image data due to aging or radiation. In this paper we will show that there actually exists much tolerability in image errors. Moreover, for AI systems we find that the tolerability is even larger. This finding provides an attractive reliability enhancement solution by classifying and filtering acceptable images. This solution allows acceptable images to still go to the AI inference process, while unacceptable images are discarded, together with warning signals activated. In this work, we first evaluate and compare error tolerability of images from human and machine perspectives. Then a number of possible test methods to support machine based error-tolerance are discussed and compared in terms of their acceptability classification accuracy and computation cost. In particular, these methods should not need golden (error-free) images as the comparison basis. This greatly facilitates developing a low-cost on-line test architecture to enable a real-time reliability enhancement solution. Our experimental results show that when applying the suggested test method to pedestrian detection, 93.48% of the erroneous images can be correctly classified. The results also show that adopting machine-based error-tolerance can extend MTTF (Mean Time To Failure) of the pedestrian detection system up to additional 88.7%, while human vision based error-tolerance can extend only additional 35.1%.
图像是行人检测等许多人工智能(AI)系统的基本数据。然而，图像处理电路或图像存储设备可能由于老化或辐射而产生错误的图像数据。在本文中，我们将证明图像误差实际上存在很大的容忍度。此外，对于人工智能系统，我们发现容忍度甚至更大。这一发现通过分类和过滤可接受的图像提供了一个有吸引力的可靠性增强解决方案。这种解决方案允许可接受的图像仍然进入AI推理过程，而不可接受的图像被丢弃，并激活警告信号。在这项工作中，我们首先从人和机器的角度评估和比较图像的误差容忍度。然后讨论了支持机器容错的几种可能的测试方法，并从可接受性、分类精度和计算成本等方面进行了比较。特别是，这些方法不应该需要黄金(无误差)图像作为比较基础。这极大地促进了开发低成本在线测试体系结构，从而实现实时可靠性增强解决方案。实验结果表明，将本文提出的测试方法应用于行人检测时，可以正确分类出93.48%的错误图像。结果还表明，采用基于机器的容错可以将行人检测系统的MTTF (Mean Time To Failure)提高88.7%，而基于人类视觉的容错仅能提高35.1%。
{"title":"On Classification of Acceptable Images for Reliable Artificial Intelligence Systems: A Case Study on Pedestrian Detection","authors":"Tong-Yu Hsieh, Pin-Xuan Wu, Chun-Chao Cheng","doi":"10.1109/VTS48691.2020.9107565","DOIUrl":"https://doi.org/10.1109/VTS48691.2020.9107565","url":null,"abstract":"Images are essential data for many artificial intelligence (AI) systems such as pedestrian detection. However, image processing circuits or image storage devices may produce erroneous image data due to aging or radiation. In this paper we will show that there actually exists much tolerability in image errors. Moreover, for AI systems we find that the tolerability is even larger. This finding provides an attractive reliability enhancement solution by classifying and filtering acceptable images. This solution allows acceptable images to still go to the AI inference process, while unacceptable images are discarded, together with warning signals activated. In this work, we first evaluate and compare error tolerability of images from human and machine perspectives. Then a number of possible test methods to support machine based error-tolerance are discussed and compared in terms of their acceptability classification accuracy and computation cost. In particular, these methods should not need golden (error-free) images as the comparison basis. This greatly facilitates developing a low-cost on-line test architecture to enable a real-time reliability enhancement solution. Our experimental results show that when applying the suggested test method to pedestrian detection, 93.48% of the erroneous images can be correctly classified. The results also show that adopting machine-based error-tolerance can extend MTTF (Mean Time To Failure) of the pedestrian detection system up to additional 88.7%, while human vision based error-tolerance can extend only additional 35.1%.","PeriodicalId":326132,"journal":{"name":"2020 IEEE 38th VLSI Test Symposium (VTS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123170743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/VTS48691.2020.9107572
J. E. R. Condia, Pierpaolo Narducci, M. Reorda, L. Sterpone
General Purpose Graphic Processing Units (GPGPUs) are effective solutions for high-demanding data processing applications. Recently, they started to be used even in safety-critical applications, such as autonomous car driving systems. GPGPUs are implemented using the latest semiconductor technologies, which are more prone to faults arising during the lifetime operation. However, until now fault mitigation solutions were not extensively included in GPGPUs, due to the limited reliability requirements of the applications they were originally intended for (e.g., gaming or multimedia). This work proposes a dynamically configurable self- repairing mechanism aimed at mitigating the impact of permanent faults in the Scalar Processor (SP) cores in GPGPUs. The mechanism is based on spare modules that can be used to replace faulty SPs when a fault is detected. A configuration instruction allows dynamically controlling in software the selection of the set of active SPs in the SM. The method is extremely flexible since it does not require any change in the application software. Experimental results show that the solution introduces a moderate area overhead while allowing continue working even in the case of any permanent faults affecting the SPs.
{"title":"A dynamic reconfiguration mechanism to increase the reliability of GPGPUs","authors":"J. E. R. Condia, Pierpaolo Narducci, M. Reorda, L. Sterpone","doi":"10.1109/VTS48691.2020.9107572","DOIUrl":"https://doi.org/10.1109/VTS48691.2020.9107572","url":null,"abstract":"General Purpose Graphic Processing Units (GPGPUs) are effective solutions for high-demanding data processing applications. Recently, they started to be used even in safety-critical applications, such as autonomous car driving systems. GPGPUs are implemented using the latest semiconductor technologies, which are more prone to faults arising during the lifetime operation. However, until now fault mitigation solutions were not extensively included in GPGPUs, due to the limited reliability requirements of the applications they were originally intended for (e.g., gaming or multimedia). This work proposes a dynamically configurable self- repairing mechanism aimed at mitigating the impact of permanent faults in the Scalar Processor (SP) cores in GPGPUs. The mechanism is based on spare modules that can be used to replace faulty SPs when a fault is detected. A configuration instruction allows dynamically controlling in software the selection of the set of active SPs in the SM. The method is extremely flexible since it does not require any change in the application software. Experimental results show that the solution introduces a moderate area overhead while allowing continue working even in the case of any permanent faults affecting the SPs.","PeriodicalId":326132,"journal":{"name":"2020 IEEE 38th VLSI Test Symposium (VTS)","volume":"243 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127535306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/VTS48691.2020.9107564
M. Collantes, Zahra Ghodsi, S. Garg
We present Safe-TPU, a framework for secure computations of Deep Neural Networks (DNNs) in untrusted hardware corrupted by Trojans or fault injection attacks. This work leverages previous advances on interactive proof (IP) systems for verifying, at run-time, the correctness of a neural network’s computations, and makes three new contributions: (1) We present a Trojan resilient DNN hardware accelerator based on interactive proofs; (2) We introduce new protocol enhancements that significantly reduce the space and time required to generate proofs; and (3) we propose an implementation of Safe-TPU with high parallelism and reuse of existing resources already deployed in the baseline DNN accelerator. We prototype Safe-TPU on an FPGA and analyze its security guarantees. Experimentally, we show that Safe-TPU’s area overhead is small (28%) over the baseline DNN accelerator and is 3.15× faster than state-of-the-art, while at the same time, Safe-TPU guarantees to catch, with high probability, any incorrect computations.
{"title":"SafeTPU: A Verifiably Secure Hardware Accelerator for Deep Neural Networks","authors":"M. Collantes, Zahra Ghodsi, S. Garg","doi":"10.1109/VTS48691.2020.9107564","DOIUrl":"https://doi.org/10.1109/VTS48691.2020.9107564","url":null,"abstract":"We present Safe-TPU, a framework for secure computations of Deep Neural Networks (DNNs) in untrusted hardware corrupted by Trojans or fault injection attacks. This work leverages previous advances on interactive proof (IP) systems for verifying, at run-time, the correctness of a neural network’s computations, and makes three new contributions: (1) We present a Trojan resilient DNN hardware accelerator based on interactive proofs; (2) We introduce new protocol enhancements that significantly reduce the space and time required to generate proofs; and (3) we propose an implementation of Safe-TPU with high parallelism and reuse of existing resources already deployed in the baseline DNN accelerator. We prototype Safe-TPU on an FPGA and analyze its security guarantees. Experimentally, we show that Safe-TPU’s area overhead is small (28%) over the baseline DNN accelerator and is 3.15× faster than state-of-the-art, while at the same time, Safe-TPU guarantees to catch, with high probability, any incorrect computations.","PeriodicalId":326132,"journal":{"name":"2020 IEEE 38th VLSI Test Symposium (VTS)","volume":"4585 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126481145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/VTS48691.2020.9107559
Y. Tuncel, Ganapati Bhat, U. Ogras
Recent developments in stretchable and flexible sensing and processing technologies enable a wide range of wearable devices. These devices can pave the way to medical applications ranging from health and activity monitoring to diagnosis and treatments of movement disorders. However, recent studies show that this potential is hindered by both adaptation challenges that affect the end users and technology challenges faced by developers. This paper first summarizes the challenges faced by wearable devices targeting health and user activity monitoring applications. Then, it reviews recent research progress towards addressing these challenges in energy harvesting, energy management, flexible system design, and test areas.
{"title":"Special Session: Physically Flexible Devices for Health and Activity Monitoring: Challenges from Design to Test","authors":"Y. Tuncel, Ganapati Bhat, U. Ogras","doi":"10.1109/VTS48691.2020.9107559","DOIUrl":"https://doi.org/10.1109/VTS48691.2020.9107559","url":null,"abstract":"Recent developments in stretchable and flexible sensing and processing technologies enable a wide range of wearable devices. These devices can pave the way to medical applications ranging from health and activity monitoring to diagnosis and treatments of movement disorders. However, recent studies show that this potential is hindered by both adaptation challenges that affect the end users and technology challenges faced by developers. This paper first summarizes the challenges faced by wearable devices targeting health and user activity monitoring applications. Then, it reviews recent research progress towards addressing these challenges in energy harvesting, energy management, flexible system design, and test areas.","PeriodicalId":326132,"journal":{"name":"2020 IEEE 38th VLSI Test Symposium (VTS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130987288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/VTS48691.2020.9107567
S. Chakravarty, Fei Su, Indira A Gohad, Sudheer V Bandana, B. S. Adithya, W. M. Lim
Many semi-conductor manufacturing companies use 3D interconnect technology to flexibly combine smaller heterogeneous designs in a system-on-package. Internal I/O (IIO) are placed at two ends of the inter-die interconnect. Small dimension of IIOs prohibits tester probing. This, along with the very large number of inter-die interconnects poses a serious challenge to robustly test these interconnects. This is a hindrance to adopting 3D interconnect technologies. This paper discusses the difference between IIO testing and GPIO, HSIO testing. A novel IIO BIST solution, which removes a major obstacle for adopting 3D-interconnect technology, is presented.
{"title":"Internal I/O Testing: Definition and a Solution","authors":"S. Chakravarty, Fei Su, Indira A Gohad, Sudheer V Bandana, B. S. Adithya, W. M. Lim","doi":"10.1109/VTS48691.2020.9107567","DOIUrl":"https://doi.org/10.1109/VTS48691.2020.9107567","url":null,"abstract":"Many semi-conductor manufacturing companies use 3D interconnect technology to flexibly combine smaller heterogeneous designs in a system-on-package. Internal I/O (IIO) are placed at two ends of the inter-die interconnect. Small dimension of IIOs prohibits tester probing. This, along with the very large number of inter-die interconnects poses a serious challenge to robustly test these interconnects. This is a hindrance to adopting 3D interconnect technologies. This paper discusses the difference between IIO testing and GPIO, HSIO testing. A novel IIO BIST solution, which removes a major obstacle for adopting 3D-interconnect technology, is presented.","PeriodicalId":326132,"journal":{"name":"2020 IEEE 38th VLSI Test Symposium (VTS)","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131913933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/VTS48691.2020.9107556
I. Pomeranz
A test set for transition faults detects smaller delay defects if transition faults are detected through longer paths. Conversely, this paper observes that it is advantageous for a test set for path delay faults, which targets small delay defects, to detect larger delay defects along the paths. The paper defines a notion of masking that prevents larger delay defects from being detected. It defines a non-masking non-robust test for a path delay fault that guarantees the detection of larger delay defects along the path. It also defines masking metrics that allow the level of masking of larger delay defects for a test, and a test set, to be evaluated. Using these metrics, the paper describes a procedure that computes a test set for path delay faults with reduced levels of masking for larger delay defects. Experimental results are presented to demonstrate the extent to which masking of larger delay defects occurs under tests for path delay faults in benchmark circuits.
{"title":"Non-Masking Non-Robust Tests for Path Delay Faults","authors":"I. Pomeranz","doi":"10.1109/VTS48691.2020.9107556","DOIUrl":"https://doi.org/10.1109/VTS48691.2020.9107556","url":null,"abstract":"A test set for transition faults detects smaller delay defects if transition faults are detected through longer paths. Conversely, this paper observes that it is advantageous for a test set for path delay faults, which targets small delay defects, to detect larger delay defects along the paths. The paper defines a notion of masking that prevents larger delay defects from being detected. It defines a non-masking non-robust test for a path delay fault that guarantees the detection of larger delay defects along the path. It also defines masking metrics that allow the level of masking of larger delay defects for a test, and a test set, to be evaluated. Using these metrics, the paper describes a procedure that computes a test set for path delay faults with reduced levels of masking for larger delay defects. Experimental results are presented to demonstrate the extent to which masking of larger delay defects occurs under tests for path delay faults in benchmark circuits.","PeriodicalId":326132,"journal":{"name":"2020 IEEE 38th VLSI Test Symposium (VTS)","volume":"166 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116428156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/VTS48691.2020.9107582
Zizhen Liu, Jing Ye, Xing Hu, Huawei Li, Xiaowei Li, Yu Hu
With the rapid development of deep learning techniques, the security issue for Neural Network (NN) systems has emerged as an urgent and severe problem. Hardware Trojan attack is one of the threatens, which provides attackers backdoors to control the prediction results of NN systems. This paper proposes a sequence triggered hardware Trojan. Normal images but with specific sequence are used to trigger the hardware Trojan and let attackers fully control the prediction results. This kind of trigger is not only robust to image pre-processing, but also unrecognizable by human beings. In comparison with existing hardware Trojan design, it is more practical and less hardware overhead. The experiments on MNIST, CIFAR100, and ISLVRC show that the proposed hardware Trojan is rarely triggered in normal working status while the hardware cost is reduced by 19X.
{"title":"Sequence Triggered Hardware Trojan in Neural Network Accelerator","authors":"Zizhen Liu, Jing Ye, Xing Hu, Huawei Li, Xiaowei Li, Yu Hu","doi":"10.1109/VTS48691.2020.9107582","DOIUrl":"https://doi.org/10.1109/VTS48691.2020.9107582","url":null,"abstract":"With the rapid development of deep learning techniques, the security issue for Neural Network (NN) systems has emerged as an urgent and severe problem. Hardware Trojan attack is one of the threatens, which provides attackers backdoors to control the prediction results of NN systems. This paper proposes a sequence triggered hardware Trojan. Normal images but with specific sequence are used to trigger the hardware Trojan and let attackers fully control the prediction results. This kind of trigger is not only robust to image pre-processing, but also unrecognizable by human beings. In comparison with existing hardware Trojan design, it is more practical and less hardware overhead. The experiments on MNIST, CIFAR100, and ISLVRC show that the proposed hardware Trojan is rarely triggered in normal working status while the hardware cost is reduced by 19X.","PeriodicalId":326132,"journal":{"name":"2020 IEEE 38th VLSI Test Symposium (VTS)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130133342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/VTS48691.2020.9107616
Praise O. Farayola, Shravan K. Chaganti, Abdullah O. Obaidi, Abalhassan Sheikh, S. Ravi, Degang Chen
Multi-site testing saves test time and tests cost by screening multiple chips at once. However, it comes with its issues. As test engineers increase the number of sites on each tester to further save test time and cost, variations are now being observed in measurements from site to site which do not correspond to actual problems in the devices under test. Thus, a cost-effective way to investigate site to site variations and identify sites with issues needs to be developed to ensure high test quality and to rule out possible problems arising from the test hardware. In this paper, regression fitting on a quantile-quantile curve is used to compare the distribution of each site to a theoretical and expected distribution. This is shown to pronounce site to site variations inherent in test data, hence identifying issue-ridden sites with ease. The quantile-quantile plot compares the integrals of two probability density functions in a single plot, thus capturing the location, scale, and skewness of the test data set. This method provides more information to the test engineer than classical statistical methods that rely on single test statistics for distribution comparison and is at no extra cost.
{"title":"Quantile – Quantile Fitting Approach to Detect Site to Site Variations in Massive Multi-site Testing","authors":"Praise O. Farayola, Shravan K. Chaganti, Abdullah O. Obaidi, Abalhassan Sheikh, S. Ravi, Degang Chen","doi":"10.1109/VTS48691.2020.9107616","DOIUrl":"https://doi.org/10.1109/VTS48691.2020.9107616","url":null,"abstract":"Multi-site testing saves test time and tests cost by screening multiple chips at once. However, it comes with its issues. As test engineers increase the number of sites on each tester to further save test time and cost, variations are now being observed in measurements from site to site which do not correspond to actual problems in the devices under test. Thus, a cost-effective way to investigate site to site variations and identify sites with issues needs to be developed to ensure high test quality and to rule out possible problems arising from the test hardware. In this paper, regression fitting on a quantile-quantile curve is used to compare the distribution of each site to a theoretical and expected distribution. This is shown to pronounce site to site variations inherent in test data, hence identifying issue-ridden sites with ease. The quantile-quantile plot compares the integrals of two probability density functions in a single plot, thus capturing the location, scale, and skewness of the test data set. This method provides more information to the test engineer than classical statistical methods that rely on single test statistics for distribution comparison and is at no extra cost.","PeriodicalId":326132,"journal":{"name":"2020 IEEE 38th VLSI Test Symposium (VTS)","volume":"43 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130852369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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