Pub Date : 2020-04-01DOI: 10.1109/VTS48691.2020.9107604
Jui-Hung Hung, Shih-Hsu Huang, Chun-Hua Cheng, Hsu-Yu Kao, W. Cheng
A reconfigurable wrapper provides the flexibility for a core test to utilize different bandwidths of test access mechanism (TAM) at different test time points. By using reconfigurable wrappers, the lower bound of total test application time can be achieved. However, since reconfigurable wrappers attempt to utilize TAM bandwidth as fully as possible, they often consume a lot of routing resources. In advanced technology nodes, routability has become a critical and difficult issue. In this paper, based on reconfigurable wrappers, we present the first work that studies the correlation between grid-based TAM wire routing and test scheduling. Our objective is to derive a feasible grid-based TAM wire routing solution with the minimum total test application time. Compared with previous works, the main advantage of our approach is that it can resolve the grid-based TAM wire routing congestion problem during test scheduling. Benchmark data show that our approach can effectively and efficiently minimize the total test application time under grid-based routing congestion constraints.
{"title":"Co-Optimization of Grid-Based TAM Wire Routing and Test Scheduling with Reconfigurable Wrappers","authors":"Jui-Hung Hung, Shih-Hsu Huang, Chun-Hua Cheng, Hsu-Yu Kao, W. Cheng","doi":"10.1109/VTS48691.2020.9107604","DOIUrl":"https://doi.org/10.1109/VTS48691.2020.9107604","url":null,"abstract":"A reconfigurable wrapper provides the flexibility for a core test to utilize different bandwidths of test access mechanism (TAM) at different test time points. By using reconfigurable wrappers, the lower bound of total test application time can be achieved. However, since reconfigurable wrappers attempt to utilize TAM bandwidth as fully as possible, they often consume a lot of routing resources. In advanced technology nodes, routability has become a critical and difficult issue. In this paper, based on reconfigurable wrappers, we present the first work that studies the correlation between grid-based TAM wire routing and test scheduling. Our objective is to derive a feasible grid-based TAM wire routing solution with the minimum total test application time. Compared with previous works, the main advantage of our approach is that it can resolve the grid-based TAM wire routing congestion problem during test scheduling. Benchmark data show that our approach can effectively and efficiently minimize the total test application time under grid-based routing congestion constraints.","PeriodicalId":326132,"journal":{"name":"2020 IEEE 38th VLSI Test Symposium (VTS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130520942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/VTS48691.2020.9107597
D. Xiang, J. Cai, Bo Liu
A new weighted pseudo-random test generator called wPRPG is proposed for low-power launch-on-capture (LOC) transition delay fault testing. The low-power weighted PRPG is implemented by assigning different weights on the test enable signals and applying a gating technique. The new low-power PRPG can achieve much higher transition delay fault coverage in LOC delay testing than the conventional test-per-scan PRPG.
{"title":"Low-Power Weighted Pseudo-Random Test Pattern Generation for Launch-on-Capture Delay Testing*","authors":"D. Xiang, J. Cai, Bo Liu","doi":"10.1109/VTS48691.2020.9107597","DOIUrl":"https://doi.org/10.1109/VTS48691.2020.9107597","url":null,"abstract":"A new weighted pseudo-random test generator called wPRPG is proposed for low-power launch-on-capture (LOC) transition delay fault testing. The low-power weighted PRPG is implemented by assigning different weights on the test enable signals and applying a gating technique. The new low-power PRPG can achieve much higher transition delay fault coverage in LOC delay testing than the conventional test-per-scan PRPG.","PeriodicalId":326132,"journal":{"name":"2020 IEEE 38th VLSI Test Symposium (VTS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121369359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/VTS48691.2020.9107600
Xingyi Wang, Li Jiang, K. Chakrabarty
Intermittent faults are a critical reliability threat in deep submicron VLSI circuits. These faults occur non-deterministically due to unstable hardware and unpredictable operating conditions; they are activated/deactivated with changes in the runtime environment. Online fault prediction models are commonly used to predict soft errors and aging effects. A small set of flip-flops, whose states constitute the signature, conveys information about the fine-grained behavior of the circuit, and serves as the input to a machine-learning (ML) model. The nondeterministic failure mechanisms of intermittent faults, however, result in temporally- and spatially-correlated signatures (TSC-signatures). Moreover, the high-dimensional time-series features impede the use of traditional ML models for intermittent-fault detection. To cope with this challenge, we adapt the TSC-signatures to existing ML detection models. Moreover, we propose a novel detection model based on Recurrent Neural Network with Long Short-Term Memory (LSTM) that is inherently suitable for this problem. Simulation results for the ITC99 benchmark circuits highlight the effectiveness of the proposed model.
{"title":"LSTM-based Analysis of Temporally- and Spatially-Correlated Signatures for Intermittent Fault Detection","authors":"Xingyi Wang, Li Jiang, K. Chakrabarty","doi":"10.1109/VTS48691.2020.9107600","DOIUrl":"https://doi.org/10.1109/VTS48691.2020.9107600","url":null,"abstract":"Intermittent faults are a critical reliability threat in deep submicron VLSI circuits. These faults occur non-deterministically due to unstable hardware and unpredictable operating conditions; they are activated/deactivated with changes in the runtime environment. Online fault prediction models are commonly used to predict soft errors and aging effects. A small set of flip-flops, whose states constitute the signature, conveys information about the fine-grained behavior of the circuit, and serves as the input to a machine-learning (ML) model. The nondeterministic failure mechanisms of intermittent faults, however, result in temporally- and spatially-correlated signatures (TSC-signatures). Moreover, the high-dimensional time-series features impede the use of traditional ML models for intermittent-fault detection. To cope with this challenge, we adapt the TSC-signatures to existing ML detection models. Moreover, we propose a novel detection model based on Recurrent Neural Network with Long Short-Term Memory (LSTM) that is inherently suitable for this problem. Simulation results for the ITC99 benchmark circuits highlight the effectiveness of the proposed model.","PeriodicalId":326132,"journal":{"name":"2020 IEEE 38th VLSI Test Symposium (VTS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128494825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/VTS48691.2020.9107588
Churan Tang, Pengkun Liu, Cunqing Ma, Zongbin Liu, Jingquan Ge
Flush based cache attacks have become a practical threat to data privacy and information security due to their advantages such as high accuracy and resolution. However, their accuracy and resolution still has room for improvement. In addition, although most of the attacks have been demonstrated on x86 processors, few of them have been executed on ARM devices. We propose a high accuracy, high resolution flush based cache attack, Flush+Time. This technique solves two important challenges for cache attacks on ARM: how to flush cache lines and how to achieve precise timing. Experiments show that Flush+Time increases accuracy from 95.1% of Flush+Reload, the most powerful general cache attack so far, to 99.3%. Flush+Time has a 30.5% higher resolution than Flush+Reload, but its execution time is only 0.59 times that of Spectre.
{"title":"Flush+Time: A High Accuracy and High Resolution Cache Attack On ARM-FPGA Embedded SoC","authors":"Churan Tang, Pengkun Liu, Cunqing Ma, Zongbin Liu, Jingquan Ge","doi":"10.1109/VTS48691.2020.9107588","DOIUrl":"https://doi.org/10.1109/VTS48691.2020.9107588","url":null,"abstract":"Flush based cache attacks have become a practical threat to data privacy and information security due to their advantages such as high accuracy and resolution. However, their accuracy and resolution still has room for improvement. In addition, although most of the attacks have been demonstrated on x86 processors, few of them have been executed on ARM devices. We propose a high accuracy, high resolution flush based cache attack, Flush+Time. This technique solves two important challenges for cache attacks on ARM: how to flush cache lines and how to achieve precise timing. Experiments show that Flush+Time increases accuracy from 95.1% of Flush+Reload, the most powerful general cache attack so far, to 99.3%. Flush+Time has a 30.5% higher resolution than Flush+Reload, but its execution time is only 0.59 times that of Spectre.","PeriodicalId":326132,"journal":{"name":"2020 IEEE 38th VLSI Test Symposium (VTS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123184403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In order to reduce DPPM (defect parts per million), IDDQ testing methodology can be exploited for identifying "outliers" which are potentially defective but not detected by signoff functional and parametric tests. Conventional IDDQ testing paradigms depending on a simple statistical 6σ rule or engineers’ experience are usually too conservative to effectively identify non-trivial outliers, especially when spatial correlations are of great concern/influence. In this paper, by employing a stochastic regression model, the mean as well as the variance of the IDDQ of a die under test (DUT) can be predicted. According to the predicted mean and variance, we derive an expected IDDQ range and identify the DUT as an outlier if its actual IDDQ measurement is beyond the expected range. The proposed stochastic regression model is obtained by training a convolutional neural network (CNN) and, based on its primitive property of convolutional kernel mapping with large volume of industrial data, spatial correlations (due to spatially-correlated process variations, etc) can be considered/captured. The trained data-driven CNN is highly accurate in terms of R-square (0.958) and RMSE (0.783), and the percentage of identified outliers (0.047%) is very close to the theoretical reference (0.050%), which validates the efficacy of our proposed methodology.
{"title":"CNN-based Stochastic Regression for IDDQ Outlier Identification","authors":"Chun-Teng Chen, Chia-Heng Yen, Cheng Wen, Cheng-Hao Yang, Kai-Chiang Wu, Mason Chern, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Shu-Yi Kao, M. Chao","doi":"10.1109/VTS48691.2020.9107570","DOIUrl":"https://doi.org/10.1109/VTS48691.2020.9107570","url":null,"abstract":"In order to reduce DPPM (defect parts per million), IDDQ testing methodology can be exploited for identifying \"outliers\" which are potentially defective but not detected by signoff functional and parametric tests. Conventional IDDQ testing paradigms depending on a simple statistical 6σ rule or engineers’ experience are usually too conservative to effectively identify non-trivial outliers, especially when spatial correlations are of great concern/influence. In this paper, by employing a stochastic regression model, the mean as well as the variance of the IDDQ of a die under test (DUT) can be predicted. According to the predicted mean and variance, we derive an expected IDDQ range and identify the DUT as an outlier if its actual IDDQ measurement is beyond the expected range. The proposed stochastic regression model is obtained by training a convolutional neural network (CNN) and, based on its primitive property of convolutional kernel mapping with large volume of industrial data, spatial correlations (due to spatially-correlated process variations, etc) can be considered/captured. The trained data-driven CNN is highly accurate in terms of R-square (0.958) and RMSE (0.783), and the percentage of identified outliers (0.047%) is very close to the theoretical reference (0.050%), which validates the efficacy of our proposed methodology.","PeriodicalId":326132,"journal":{"name":"2020 IEEE 38th VLSI Test Symposium (VTS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121537005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/VTS48691.2020.9107566
Qidong Wang, Aijiao Cui, G. Qu, Huawei Li
Scan-based side-channel attack has become a new threat to cryptographic chips. Many countermeasures are proposed to safeguard scan design against the scan-based attacks. Among which, the methods based on lock and key scheme present more effective and popular. In this paper, we propose a new lock and key scheme which adopts physical unclonable function (PUF) design to generate a unique key for each design. The uniqueness of PUF enables each chip taped out from one mask to possess a different golden key. Once the PUF is invoked for the first time, the PUF response will be hardcoded into the design so that even the environment changes, the PUF-based key maintains. The proposed secure scan design with PUF-based key can protect the cryptographic chips against all known scan-based side-channel attacks while incurring negligible overhead.
{"title":"A New Secure Scan Design with PUF-based Key for Authentication","authors":"Qidong Wang, Aijiao Cui, G. Qu, Huawei Li","doi":"10.1109/VTS48691.2020.9107566","DOIUrl":"https://doi.org/10.1109/VTS48691.2020.9107566","url":null,"abstract":"Scan-based side-channel attack has become a new threat to cryptographic chips. Many countermeasures are proposed to safeguard scan design against the scan-based attacks. Among which, the methods based on lock and key scheme present more effective and popular. In this paper, we propose a new lock and key scheme which adopts physical unclonable function (PUF) design to generate a unique key for each design. The uniqueness of PUF enables each chip taped out from one mask to possess a different golden key. Once the PUF is invoked for the first time, the PUF response will be hardcoded into the design so that even the environment changes, the PUF-based key maintains. The proposed secure scan design with PUF-based key can protect the cryptographic chips against all known scan-based side-channel attacks while incurring negligible overhead.","PeriodicalId":326132,"journal":{"name":"2020 IEEE 38th VLSI Test Symposium (VTS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133758766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/VTS48691.2020.9107627
Brett Sparkman, S. Smith, J. Di
While a number of methods exist for asynchronous circuit synthesis, there are limited applicable test methodologies. This paper presents a Built-In Self-Test (BIST) method for Multi-Threshold NULL Convention Logic (MTNCL) asynchronous circuits, which utilizes standard synchronous tools, and is automated to achieve maximum fault coverage while minimizing area overhead and test time.
{"title":"Built-In Self-Test for Multi-Threshold NULL Convention Logic Asynchronous Circuits","authors":"Brett Sparkman, S. Smith, J. Di","doi":"10.1109/VTS48691.2020.9107627","DOIUrl":"https://doi.org/10.1109/VTS48691.2020.9107627","url":null,"abstract":"While a number of methods exist for asynchronous circuit synthesis, there are limited applicable test methodologies. This paper presents a Built-In Self-Test (BIST) method for Multi-Threshold NULL Convention Logic (MTNCL) asynchronous circuits, which utilizes standard synchronous tools, and is automated to achieve maximum fault coverage while minimizing area overhead and test time.","PeriodicalId":326132,"journal":{"name":"2020 IEEE 38th VLSI Test Symposium (VTS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131933025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/VTS48691.2020.9107638
Zhen Gao, Lingling Zhang, Ruishi Han, P. Reviriego, Zhiqiang Li
Turbo codes are widely used in satellite communications. When a Turbo decoder is implemented on a Field Programmable Gate Array (FPGA) in a space platform, it will suffer Single Event Upsets (SEUs) that can cause failures and disrupt communications. In this paper, the reliability of Turbo decoders implemented on FPGAs is evaluated. The Turbo decoder with Log-MAP algorithm is implemented on an SRAM-FPGA. Then, fault injection experiments are conducted to simulate the effects of SEU on the user memory and on the configuration memory of the Turbo decoder. Experimental results show that, for user memory, the SEU tolerance rate is over 95%, and the effect of SEU is related to the iteration period, bit position and Signal to Noise Ratio (SNR). In particular, SEUs on the control/address registers and on the interleaving table have a larger impact than on other registers or memories. For the configuration memory, the SEU tolerance rate is higher than 86%, and decreases as SNR increases. In general, the Turbo decoder exhibits a high reliability against SEUs, and the user memory is more reliable than the configuration memory.
{"title":"Reliability Evaluation of Turbo Decoders Implemented on SRAM-FPGAs","authors":"Zhen Gao, Lingling Zhang, Ruishi Han, P. Reviriego, Zhiqiang Li","doi":"10.1109/VTS48691.2020.9107638","DOIUrl":"https://doi.org/10.1109/VTS48691.2020.9107638","url":null,"abstract":"Turbo codes are widely used in satellite communications. When a Turbo decoder is implemented on a Field Programmable Gate Array (FPGA) in a space platform, it will suffer Single Event Upsets (SEUs) that can cause failures and disrupt communications. In this paper, the reliability of Turbo decoders implemented on FPGAs is evaluated. The Turbo decoder with Log-MAP algorithm is implemented on an SRAM-FPGA. Then, fault injection experiments are conducted to simulate the effects of SEU on the user memory and on the configuration memory of the Turbo decoder. Experimental results show that, for user memory, the SEU tolerance rate is over 95%, and the effect of SEU is related to the iteration period, bit position and Signal to Noise Ratio (SNR). In particular, SEUs on the control/address registers and on the interleaving table have a larger impact than on other registers or memories. For the configuration memory, the SEU tolerance rate is higher than 86%, and decreases as SNR increases. In general, the Turbo decoder exhibits a high reliability against SEUs, and the user memory is more reliable than the configuration memory.","PeriodicalId":326132,"journal":{"name":"2020 IEEE 38th VLSI Test Symposium (VTS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123519520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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