Pub Date : 2020-04-01DOI: 10.1109/VTS48691.2020.9107567
S. Chakravarty, Fei Su, Indira A Gohad, Sudheer V Bandana, B. S. Adithya, W. M. Lim
Many semi-conductor manufacturing companies use 3D interconnect technology to flexibly combine smaller heterogeneous designs in a system-on-package. Internal I/O (IIO) are placed at two ends of the inter-die interconnect. Small dimension of IIOs prohibits tester probing. This, along with the very large number of inter-die interconnects poses a serious challenge to robustly test these interconnects. This is a hindrance to adopting 3D interconnect technologies. This paper discusses the difference between IIO testing and GPIO, HSIO testing. A novel IIO BIST solution, which removes a major obstacle for adopting 3D-interconnect technology, is presented.
{"title":"Internal I/O Testing: Definition and a Solution","authors":"S. Chakravarty, Fei Su, Indira A Gohad, Sudheer V Bandana, B. S. Adithya, W. M. Lim","doi":"10.1109/VTS48691.2020.9107567","DOIUrl":"https://doi.org/10.1109/VTS48691.2020.9107567","url":null,"abstract":"Many semi-conductor manufacturing companies use 3D interconnect technology to flexibly combine smaller heterogeneous designs in a system-on-package. Internal I/O (IIO) are placed at two ends of the inter-die interconnect. Small dimension of IIOs prohibits tester probing. This, along with the very large number of inter-die interconnects poses a serious challenge to robustly test these interconnects. This is a hindrance to adopting 3D interconnect technologies. This paper discusses the difference between IIO testing and GPIO, HSIO testing. A novel IIO BIST solution, which removes a major obstacle for adopting 3D-interconnect technology, is presented.","PeriodicalId":326132,"journal":{"name":"2020 IEEE 38th VLSI Test Symposium (VTS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131913933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-02-18DOI: 10.1109/VTS48691.2020.9107629
Shervin Roshanisefat, Hadi Mardani Kamali, K. Z. Azar, Sai Manoj Pudukotai Dinakarrao, Naghmeh Karimi, H. Homayoun, Avesta Sasan
In this paper, we introduce DFSSD, a novel logic locking solution for sequential and FSM circuits with a restricted (locked) access to the scan chain. DFSSD combines two techniques for obfuscation: (1) Deep Faults, and (2) Shallow State Duality. Both techniques are specifically designed to resist against sequential SAT attacks based on bounded model checking. The shallow state duality prevents a sequential SAT attack from taking a shortcut for early termination without running an exhaustive unbounded model checker to assess if the attack could be terminated. The deep fault, on the other hand, provides a designer with a technique for building deep, yet key recoverable faults that could not be discovered by sequential SAT (and bounded model checker based) attacks in a reasonable time.
{"title":"DFSSD: Deep Faults and Shallow State Duality, A Provably Strong Obfuscation Solution for Circuits with Restricted Access to Scan Chain","authors":"Shervin Roshanisefat, Hadi Mardani Kamali, K. Z. Azar, Sai Manoj Pudukotai Dinakarrao, Naghmeh Karimi, H. Homayoun, Avesta Sasan","doi":"10.1109/VTS48691.2020.9107629","DOIUrl":"https://doi.org/10.1109/VTS48691.2020.9107629","url":null,"abstract":"In this paper, we introduce DFSSD, a novel logic locking solution for sequential and FSM circuits with a restricted (locked) access to the scan chain. DFSSD combines two techniques for obfuscation: (1) Deep Faults, and (2) Shallow State Duality. Both techniques are specifically designed to resist against sequential SAT attacks based on bounded model checking. The shallow state duality prevents a sequential SAT attack from taking a shortcut for early termination without running an exhaustive unbounded model checker to assess if the attack could be terminated. The deep fault, on the other hand, provides a designer with a technique for building deep, yet key recoverable faults that could not be discovered by sequential SAT (and bounded model checker based) attacks in a reasonable time.","PeriodicalId":326132,"journal":{"name":"2020 IEEE 38th VLSI Test Symposium (VTS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-02-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130763720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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