Pub Date : 2017-12-01DOI: 10.1109/EDAPS.2017.8276916
Xiang-ting Wang, Xiaochun Li, J. Mao
In this paper, a novel microstrip transmission line structure based on the electromagnetic bandgap (EBG) is proposed to suppress simultaneous switching noise (SSN) with good transmission performance. Different from the common microstrip lines, in which the conductor line is uniform and EBG is etched on the ground plane to suppress SSN, the proposed microstrip transmission line applies EBG structure to conductor line instead of ground plane. The simulation results show that the novel microstrip line can exhibit better noise suppression performance than common microstrip line with EBG structure etched on ground plane.
{"title":"A novel EBG microstrip line with noise suppression","authors":"Xiang-ting Wang, Xiaochun Li, J. Mao","doi":"10.1109/EDAPS.2017.8276916","DOIUrl":"https://doi.org/10.1109/EDAPS.2017.8276916","url":null,"abstract":"In this paper, a novel microstrip transmission line structure based on the electromagnetic bandgap (EBG) is proposed to suppress simultaneous switching noise (SSN) with good transmission performance. Different from the common microstrip lines, in which the conductor line is uniform and EBG is etched on the ground plane to suppress SSN, the proposed microstrip transmission line applies EBG structure to conductor line instead of ground plane. The simulation results show that the novel microstrip line can exhibit better noise suppression performance than common microstrip line with EBG structure etched on ground plane.","PeriodicalId":329279,"journal":{"name":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123140762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EDAPS.2017.8276996
Xin Chen, Q. Tang, M. Tong
In this paper, a new algorithm for the generation of the approximate poles and residues of multiconductor transmission lines characterized by frequency-dependent per-unit-length parameters is presented. Based on the Green's function-based delay-rational model for lossy transmission lines, which performs a reduced number of rational functions for the open-end impedance matrix, the proposed algorithm is more efficient by performing the poles and residues approximation comparing with solving high order equation. And the frequency response and transient analysis results have been considered when compared to the delay-rational model calculated. The results show that the proposed method can achieve an over seventy percent speed-up while keeping a good accuracy.
{"title":"An efficient approximation method for delay-rational model of multiconductor transmission line","authors":"Xin Chen, Q. Tang, M. Tong","doi":"10.1109/EDAPS.2017.8276996","DOIUrl":"https://doi.org/10.1109/EDAPS.2017.8276996","url":null,"abstract":"In this paper, a new algorithm for the generation of the approximate poles and residues of multiconductor transmission lines characterized by frequency-dependent per-unit-length parameters is presented. Based on the Green's function-based delay-rational model for lossy transmission lines, which performs a reduced number of rational functions for the open-end impedance matrix, the proposed algorithm is more efficient by performing the poles and residues approximation comparing with solving high order equation. And the frequency response and transient analysis results have been considered when compared to the delay-rational model calculated. The results show that the proposed method can achieve an over seventy percent speed-up while keeping a good accuracy.","PeriodicalId":329279,"journal":{"name":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129132558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EDAPS.2017.8276911
Wei Wu, Hong-li Peng, J. Mao
A new compact dual polarized co-axial antenna with gain greater than 8.0dBi is presented operated in 0.69GHz–0.96GHz/1.71GHz–2.69GHz. The size of the antenna is 286 × 286 × 81mm3. Its reflection coefficient and the cross-polarization isolation are less than −10.5dB (−12dB) and higher than 15dB (20dB) in low (high) frequency respectively. Measured results are agree well with the simulated one, verifying the availability of this antenna design.
{"title":"A new compact dual-polarized co-axial full-band antenna for 2G/3G/LTE base station applications","authors":"Wei Wu, Hong-li Peng, J. Mao","doi":"10.1109/EDAPS.2017.8276911","DOIUrl":"https://doi.org/10.1109/EDAPS.2017.8276911","url":null,"abstract":"A new compact dual polarized co-axial antenna with gain greater than 8.0dBi is presented operated in 0.69GHz–0.96GHz/1.71GHz–2.69GHz. The size of the antenna is 286 × 286 × 81mm<sup>3</sup>. Its reflection coefficient and the cross-polarization isolation are less than −10.5dB (−12dB) and higher than 15dB (20dB) in low (high) frequency respectively. Measured results are agree well with the simulated one, verifying the availability of this antenna design.","PeriodicalId":329279,"journal":{"name":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120948009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EDAPS.2017.8277050
B. Wu
In this paper, we describe the architecture and performance of a fine pitch multi-chip heterogeneous integration solution using embedded ceramic interconnect bridge (ECIB) in organic substrate package. We present the increased IO density and the improvement of electrical high-speed performance on signal integrity are achievable through this novel integration scheme, where small ceramic elements are embedded and served as interconnect bridges in organic substrate.
{"title":"Embedded ceramic interconnect bridge in organic substrate for heterogeneous integration and multi-chip packaging","authors":"B. Wu","doi":"10.1109/EDAPS.2017.8277050","DOIUrl":"https://doi.org/10.1109/EDAPS.2017.8277050","url":null,"abstract":"In this paper, we describe the architecture and performance of a fine pitch multi-chip heterogeneous integration solution using embedded ceramic interconnect bridge (ECIB) in organic substrate package. We present the increased IO density and the improvement of electrical high-speed performance on signal integrity are achievable through this novel integration scheme, where small ceramic elements are embedded and served as interconnect bridges in organic substrate.","PeriodicalId":329279,"journal":{"name":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117345216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EDAPS.2017.8276967
Hang Jin, Le Zhang, Hanzhi Ma, Sichen Yang, Xiao-Li Yang, E. Li
The electromagnetic interference (EMI) problem of extra-high speed electronic devices and systems is becoming more complex with an increase of operating frequency. The conventional analysis and design methods could not cope with the current EMI problems. Advanced analysis and design methods are desired. Deep neural network (DNN) and Bayesian optimization algorithm (BOA) based on machine learning are utilized in prediction of EMI radiation, optimization of design parameters and localization of EMI sources. The feasibility of DNN and BOA is investigated and validated. The steps of using DNN and BOA are proposed in the paper.
{"title":"Machine learning for complex EMI prediction, optimization and localization","authors":"Hang Jin, Le Zhang, Hanzhi Ma, Sichen Yang, Xiao-Li Yang, E. Li","doi":"10.1109/EDAPS.2017.8276967","DOIUrl":"https://doi.org/10.1109/EDAPS.2017.8276967","url":null,"abstract":"The electromagnetic interference (EMI) problem of extra-high speed electronic devices and systems is becoming more complex with an increase of operating frequency. The conventional analysis and design methods could not cope with the current EMI problems. Advanced analysis and design methods are desired. Deep neural network (DNN) and Bayesian optimization algorithm (BOA) based on machine learning are utilized in prediction of EMI radiation, optimization of design parameters and localization of EMI sources. The feasibility of DNN and BOA is investigated and validated. The steps of using DNN and BOA are proposed in the paper.","PeriodicalId":329279,"journal":{"name":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115138593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EDAPS.2017.8276929
Yujie Hua, Cheng-rui Zhang, Liang Zhou, J. Mao
This paper demonstrated the design methodology of 3 dimensional wafer level integrations of slow wave coupled oscillators. The Q factors have been calculated, compared and improved with the transmission line resonators. In order to minimize the size of the oscillator, we used multilayer BCB to integrate the GaAs FET low noise amplifier and slow wave resonators. Finally the phase noise of the packaged oscillator has been calculated.
{"title":"Design of 3-dimensional wafer level integrations of slow-wave coupled oscillators","authors":"Yujie Hua, Cheng-rui Zhang, Liang Zhou, J. Mao","doi":"10.1109/EDAPS.2017.8276929","DOIUrl":"https://doi.org/10.1109/EDAPS.2017.8276929","url":null,"abstract":"This paper demonstrated the design methodology of 3 dimensional wafer level integrations of slow wave coupled oscillators. The Q factors have been calculated, compared and improved with the transmission line resonators. In order to minimize the size of the oscillator, we used multilayer BCB to integrate the GaAs FET low noise amplifier and slow wave resonators. Finally the phase noise of the packaged oscillator has been calculated.","PeriodicalId":329279,"journal":{"name":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116568541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EDAPS.2017.8276965
Qijun Lu, Zhangming Zhu, Yintang Yang, Xiangkun Yin, Xiaoxian Liu, Chenbing Qu, Yang Liu
A simple formula for the internal impedance of mixed carbon nanotube (CNT) bundles is proposed in this paper. It can appropriately capture the skin effect as well as temperature effect of mixed CNT bundles. The computing time and results of the simple formula and the numerical calculation are compared with various mean diameters, standard deviations, and temperatures. It is shown that the proposed simple formula can improve the efficiency dramatically, and has very high accuracy in the whole frequency range considered, with maximum errors of 1.2% and 2.5% for the resistance and the internal inductance, respectively.
{"title":"Simple formula for the internal impedance of mixed carbon nanotube bundles","authors":"Qijun Lu, Zhangming Zhu, Yintang Yang, Xiangkun Yin, Xiaoxian Liu, Chenbing Qu, Yang Liu","doi":"10.1109/EDAPS.2017.8276965","DOIUrl":"https://doi.org/10.1109/EDAPS.2017.8276965","url":null,"abstract":"A simple formula for the internal impedance of mixed carbon nanotube (CNT) bundles is proposed in this paper. It can appropriately capture the skin effect as well as temperature effect of mixed CNT bundles. The computing time and results of the simple formula and the numerical calculation are compared with various mean diameters, standard deviations, and temperatures. It is shown that the proposed simple formula can improve the efficiency dramatically, and has very high accuracy in the whole frequency range considered, with maximum errors of 1.2% and 2.5% for the resistance and the internal inductance, respectively.","PeriodicalId":329279,"journal":{"name":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116606967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EDAPS.2017.8277040
Tae-Young Choi, Soyoung Kim
In latest laptop computers, the Wi-Fi performance has been degraded significantly due to the radio frequency interference (RFI) in 2.4-GHz ISM band caused by DDR4 memory. In order to solve this problem, a shielding can that is specifically designed for DDR4 connector interface is proposed in this work. We propose to add shielding finger structure to the ground contact of the long slot in the shielding can to improve the shielding effectiveness without increasing the number of ground contacts. 3D full-wave simulation is performed, and a test structure was fabricated and measured to prove the reduction in RFI. 8-dB reduction in the noise level is achieved by using the shielding finger structures proposed in this work.
{"title":"Shielding can design for a DDR4 connector system to reduce RFI","authors":"Tae-Young Choi, Soyoung Kim","doi":"10.1109/EDAPS.2017.8277040","DOIUrl":"https://doi.org/10.1109/EDAPS.2017.8277040","url":null,"abstract":"In latest laptop computers, the Wi-Fi performance has been degraded significantly due to the radio frequency interference (RFI) in 2.4-GHz ISM band caused by DDR4 memory. In order to solve this problem, a shielding can that is specifically designed for DDR4 connector interface is proposed in this work. We propose to add shielding finger structure to the ground contact of the long slot in the shielding can to improve the shielding effectiveness without increasing the number of ground contacts. 3D full-wave simulation is performed, and a test structure was fabricated and measured to prove the reduction in RFI. 8-dB reduction in the noise level is achieved by using the shielding finger structures proposed in this work.","PeriodicalId":329279,"journal":{"name":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122060443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EDAPS.2017.8276946
Masaki Kanemoto, M. Aoki, A. Mochizuki, Y. Murakami, M. Tsunoda, Goro Yoshinari, N. Nakano
This work clarifies the thermal stress profiles and concentrations under thermal cycling test by 3D multi-physics solver for SiC and Si power device chip systems using Ag sintering chip-attachment on Cu plate. A comparison analysis between SiC and Si showed that the maximum stress value in SiC structure is higher than that in Si structure for both Ag sintering and conventional solder chip-attachments due to larger Young's modulus of SiC. The thickness of Ag sintered layer is five times thinner than conventional solder, and this slightly increases the stress in Ag sintered layer for SiC structures with the Cu plate thickness below 3 mm. To reveal the physical mechanism of thermal stress the stress directions are also clarified. It was found that the normal stress is the major component of von Mises stress at the corners of Ag sintered layer, and both SiC and Si chips.
{"title":"Comparison of thermal stress under TCT between SiC and Si power devices using direct chip-bonding with ag sintered layer on Cu plate","authors":"Masaki Kanemoto, M. Aoki, A. Mochizuki, Y. Murakami, M. Tsunoda, Goro Yoshinari, N. Nakano","doi":"10.1109/EDAPS.2017.8276946","DOIUrl":"https://doi.org/10.1109/EDAPS.2017.8276946","url":null,"abstract":"This work clarifies the thermal stress profiles and concentrations under thermal cycling test by 3D multi-physics solver for SiC and Si power device chip systems using Ag sintering chip-attachment on Cu plate. A comparison analysis between SiC and Si showed that the maximum stress value in SiC structure is higher than that in Si structure for both Ag sintering and conventional solder chip-attachments due to larger Young's modulus of SiC. The thickness of Ag sintered layer is five times thinner than conventional solder, and this slightly increases the stress in Ag sintered layer for SiC structures with the Cu plate thickness below 3 mm. To reveal the physical mechanism of thermal stress the stress directions are also clarified. It was found that the normal stress is the major component of von Mises stress at the corners of Ag sintered layer, and both SiC and Si chips.","PeriodicalId":329279,"journal":{"name":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122393221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EDAPS.2017.8277039
Qiwei Zhan, Rui Zhang, James Baker, H. Hansen, Q. Liu
Foaming the expanded polyethylene (PE) is a prevailing way to lower the dielectric constants and dissipation factors of insulators in modern communication high-speed cables. The porosity and elongated cell shapes impose significant effects on the dielectric properties of PE. However, a theoretical study is lacking. This work proposes an effective way to predict the dielectric parameters of foamed PE. Unlike directly generating the extremely dense meshes for the randomly distributed pores, which is usually computationally intractable, we apply an electrodynamics homogenization method to obtain the equivalent anisotropic model for the complex foamed insulators. It is shown that the predicted values are amenable to the experimentally measured data.
{"title":"Mapping the foam-induced dielectric anisotropy for high-speed cables","authors":"Qiwei Zhan, Rui Zhang, James Baker, H. Hansen, Q. Liu","doi":"10.1109/EDAPS.2017.8277039","DOIUrl":"https://doi.org/10.1109/EDAPS.2017.8277039","url":null,"abstract":"Foaming the expanded polyethylene (PE) is a prevailing way to lower the dielectric constants and dissipation factors of insulators in modern communication high-speed cables. The porosity and elongated cell shapes impose significant effects on the dielectric properties of PE. However, a theoretical study is lacking. This work proposes an effective way to predict the dielectric parameters of foamed PE. Unlike directly generating the extremely dense meshes for the randomly distributed pores, which is usually computationally intractable, we apply an electrodynamics homogenization method to obtain the equivalent anisotropic model for the complex foamed insulators. It is shown that the predicted values are amenable to the experimentally measured data.","PeriodicalId":329279,"journal":{"name":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128768127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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