Pub Date : 2017-12-01DOI: 10.1109/EDAPS.2017.8277012
Qixuan Sun, S. Bai, J. Drewniak, E. Li
A low impedance power distribution network (PDN) is essential for the functionality of high speed printed circuit boards. A pre-layout impedance calculation can avoid time consuming changes on the design during post-layout stage. Design curves for inductance estimation are convenient to use in pre-layout stage. However, the high density voids on the power plane, which is caused by the anti-pads, are not considered in those design curves. This short paper discussed the extra inductance caused by the anti-pads, in two common situations.
{"title":"The influence of anti-pad array on the inductance of PCB power net area fill","authors":"Qixuan Sun, S. Bai, J. Drewniak, E. Li","doi":"10.1109/EDAPS.2017.8277012","DOIUrl":"https://doi.org/10.1109/EDAPS.2017.8277012","url":null,"abstract":"A low impedance power distribution network (PDN) is essential for the functionality of high speed printed circuit boards. A pre-layout impedance calculation can avoid time consuming changes on the design during post-layout stage. Design curves for inductance estimation are convenient to use in pre-layout stage. However, the high density voids on the power plane, which is caused by the anti-pads, are not considered in those design curves. This short paper discussed the extra inductance caused by the anti-pads, in two common situations.","PeriodicalId":329279,"journal":{"name":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114508073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EDAPS.2017.8276967
Hang Jin, Le Zhang, Hanzhi Ma, Sichen Yang, Xiao-Li Yang, E. Li
The electromagnetic interference (EMI) problem of extra-high speed electronic devices and systems is becoming more complex with an increase of operating frequency. The conventional analysis and design methods could not cope with the current EMI problems. Advanced analysis and design methods are desired. Deep neural network (DNN) and Bayesian optimization algorithm (BOA) based on machine learning are utilized in prediction of EMI radiation, optimization of design parameters and localization of EMI sources. The feasibility of DNN and BOA is investigated and validated. The steps of using DNN and BOA are proposed in the paper.
{"title":"Machine learning for complex EMI prediction, optimization and localization","authors":"Hang Jin, Le Zhang, Hanzhi Ma, Sichen Yang, Xiao-Li Yang, E. Li","doi":"10.1109/EDAPS.2017.8276967","DOIUrl":"https://doi.org/10.1109/EDAPS.2017.8276967","url":null,"abstract":"The electromagnetic interference (EMI) problem of extra-high speed electronic devices and systems is becoming more complex with an increase of operating frequency. The conventional analysis and design methods could not cope with the current EMI problems. Advanced analysis and design methods are desired. Deep neural network (DNN) and Bayesian optimization algorithm (BOA) based on machine learning are utilized in prediction of EMI radiation, optimization of design parameters and localization of EMI sources. The feasibility of DNN and BOA is investigated and validated. The steps of using DNN and BOA are proposed in the paper.","PeriodicalId":329279,"journal":{"name":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115138593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EDAPS.2017.8276916
Xiang-ting Wang, Xiaochun Li, J. Mao
In this paper, a novel microstrip transmission line structure based on the electromagnetic bandgap (EBG) is proposed to suppress simultaneous switching noise (SSN) with good transmission performance. Different from the common microstrip lines, in which the conductor line is uniform and EBG is etched on the ground plane to suppress SSN, the proposed microstrip transmission line applies EBG structure to conductor line instead of ground plane. The simulation results show that the novel microstrip line can exhibit better noise suppression performance than common microstrip line with EBG structure etched on ground plane.
{"title":"A novel EBG microstrip line with noise suppression","authors":"Xiang-ting Wang, Xiaochun Li, J. Mao","doi":"10.1109/EDAPS.2017.8276916","DOIUrl":"https://doi.org/10.1109/EDAPS.2017.8276916","url":null,"abstract":"In this paper, a novel microstrip transmission line structure based on the electromagnetic bandgap (EBG) is proposed to suppress simultaneous switching noise (SSN) with good transmission performance. Different from the common microstrip lines, in which the conductor line is uniform and EBG is etched on the ground plane to suppress SSN, the proposed microstrip transmission line applies EBG structure to conductor line instead of ground plane. The simulation results show that the novel microstrip line can exhibit better noise suppression performance than common microstrip line with EBG structure etched on ground plane.","PeriodicalId":329279,"journal":{"name":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123140762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EDAPS.2017.8277040
Tae-Young Choi, Soyoung Kim
In latest laptop computers, the Wi-Fi performance has been degraded significantly due to the radio frequency interference (RFI) in 2.4-GHz ISM band caused by DDR4 memory. In order to solve this problem, a shielding can that is specifically designed for DDR4 connector interface is proposed in this work. We propose to add shielding finger structure to the ground contact of the long slot in the shielding can to improve the shielding effectiveness without increasing the number of ground contacts. 3D full-wave simulation is performed, and a test structure was fabricated and measured to prove the reduction in RFI. 8-dB reduction in the noise level is achieved by using the shielding finger structures proposed in this work.
{"title":"Shielding can design for a DDR4 connector system to reduce RFI","authors":"Tae-Young Choi, Soyoung Kim","doi":"10.1109/EDAPS.2017.8277040","DOIUrl":"https://doi.org/10.1109/EDAPS.2017.8277040","url":null,"abstract":"In latest laptop computers, the Wi-Fi performance has been degraded significantly due to the radio frequency interference (RFI) in 2.4-GHz ISM band caused by DDR4 memory. In order to solve this problem, a shielding can that is specifically designed for DDR4 connector interface is proposed in this work. We propose to add shielding finger structure to the ground contact of the long slot in the shielding can to improve the shielding effectiveness without increasing the number of ground contacts. 3D full-wave simulation is performed, and a test structure was fabricated and measured to prove the reduction in RFI. 8-dB reduction in the noise level is achieved by using the shielding finger structures proposed in this work.","PeriodicalId":329279,"journal":{"name":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122060443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EDAPS.2017.8277055
Pengfei Sun, Tang Liu, Jian Zhang, Linpu Huang
This paper presents an integration of a 60 GHz packaged low-temperature cofired ceramic (LTCC) grid array antenna (GAA) with a power amplifier under the concept of antenna-in-package. The demonstrated single GAA has a measured maximum gain of 15.12dB at 60GHz, with an accepted impedance bandwidth from 58 to 61 GHz and ±15° half-power beam width (HPBW). Vertical vias and wire-bonding are used to realize low-loss interconnection between the amplifier and the GAA. The measured results indicate that the maximum gain is 26.4dB when the packaged GAA is working as the transmitter, and the maximum gain is 25.69dB when the packaged GAA is working as the receiver, which is 11.28dB and 10.57dB respectively higher than the single GAA. These results clearly demonstrate the feasibility and potential of the solution for the 60 GHz front-end integration and package.
{"title":"Integration of a 60 GHz packaged LTCC grid array antenna with an amplifier","authors":"Pengfei Sun, Tang Liu, Jian Zhang, Linpu Huang","doi":"10.1109/EDAPS.2017.8277055","DOIUrl":"https://doi.org/10.1109/EDAPS.2017.8277055","url":null,"abstract":"This paper presents an integration of a 60 GHz packaged low-temperature cofired ceramic (LTCC) grid array antenna (GAA) with a power amplifier under the concept of antenna-in-package. The demonstrated single GAA has a measured maximum gain of 15.12dB at 60GHz, with an accepted impedance bandwidth from 58 to 61 GHz and ±15° half-power beam width (HPBW). Vertical vias and wire-bonding are used to realize low-loss interconnection between the amplifier and the GAA. The measured results indicate that the maximum gain is 26.4dB when the packaged GAA is working as the transmitter, and the maximum gain is 25.69dB when the packaged GAA is working as the receiver, which is 11.28dB and 10.57dB respectively higher than the single GAA. These results clearly demonstrate the feasibility and potential of the solution for the 60 GHz front-end integration and package.","PeriodicalId":329279,"journal":{"name":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129533244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EDAPS.2017.8276988
Wenbo Shi, Kaixue Ma, Shouxian Mou, F. Meng
This paper presents a compact 14–18 GHz 6-bit attenuator in 0.35-μm SiGe BiCMOS technology. To realize size miniaturization, large attenuation range and low insertion loss, the switched Pi/T attenuator topology is employed. It adopts serial and shunt single-pole-single-throw switches merged with a resistive network to control attenuation accurately. In addition, the proposed attenuators use a novel inductive low-pass filter for phase correction to compensate the phase error in difference states. The designed prototype achieves an attenuation range of 31.5 dB in a 0.5-dB step size with 64 states, average insertion loss of 8±0.6 dB, P1dB of better than 10 dBm, input/output return losses of better than −10/-11 dB in all states, and chip size of 0.80×0.34 mm2 only excluding testing pads. The calculated root-mean-square (rms) amplitude error is less than 0.29 dB, with rms phase error is less than 3.9o in the designed frequency range.
{"title":"A compact ku-band 6-bit attenuator in 0.35um SiGe BiCMOS technology","authors":"Wenbo Shi, Kaixue Ma, Shouxian Mou, F. Meng","doi":"10.1109/EDAPS.2017.8276988","DOIUrl":"https://doi.org/10.1109/EDAPS.2017.8276988","url":null,"abstract":"This paper presents a compact 14–18 GHz 6-bit attenuator in 0.35-μm SiGe BiCMOS technology. To realize size miniaturization, large attenuation range and low insertion loss, the switched Pi/T attenuator topology is employed. It adopts serial and shunt single-pole-single-throw switches merged with a resistive network to control attenuation accurately. In addition, the proposed attenuators use a novel inductive low-pass filter for phase correction to compensate the phase error in difference states. The designed prototype achieves an attenuation range of 31.5 dB in a 0.5-dB step size with 64 states, average insertion loss of 8±0.6 dB, P1dB of better than 10 dBm, input/output return losses of better than −10/-11 dB in all states, and chip size of 0.80×0.34 mm2 only excluding testing pads. The calculated root-mean-square (rms) amplitude error is less than 0.29 dB, with rms phase error is less than 3.9o in the designed frequency range.","PeriodicalId":329279,"journal":{"name":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128559349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EDAPS.2017.8276920
Xiang Chen, Liang Zhou, J. Mao, W. Yin
This study demonstrates comparisons of power to failure for SiGe based low noise amplifiers under the injection of high-power microwave (HPM) pulses. A general equation was derived to calculate power to failure. The pulse thermal resistance and breakdown temperature are calculated and determined. It is found that although these two transistors have close structure, their power to failure depend on the number of slots, pulse thermal resistance, thermal capacitance and breakdown temperature. Calculated and measured results show close correlations.
{"title":"Comparisons of power to failure for low-noise amplifiers under high-power microwave pulses","authors":"Xiang Chen, Liang Zhou, J. Mao, W. Yin","doi":"10.1109/EDAPS.2017.8276920","DOIUrl":"https://doi.org/10.1109/EDAPS.2017.8276920","url":null,"abstract":"This study demonstrates comparisons of power to failure for SiGe based low noise amplifiers under the injection of high-power microwave (HPM) pulses. A general equation was derived to calculate power to failure. The pulse thermal resistance and breakdown temperature are calculated and determined. It is found that although these two transistors have close structure, their power to failure depend on the number of slots, pulse thermal resistance, thermal capacitance and breakdown temperature. Calculated and measured results show close correlations.","PeriodicalId":329279,"journal":{"name":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128723089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EDAPS.2017.8277038
Yi-Xiao Shi, Zhenzhen Jiang, S. Lam, M. Leach, Jingchen Wang, E. Lim
This paper reports experimental work on 50 Ω microstrip transmission lines implemented by screen-printing low-cost silver paste onto thin flexible polyethylene terephthalate (PET) substrates of varying thickness. The microstrip line designs are based on PET substrates with thicknesses of 1.4 mm, 0.7 mm and 0.5 mm, leading to conductive track widths of 3.8 mm, 1.7 mm and 1.2 mm respectively for a 50 Ω line; these designs were then realised. The S-parameter measurements show that the insertion loss of the microstrip transmission lines on each substrate can be as low as 0.2 dB/cm, 0.17 dB/cm, and 0.14 dB/cm up to a frequency of 5 GHz in spite of the average quality of the silver paste used. The experimental results also show that the screen-printed transmission lines still work quite well in bent condition and wearable electronics application at GHz is possible.
本文报道了50条Ω微带传输线的实验工作，该微带传输线是通过丝网印刷低成本的银浆在不同厚度的柔性聚乙烯对苯二甲酸乙二醇酯(PET)衬底上实现的。微带线设计基于厚度为1.4 mm, 0.7 mm和0.5 mm的PET衬底，导致50 Ω线的导电轨道宽度分别为3.8 mm, 1.7 mm和1.2 mm;这些设计后来实现了。s参数测量结果表明，在5 GHz频率下，无论所用银浆的平均质量如何，每块衬底上微带传输线的插入损耗均可低至0.2 dB/cm、0.17 dB/cm和0.14 dB/cm。实验结果还表明，丝网印刷的传输线在弯曲条件下仍然可以很好地工作，并且可以在GHz下应用于可穿戴电子设备。
{"title":"Multi-GHz microstrip transmission lines realised by screen printing on flexible substrates","authors":"Yi-Xiao Shi, Zhenzhen Jiang, S. Lam, M. Leach, Jingchen Wang, E. Lim","doi":"10.1109/EDAPS.2017.8277038","DOIUrl":"https://doi.org/10.1109/EDAPS.2017.8277038","url":null,"abstract":"This paper reports experimental work on 50 Ω microstrip transmission lines implemented by screen-printing low-cost silver paste onto thin flexible polyethylene terephthalate (PET) substrates of varying thickness. The microstrip line designs are based on PET substrates with thicknesses of 1.4 mm, 0.7 mm and 0.5 mm, leading to conductive track widths of 3.8 mm, 1.7 mm and 1.2 mm respectively for a 50 Ω line; these designs were then realised. The S-parameter measurements show that the insertion loss of the microstrip transmission lines on each substrate can be as low as 0.2 dB/cm, 0.17 dB/cm, and 0.14 dB/cm up to a frequency of 5 GHz in spite of the average quality of the silver paste used. The experimental results also show that the screen-printed transmission lines still work quite well in bent condition and wearable electronics application at GHz is possible.","PeriodicalId":329279,"journal":{"name":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127696999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EDAPS.2017.8277053
Shulin Liu, Dandan Xu
Aim to the existing shortages of fault monitoring technology in power grid, this paper presents a kind of self-powered short-circuit fault detection system based on current transformer (CT) to acquire power and GSM module to realize fault wireless remote alarming. The system utilizes the energy generated at the moment of short-circuit fault in grid, Combing the switching power supply technology, CT couples short-circuit energy to the secondary-side to supply power for the entire system, it can achieve zero power consumption; The ultra low power microprocessor controls the GSM wireless communication module to send fault signal to the monitoring terminal; super capacitor (SC) as the uninterrupted power supply, when the fault signal is to be sent, the stored energy is released instantaneously. The system eliminates the dependence on the dry battery and display screen, short-circuit fault information can be obtained in a distance of thousands of miles in time. At last, experiment results verify that the designed system can detect short-circuit fault quickly and effectively.
{"title":"Research on self-powered short-circuit fault alarming system in power grid","authors":"Shulin Liu, Dandan Xu","doi":"10.1109/EDAPS.2017.8277053","DOIUrl":"https://doi.org/10.1109/EDAPS.2017.8277053","url":null,"abstract":"Aim to the existing shortages of fault monitoring technology in power grid, this paper presents a kind of self-powered short-circuit fault detection system based on current transformer (CT) to acquire power and GSM module to realize fault wireless remote alarming. The system utilizes the energy generated at the moment of short-circuit fault in grid, Combing the switching power supply technology, CT couples short-circuit energy to the secondary-side to supply power for the entire system, it can achieve zero power consumption; The ultra low power microprocessor controls the GSM wireless communication module to send fault signal to the monitoring terminal; super capacitor (SC) as the uninterrupted power supply, when the fault signal is to be sent, the stored energy is released instantaneously. The system eliminates the dependence on the dry battery and display screen, short-circuit fault information can be obtained in a distance of thousands of miles in time. At last, experiment results verify that the designed system can detect short-circuit fault quickly and effectively.","PeriodicalId":329279,"journal":{"name":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122150895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EDAPS.2017.8276946
Masaki Kanemoto, M. Aoki, A. Mochizuki, Y. Murakami, M. Tsunoda, Goro Yoshinari, N. Nakano
This work clarifies the thermal stress profiles and concentrations under thermal cycling test by 3D multi-physics solver for SiC and Si power device chip systems using Ag sintering chip-attachment on Cu plate. A comparison analysis between SiC and Si showed that the maximum stress value in SiC structure is higher than that in Si structure for both Ag sintering and conventional solder chip-attachments due to larger Young's modulus of SiC. The thickness of Ag sintered layer is five times thinner than conventional solder, and this slightly increases the stress in Ag sintered layer for SiC structures with the Cu plate thickness below 3 mm. To reveal the physical mechanism of thermal stress the stress directions are also clarified. It was found that the normal stress is the major component of von Mises stress at the corners of Ag sintered layer, and both SiC and Si chips.
{"title":"Comparison of thermal stress under TCT between SiC and Si power devices using direct chip-bonding with ag sintered layer on Cu plate","authors":"Masaki Kanemoto, M. Aoki, A. Mochizuki, Y. Murakami, M. Tsunoda, Goro Yoshinari, N. Nakano","doi":"10.1109/EDAPS.2017.8276946","DOIUrl":"https://doi.org/10.1109/EDAPS.2017.8276946","url":null,"abstract":"This work clarifies the thermal stress profiles and concentrations under thermal cycling test by 3D multi-physics solver for SiC and Si power device chip systems using Ag sintering chip-attachment on Cu plate. A comparison analysis between SiC and Si showed that the maximum stress value in SiC structure is higher than that in Si structure for both Ag sintering and conventional solder chip-attachments due to larger Young's modulus of SiC. The thickness of Ag sintered layer is five times thinner than conventional solder, and this slightly increases the stress in Ag sintered layer for SiC structures with the Cu plate thickness below 3 mm. To reveal the physical mechanism of thermal stress the stress directions are also clarified. It was found that the normal stress is the major component of von Mises stress at the corners of Ag sintered layer, and both SiC and Si chips.","PeriodicalId":329279,"journal":{"name":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122393221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：