Pub Date : 2017-12-01DOI: 10.1109/EDAPS.2017.8276977
Kai Fu, Jin-Wei Pan, Jing Jin, Wensheng Zhao, Gaofeng Wang
Through-silicon via (TSV)-to-TSV coupling is a critical challenge of 3-D ICs, and, it is quite different from the coupling issues of on-chip interconnects. In this paper, the traditional TSV-to-TSV coupling model is restated and modified. The current return path, i.e., ground TSV, is considered. Then, the impacts of circuit elements on the coupling coefficient are analyzed based on the circuit model.
{"title":"The impact of current return path on the signal propagation in the through-silicon via array","authors":"Kai Fu, Jin-Wei Pan, Jing Jin, Wensheng Zhao, Gaofeng Wang","doi":"10.1109/EDAPS.2017.8276977","DOIUrl":"https://doi.org/10.1109/EDAPS.2017.8276977","url":null,"abstract":"Through-silicon via (TSV)-to-TSV coupling is a critical challenge of 3-D ICs, and, it is quite different from the coupling issues of on-chip interconnects. In this paper, the traditional TSV-to-TSV coupling model is restated and modified. The current return path, i.e., ground TSV, is considered. Then, the impacts of circuit elements on the coupling coefficient are analyzed based on the circuit model.","PeriodicalId":329279,"journal":{"name":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121308572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EDAPS.2017.8276974
Tuomin Tao, Hanzhi Ma, Chenxi Huang, Y. S. Cao, J. Drewniak, E. Li
Dog-bone structure has been widely used in package PDN, yet it has not been thoroughly investigated. In this paper, the associated inductance for the dog-bone structure is studied with the partial element equivalent circuit (PEEC) method and CST. PEEC method is based on the electrical field integral equation (EFIE) and it serves as a bridge between electromagnetic problems and circuit ones. In this paper, the detailed geometry of the dog-bone structure in packages is discussed, the geometrical features of the inductance associated with the dog-bone structure are described. Besides, this paper also compares the inductance of the dog-bone structure with and without ground planes, which illustrates the effectiveness of the plane size to the total inductance of the dog-bone structure.
{"title":"'Dog-bone' geometry modeling based on PEEC for package PDN","authors":"Tuomin Tao, Hanzhi Ma, Chenxi Huang, Y. S. Cao, J. Drewniak, E. Li","doi":"10.1109/EDAPS.2017.8276974","DOIUrl":"https://doi.org/10.1109/EDAPS.2017.8276974","url":null,"abstract":"Dog-bone structure has been widely used in package PDN, yet it has not been thoroughly investigated. In this paper, the associated inductance for the dog-bone structure is studied with the partial element equivalent circuit (PEEC) method and CST. PEEC method is based on the electrical field integral equation (EFIE) and it serves as a bridge between electromagnetic problems and circuit ones. In this paper, the detailed geometry of the dog-bone structure in packages is discussed, the geometrical features of the inductance associated with the dog-bone structure are described. Besides, this paper also compares the inductance of the dog-bone structure with and without ground planes, which illustrates the effectiveness of the plane size to the total inductance of the dog-bone structure.","PeriodicalId":329279,"journal":{"name":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125273622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EDAPS.2017.8276986
ZhengLe Fan, Kaixue Ma, Shouxian Mou, F. Meng
In this paper, a compact high-isolation Ku-band SPDT switch using triple-well transistors based on 0.35μm SiGe BiCMOS process is proposed. Improved series-shunt-shunt topology is used in this design to enhance the isolation and to reduce the insertion loss simultaneously. In order to improve the power handling capability, body-floating transistor is employed and analyzed. The full-wave simulated results show that the insertion loss of the ON state path is better than 1.76 dB, and the isolation of the OFF state path is higher than 40.8 dB in the entire designed frequency band of 14–18 GHz. The output P1dB of the ON state path at center frequency 16 GHz is 10.51dBm, and the core area of this SPDT is only 0.36×0.41 mm2 excluding testing pads.
{"title":"A high-isolation ku-band SPDT switch in 0.35μm SiGe BiCMOS technology","authors":"ZhengLe Fan, Kaixue Ma, Shouxian Mou, F. Meng","doi":"10.1109/EDAPS.2017.8276986","DOIUrl":"https://doi.org/10.1109/EDAPS.2017.8276986","url":null,"abstract":"In this paper, a compact high-isolation Ku-band SPDT switch using triple-well transistors based on 0.35μm SiGe BiCMOS process is proposed. Improved series-shunt-shunt topology is used in this design to enhance the isolation and to reduce the insertion loss simultaneously. In order to improve the power handling capability, body-floating transistor is employed and analyzed. The full-wave simulated results show that the insertion loss of the ON state path is better than 1.76 dB, and the isolation of the OFF state path is higher than 40.8 dB in the entire designed frequency band of 14–18 GHz. The output P1dB of the ON state path at center frequency 16 GHz is 10.51dBm, and the core area of this SPDT is only 0.36×0.41 mm2 excluding testing pads.","PeriodicalId":329279,"journal":{"name":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122508933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EDAPS.2017.8277060
Zhijun Yang, Yangyang Sun
In view of the limited energy of nodes in wireless sensor networks, from the perspective of improving the work efficiency of the polling control system, this paper proposes a parallel busy limited polling wireless sensor network control protocol idle state. The mathematical modeling and analysis of the parallel limited polling system with busy state is carried out. The simulation results show the consistency and rationality of the theoretical analysis and the simulation experiment. The polling scheduling protocol for wireless sensor networks with busy state parallel scheduling mechanism provides a stable and reliable guarantee for wireless terminal with higher requirements for time delay QoS.
{"title":"Parallel restricted polling control for wireless sensor networks with busy state","authors":"Zhijun Yang, Yangyang Sun","doi":"10.1109/EDAPS.2017.8277060","DOIUrl":"https://doi.org/10.1109/EDAPS.2017.8277060","url":null,"abstract":"In view of the limited energy of nodes in wireless sensor networks, from the perspective of improving the work efficiency of the polling control system, this paper proposes a parallel busy limited polling wireless sensor network control protocol idle state. The mathematical modeling and analysis of the parallel limited polling system with busy state is carried out. The simulation results show the consistency and rationality of the theoretical analysis and the simulation experiment. The polling scheduling protocol for wireless sensor networks with busy state parallel scheduling mechanism provides a stable and reliable guarantee for wireless terminal with higher requirements for time delay QoS.","PeriodicalId":329279,"journal":{"name":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131560928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EDAPS.2017.8276906
Ning Wang, Zhiyong Liu, Hongzhi Jia
Thermoelectric cooler (TEC) and generator (TEG), as solid devices, are widely used in current thermal management design. In this paper, a TEC-TEG parallel connection collaborative cooling model based on energy harvesting mechanism is proposed to obtain enhanced TEC performance. Firstly, an equation determining electric current flowing through TEC is deduced to abstractly show that its value in collaborative cooling system is higher than typical Peltier cooling system. Then, a corresponding SPICE model with novel TEC-TEG parallel connection structure is proposed to analyze the cooling capacity of different type of TEC. Under the condition of a constant temperature of 300K in the hot side, simulation results show that the increment of current, temperature difference and conversion efficient can be kept in a certain voltage ranges, and the maximum increment of them are about 0.71A, 9.8C and 8.1%, which demonstrates the proposed model offers a feasible solution to improve the cooling capacity of TEC.
{"title":"Study of the electro-thermal collaborative cooling based on energy harvesting for thermoelectric coolers","authors":"Ning Wang, Zhiyong Liu, Hongzhi Jia","doi":"10.1109/EDAPS.2017.8276906","DOIUrl":"https://doi.org/10.1109/EDAPS.2017.8276906","url":null,"abstract":"Thermoelectric cooler (TEC) and generator (TEG), as solid devices, are widely used in current thermal management design. In this paper, a TEC-TEG parallel connection collaborative cooling model based on energy harvesting mechanism is proposed to obtain enhanced TEC performance. Firstly, an equation determining electric current flowing through TEC is deduced to abstractly show that its value in collaborative cooling system is higher than typical Peltier cooling system. Then, a corresponding SPICE model with novel TEC-TEG parallel connection structure is proposed to analyze the cooling capacity of different type of TEC. Under the condition of a constant temperature of 300K in the hot side, simulation results show that the increment of current, temperature difference and conversion efficient can be kept in a certain voltage ranges, and the maximum increment of them are about 0.71A, 9.8C and 8.1%, which demonstrates the proposed model offers a feasible solution to improve the cooling capacity of TEC.","PeriodicalId":329279,"journal":{"name":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128151377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EDAPS.2017.8276983
Wenchao Chen, Manxi Wang, Xiaofan Yang, W. Yin, Erping Li
Modeling and simulation of Si/PEDOT:PSS planar heterojunction solar cell is performed by using the finite element method to solve Poisson equation, drift-diffusion equations and current continuity equations. PEDOT:PSS is a hole-rich organic semiconductor, which can be treated as highly p-type doped semiconductor. While, the 2μm silicon thin film is n-type doped. The Si/PEDOT:PSS heterojunction behaves like a pn junction rather than a Schottky junction as clarified in previous study and the PEDOT : PSS is much highly doped, the hole diffusion current in Si is the dominant current component. The simulated J-V characteristics of the Si/PEDOT:PSS planar heterojunction are obtained and compared with experiments.
{"title":"Modeling and simulation of Si/PEDOT:PSS planar heterojunction photovoltaics by finite element method","authors":"Wenchao Chen, Manxi Wang, Xiaofan Yang, W. Yin, Erping Li","doi":"10.1109/EDAPS.2017.8276983","DOIUrl":"https://doi.org/10.1109/EDAPS.2017.8276983","url":null,"abstract":"Modeling and simulation of Si/PEDOT:PSS planar heterojunction solar cell is performed by using the finite element method to solve Poisson equation, drift-diffusion equations and current continuity equations. PEDOT:PSS is a hole-rich organic semiconductor, which can be treated as highly p-type doped semiconductor. While, the 2μm silicon thin film is n-type doped. The Si/PEDOT:PSS heterojunction behaves like a pn junction rather than a Schottky junction as clarified in previous study and the PEDOT : PSS is much highly doped, the hole diffusion current in Si is the dominant current component. The simulated J-V characteristics of the Si/PEDOT:PSS planar heterojunction are obtained and compared with experiments.","PeriodicalId":329279,"journal":{"name":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133672101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EDAPS.2017.8277061
J. Wu, Y. Li, Z. Gao, M. Wang
Accompanied with fast development of the high-speed board/package design, for the complex interconnection structure composed of via, solder ball and printing line has become a basic unit, designer are trying to eliminate or minimize all the impedance mismatches along the high-speed signal path. This paper addresses designing for crosstalk by comparing the crosstalk of near end and far end. The crosstalk can be minimized by optimizing a few parameters such as dielectric constant, current direction and spacing. The impacts of theses parameters are investigated with the help of a full-wave electromagnetic simulation. The results clearly show that the small changes in interconnection structure can affect the impedance mismatch significantly meanwhile degrade the signal propagation performance.
{"title":"The crosstalk analysis of package-PCB complex interconnect structure","authors":"J. Wu, Y. Li, Z. Gao, M. Wang","doi":"10.1109/EDAPS.2017.8277061","DOIUrl":"https://doi.org/10.1109/EDAPS.2017.8277061","url":null,"abstract":"Accompanied with fast development of the high-speed board/package design, for the complex interconnection structure composed of via, solder ball and printing line has become a basic unit, designer are trying to eliminate or minimize all the impedance mismatches along the high-speed signal path. This paper addresses designing for crosstalk by comparing the crosstalk of near end and far end. The crosstalk can be minimized by optimizing a few parameters such as dielectric constant, current direction and spacing. The impacts of theses parameters are investigated with the help of a full-wave electromagnetic simulation. The results clearly show that the small changes in interconnection structure can affect the impedance mismatch significantly meanwhile degrade the signal propagation performance.","PeriodicalId":329279,"journal":{"name":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133743624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EDAPS.2017.8276949
Shiquan Fan, Zhongming Xue, Zhuoqi Guo, W. Gou, Xu Yang, Li Geng
In this paper, we present an ultra-low power (ULP) zero-current-detector (ZCD) circuit by using sub-threshold design method and discontinued operating time to decrease power consumption, which can be widely used in switching inductor converters such as boost, buck or buck-boost converters. The designed ZCD circuit consumes only 40 nA quiescent current to realize nearly 70 dB DC gain and 650 kHz gain-bandwidth (GBW) when it operates. The main comparator of the ZCD circuit has high sensitivity and very low delay time to turn-off the synchronous switches of the DC-DC converter on time. The average quiescent current consumption is less than 1.6 nA because the operating time is only 40 μs under the minimum switching period of 1 ms. Finally, the designed ZCD circuit is used in a boost converter for vibrational energy harvesting applications.
{"title":"An ultra-low power (ULP) zero-current-detector (ZCD) circuit for switching inductor converter applied in energy harvesting system","authors":"Shiquan Fan, Zhongming Xue, Zhuoqi Guo, W. Gou, Xu Yang, Li Geng","doi":"10.1109/EDAPS.2017.8276949","DOIUrl":"https://doi.org/10.1109/EDAPS.2017.8276949","url":null,"abstract":"In this paper, we present an ultra-low power (ULP) zero-current-detector (ZCD) circuit by using sub-threshold design method and discontinued operating time to decrease power consumption, which can be widely used in switching inductor converters such as boost, buck or buck-boost converters. The designed ZCD circuit consumes only 40 nA quiescent current to realize nearly 70 dB DC gain and 650 kHz gain-bandwidth (GBW) when it operates. The main comparator of the ZCD circuit has high sensitivity and very low delay time to turn-off the synchronous switches of the DC-DC converter on time. The average quiescent current consumption is less than 1.6 nA because the operating time is only 40 μs under the minimum switching period of 1 ms. Finally, the designed ZCD circuit is used in a boost converter for vibrational energy harvesting applications.","PeriodicalId":329279,"journal":{"name":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","volume":"186 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131866721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EDAPS.2017.8276975
D. Jung, H. Jang, Minki Kim, Junbo Park, H. Lee, C. Jun, S. Ko, S. Son, Jong Mun Park
We propose a dual output dc/dc converter for high efficiency and small form factor in electric bike applications. To implement a converter with single input of 48 V and dual output of 5 V and 12 V, we propose the system architecture combined with a 48-to-12 V converter and a 12-to-5 V converter on single PCB. The input of the 12-to-5 V is connected to the output of the 48-to-12 V converter to obtain stable 5 V without regard to the battery voltage. For high efficiency, both converters use synchronous topologies. For small form factor, the switching frequencies of the converters are fixed to 300 kHz and 1 MHz, respectively. To minimize undesirable PCB noise, several resistors are added and signal paths are designed shortly. The proposed dual output converter was implemented to 45 mm × 42 mm size. When the input voltage of 48 V is supplied, the measure efficiency is 87.5 % under a full-load condition of 3.1 A at 5 V output and 2 A at 12 V output.
{"title":"48-to-5/12 V dual output DC/DC converter for high efficiency and small form factor in electric bike applications","authors":"D. Jung, H. Jang, Minki Kim, Junbo Park, H. Lee, C. Jun, S. Ko, S. Son, Jong Mun Park","doi":"10.1109/EDAPS.2017.8276975","DOIUrl":"https://doi.org/10.1109/EDAPS.2017.8276975","url":null,"abstract":"We propose a dual output dc/dc converter for high efficiency and small form factor in electric bike applications. To implement a converter with single input of 48 V and dual output of 5 V and 12 V, we propose the system architecture combined with a 48-to-12 V converter and a 12-to-5 V converter on single PCB. The input of the 12-to-5 V is connected to the output of the 48-to-12 V converter to obtain stable 5 V without regard to the battery voltage. For high efficiency, both converters use synchronous topologies. For small form factor, the switching frequencies of the converters are fixed to 300 kHz and 1 MHz, respectively. To minimize undesirable PCB noise, several resistors are added and signal paths are designed shortly. The proposed dual output converter was implemented to 45 mm × 42 mm size. When the input voltage of 48 V is supplied, the measure efficiency is 87.5 % under a full-load condition of 3.1 A at 5 V output and 2 A at 12 V output.","PeriodicalId":329279,"journal":{"name":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","volume":"314 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131921829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EDAPS.2017.8276960
Libo Qian, Jifei Sang, Yidie Ye, Ge Shi
Based on extracted equivalent circuit parameters, this paper established the power delivery network model of carbon-based three-dimensional (3-D) integration and derived analytical formulas to predict the voltage drop in the proposed 3-D circuit, in which the horizontal interconnects and vertical TSVs are built with multi-layer graphene nanoribbons (MLGNRs) and carbon nanotubes (CNTs), respectively. Comparison in electrical performance shows that the voltage drop of 3-D integration is dominated by vertical components and therefore increasing the total number of signal/ground TSVs used for power delivery can significantly decrease the maximum voltage drop in 3-D integration. For present fabrication limits, only carbon based 3D integration built with larger diameter MWCNT TSVs and MLGNRs can obtain lower voltage drops in comparison to Cu interconnects. The proposed results would provide some design guides for future carbon-based 3-D integration.
{"title":"Electrical modeling and analysis of carbon based three dimensional integration","authors":"Libo Qian, Jifei Sang, Yidie Ye, Ge Shi","doi":"10.1109/EDAPS.2017.8276960","DOIUrl":"https://doi.org/10.1109/EDAPS.2017.8276960","url":null,"abstract":"Based on extracted equivalent circuit parameters, this paper established the power delivery network model of carbon-based three-dimensional (3-D) integration and derived analytical formulas to predict the voltage drop in the proposed 3-D circuit, in which the horizontal interconnects and vertical TSVs are built with multi-layer graphene nanoribbons (MLGNRs) and carbon nanotubes (CNTs), respectively. Comparison in electrical performance shows that the voltage drop of 3-D integration is dominated by vertical components and therefore increasing the total number of signal/ground TSVs used for power delivery can significantly decrease the maximum voltage drop in 3-D integration. For present fabrication limits, only carbon based 3D integration built with larger diameter MWCNT TSVs and MLGNRs can obtain lower voltage drops in comparison to Cu interconnects. The proposed results would provide some design guides for future carbon-based 3-D integration.","PeriodicalId":329279,"journal":{"name":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132249547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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