Pub Date : 1900-01-01DOI: 10.1109/RFIT.2005.1598863
C. Enz, N. Scolari, U. Yodprasit
Power consumption and size are the most important challenges faced when designing radios for distributed wireless sensor networks (WSN). Reducing power consumption requires optimization across all the layers of the communication systems. Although the MAC layer plays a crucial role in the overall energy efficiency, the radio remains one of the bottleneck for implementing ultra low-power WSN. The power consumption of the radios available today does not allow for continuous operation and the radio has to be duty-cycled in order to reach the targeted several years autonomy. This clearly has an impact on how to design a radio for WSN. Reducing the node size can be partly achieved by a high level of integration of all the functions required by one node on a single chip. This leads to systems-on-chip (SoC) that are dedicated to WSN. This paper addresses the different issues in the design of ultra low-power WSN with a particular emphasis on the radio. It reviews the constraints imposed on the transceiver design by the low-power and low-voltage specifications, the duty-cycled operation and the modulation scheme. Several radio architectures that can potentially be used for WSN are discussed in the perspective of a CMOS implementation. As examples, the 1st-and 2nd-generation of WiseNET ultra low-power transceivers are presented. The 1st-generation WiseNET transceiver is integrated in a 0.5 /spl mu/m standard digital CMOS process. It operates in the 434 MHz band and consumes only 1 mW from a 1 V supply, while achieving a -95 dBm sensitivity for a 24 kb/s data rate with a 10/sup -3/ BER. The 2nd-generation WiseNET transceiver was designed and specifically optimized for the new WiseMAC protocol specially developed for WSN. It runs from a single 1.5 V battery and operates down to 0.9 V while consuming only 1.8 mW in receive mode. It achieves a -104 dBm sensitivity for 25 kb/s data rate with a 10/sup -3/ BER. In addition to this low-power radio, the 2nd-generation WiseNET system-on-chip (SoC) also includes all the functions required for data acquisition, processing and storage of the information provided by the sensor. The WiseNET solution comprising the WiseNET SoC together with the WiseMAC protocol consumes more than 30 times less power than comparable solutions available today, using for example the IEEE 802.15.4 standard. Finally, some important blocks such as the frequency synthesizer and the ADC are discussed in the perspective of moving to higher data rates, higher operating frequency and phase modulation, taking as example the IEEE 802.15.4 standard. Examples of injection locked oscillators and dividers are given. The conversion of I/Q phase modulated signals to digital are illustrated by an example of an I/Q /spl Delta/-/spl Sigma/ ADC and a direct phase ADC.
{"title":"Ultra low-power radio design for wireless sensor networks","authors":"C. Enz, N. Scolari, U. Yodprasit","doi":"10.1109/RFIT.2005.1598863","DOIUrl":"https://doi.org/10.1109/RFIT.2005.1598863","url":null,"abstract":"Power consumption and size are the most important challenges faced when designing radios for distributed wireless sensor networks (WSN). Reducing power consumption requires optimization across all the layers of the communication systems. Although the MAC layer plays a crucial role in the overall energy efficiency, the radio remains one of the bottleneck for implementing ultra low-power WSN. The power consumption of the radios available today does not allow for continuous operation and the radio has to be duty-cycled in order to reach the targeted several years autonomy. This clearly has an impact on how to design a radio for WSN. Reducing the node size can be partly achieved by a high level of integration of all the functions required by one node on a single chip. This leads to systems-on-chip (SoC) that are dedicated to WSN. This paper addresses the different issues in the design of ultra low-power WSN with a particular emphasis on the radio. It reviews the constraints imposed on the transceiver design by the low-power and low-voltage specifications, the duty-cycled operation and the modulation scheme. Several radio architectures that can potentially be used for WSN are discussed in the perspective of a CMOS implementation. As examples, the 1st-and 2nd-generation of WiseNET ultra low-power transceivers are presented. The 1st-generation WiseNET transceiver is integrated in a 0.5 /spl mu/m standard digital CMOS process. It operates in the 434 MHz band and consumes only 1 mW from a 1 V supply, while achieving a -95 dBm sensitivity for a 24 kb/s data rate with a 10/sup -3/ BER. The 2nd-generation WiseNET transceiver was designed and specifically optimized for the new WiseMAC protocol specially developed for WSN. It runs from a single 1.5 V battery and operates down to 0.9 V while consuming only 1.8 mW in receive mode. It achieves a -104 dBm sensitivity for 25 kb/s data rate with a 10/sup -3/ BER. In addition to this low-power radio, the 2nd-generation WiseNET system-on-chip (SoC) also includes all the functions required for data acquisition, processing and storage of the information provided by the sensor. The WiseNET solution comprising the WiseNET SoC together with the WiseMAC protocol consumes more than 30 times less power than comparable solutions available today, using for example the IEEE 802.15.4 standard. Finally, some important blocks such as the frequency synthesizer and the ADC are discussed in the perspective of moving to higher data rates, higher operating frequency and phase modulation, taking as example the IEEE 802.15.4 standard. Examples of injection locked oscillators and dividers are given. The conversion of I/Q phase modulated signals to digital are illustrated by an example of an I/Q /spl Delta/-/spl Sigma/ ADC and a direct phase ADC.","PeriodicalId":337918,"journal":{"name":"2005 IEEE International Wkshp on Radio-Frequency Integration Technology: Integrated Circuits for Wideband Comm & Wireless Sensor Networks","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115756411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RFIT.2005.1598894
Y.J. Chan, C. P. Kung, Z. Pei
Novel technology, printed electronics, to cost down the RFID tags for item level is reported in recent years. We review the technology and application like as rectifier, memory and think film transistor in this paper.
{"title":"Printed RFID: technology and application","authors":"Y.J. Chan, C. P. Kung, Z. Pei","doi":"10.1109/RFIT.2005.1598894","DOIUrl":"https://doi.org/10.1109/RFIT.2005.1598894","url":null,"abstract":"Novel technology, printed electronics, to cost down the RFID tags for item level is reported in recent years. We review the technology and application like as rectifier, memory and think film transistor in this paper.","PeriodicalId":337918,"journal":{"name":"2005 IEEE International Wkshp on Radio-Frequency Integration Technology: Integrated Circuits for Wideband Comm & Wireless Sensor Networks","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116455742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RFIT.2005.1598900
F. Huang, Y. Chan
In this report, an injection-locked frequency divider (ILFD) was designed and realized using the 0.13 /spl mu/m CMOS technologies. It not only demonstrates a variable self-oscillation frequency from 300 MHz to 4.7 GHz adjusted by the controlled voltages, but also exhibits the divider performance with a wide locking range for division ratios of 2, 4 and 6 as the self-oscillation frequency fixed to 2.5 GHz. The transient responses in ILFD, the FSK signal deviations through the frequency down-conversion operation have been demonstrated for the high-order division ratios.
{"title":"A CMOS injection-locked frequency divider with FSK signal deviations for high-order division","authors":"F. Huang, Y. Chan","doi":"10.1109/RFIT.2005.1598900","DOIUrl":"https://doi.org/10.1109/RFIT.2005.1598900","url":null,"abstract":"In this report, an injection-locked frequency divider (ILFD) was designed and realized using the 0.13 /spl mu/m CMOS technologies. It not only demonstrates a variable self-oscillation frequency from 300 MHz to 4.7 GHz adjusted by the controlled voltages, but also exhibits the divider performance with a wide locking range for division ratios of 2, 4 and 6 as the self-oscillation frequency fixed to 2.5 GHz. The transient responses in ILFD, the FSK signal deviations through the frequency down-conversion operation have been demonstrated for the high-order division ratios.","PeriodicalId":337918,"journal":{"name":"2005 IEEE International Wkshp on Radio-Frequency Integration Technology: Integrated Circuits for Wideband Comm & Wireless Sensor Networks","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128338556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RFIT.2005.1598916
Zhigong Wang
The construction of the RF-part of a wireless transceiver and that of an optic-fiber transceiver are described. The functions of the basic function blocks are briefly introduced. Different technologies for RF-IC and ultrahigh speed IC are compared. Circuit techniques required for these IC design are discussed. The mode of fabless IC design plus foundry IC fabrication is explained. A series ICs realized and tested is shown.
{"title":"Fabless IC design for wireless and optic-fiber communications","authors":"Zhigong Wang","doi":"10.1109/RFIT.2005.1598916","DOIUrl":"https://doi.org/10.1109/RFIT.2005.1598916","url":null,"abstract":"The construction of the RF-part of a wireless transceiver and that of an optic-fiber transceiver are described. The functions of the basic function blocks are briefly introduced. Different technologies for RF-IC and ultrahigh speed IC are compared. Circuit techniques required for these IC design are discussed. The mode of fabless IC design plus foundry IC fabrication is explained. A series ICs realized and tested is shown.","PeriodicalId":337918,"journal":{"name":"2005 IEEE International Wkshp on Radio-Frequency Integration Technology: Integrated Circuits for Wideband Comm & Wireless Sensor Networks","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114222153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RFIT.2005.1598866
S. Chakraborty, N. Belk, A. Batra, M. Goel, A. Dabak
Design considerations of a generic wideband communication system differ significantly from its narrowband counterpart. In a wideband system, intermodulation distortion increases significantly, as the signal propagates through various active stages of RF/analog signal processing blocks. Thus, in contrary to the narrowband approach, it requires careful optimization of noise and linearity for a given power consumption. Many of these systems today utilize multicarrier modulation approach to provide robustness for dynamic wireless environment. Multicarrier modulation also aids the development of direct conversion transceivers leading to further optimization of signal processing algorithms at the baseband. In this paper, we would illustrate the architectural trade-off and design consideration of fully integrated direct conversion transceivers in standard silicon based processes. Fundamental considerations of power, linearity, effect of out-of-band blockers, coexistence with other standards would be addressed for a direct conversion UWB transceiver based on multi-band OFDM approach.
{"title":"Towards fully integrated wideband transceivers: fundamental challenges, solutions and future","authors":"S. Chakraborty, N. Belk, A. Batra, M. Goel, A. Dabak","doi":"10.1109/RFIT.2005.1598866","DOIUrl":"https://doi.org/10.1109/RFIT.2005.1598866","url":null,"abstract":"Design considerations of a generic wideband communication system differ significantly from its narrowband counterpart. In a wideband system, intermodulation distortion increases significantly, as the signal propagates through various active stages of RF/analog signal processing blocks. Thus, in contrary to the narrowband approach, it requires careful optimization of noise and linearity for a given power consumption. Many of these systems today utilize multicarrier modulation approach to provide robustness for dynamic wireless environment. Multicarrier modulation also aids the development of direct conversion transceivers leading to further optimization of signal processing algorithms at the baseband. In this paper, we would illustrate the architectural trade-off and design consideration of fully integrated direct conversion transceivers in standard silicon based processes. Fundamental considerations of power, linearity, effect of out-of-band blockers, coexistence with other standards would be addressed for a direct conversion UWB transceiver based on multi-band OFDM approach.","PeriodicalId":337918,"journal":{"name":"2005 IEEE International Wkshp on Radio-Frequency Integration Technology: Integrated Circuits for Wideband Comm & Wireless Sensor Networks","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134502744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RFIT.2005.1598887
D. Belot
Part of the challenge, when issuing transceiver chips for the telecommunication market today, is not only to make a consistent choice between a set standards, but also to choose the adequate technology. Depending on the standards characteristics and the proposed architecture the choice will lead either to system on chip or to system on module solutions.
{"title":"CMOS and SiGe BiCMOS: silicon integrated transceivers technology for SOC and SIP","authors":"D. Belot","doi":"10.1109/RFIT.2005.1598887","DOIUrl":"https://doi.org/10.1109/RFIT.2005.1598887","url":null,"abstract":"Part of the challenge, when issuing transceiver chips for the telecommunication market today, is not only to make a consistent choice between a set standards, but also to choose the adequate technology. Depending on the standards characteristics and the proposed architecture the choice will lead either to system on chip or to system on module solutions.","PeriodicalId":337918,"journal":{"name":"2005 IEEE International Wkshp on Radio-Frequency Integration Technology: Integrated Circuits for Wideband Comm & Wireless Sensor Networks","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130432827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RFIT.2005.1598870
M. Schlechtweg, A. Tessmann, A. Leuther, C. Schw, H. Massler, M. Mikulla, Martin Walther, M. Riessle
High performance integrated circuits and modules for millimeter-wave applications based on metamorphic InAlAs/InGaAs HEMTs on 4" GaAs substrates are presented. An extrinsic transit frequency of 410 GHz for 50 nm gate length devices is achieved. The IC process features high yield on both transistor and circuit levels. Two-stage low-noise amplifiers demonstrate a small signal gain of 20 dB and a noise figure of 2.4 dB at 94 GHz. An amplifier MMIC developed for G-band operation exhibits a gain of 21 dB at 220 GHz. High-gain modules featuring low-noise performance are discussed which enable novel applications, such as millimeter-wave imaging up to 220 GHz.
{"title":"Advanced mm-wave ICs and applications","authors":"M. Schlechtweg, A. Tessmann, A. Leuther, C. Schw, H. Massler, M. Mikulla, Martin Walther, M. Riessle","doi":"10.1109/RFIT.2005.1598870","DOIUrl":"https://doi.org/10.1109/RFIT.2005.1598870","url":null,"abstract":"High performance integrated circuits and modules for millimeter-wave applications based on metamorphic InAlAs/InGaAs HEMTs on 4\" GaAs substrates are presented. An extrinsic transit frequency of 410 GHz for 50 nm gate length devices is achieved. The IC process features high yield on both transistor and circuit levels. Two-stage low-noise amplifiers demonstrate a small signal gain of 20 dB and a noise figure of 2.4 dB at 94 GHz. An amplifier MMIC developed for G-band operation exhibits a gain of 21 dB at 220 GHz. High-gain modules featuring low-noise performance are discussed which enable novel applications, such as millimeter-wave imaging up to 220 GHz.","PeriodicalId":337918,"journal":{"name":"2005 IEEE International Wkshp on Radio-Frequency Integration Technology: Integrated Circuits for Wideband Comm & Wireless Sensor Networks","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134630014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RFIT.2005.1598882
G. Vendelin
Lossless feedback can be applied to three types of microwave amplifiers: (1) high gain amplifiers (HGA) Mason 1954 (2) low noise amplifiers (LNA) Vendelin 1975 and (3) high power amplifiers (HPA). The LNA and HPA are duals of each other. This paper gives a tutorial review of all three feedback amplifiers.
{"title":"Lossless feedback amplifier design","authors":"G. Vendelin","doi":"10.1109/RFIT.2005.1598882","DOIUrl":"https://doi.org/10.1109/RFIT.2005.1598882","url":null,"abstract":"Lossless feedback can be applied to three types of microwave amplifiers: (1) high gain amplifiers (HGA) Mason 1954 (2) low noise amplifiers (LNA) Vendelin 1975 and (3) high power amplifiers (HPA). The LNA and HPA are duals of each other. This paper gives a tutorial review of all three feedback amplifiers.","PeriodicalId":337918,"journal":{"name":"2005 IEEE International Wkshp on Radio-Frequency Integration Technology: Integrated Circuits for Wideband Comm & Wireless Sensor Networks","volume":"2014 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133976256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RFIT.2005.1598905
Chiung-Feng Tai, Chih-Yu Tsai, H. Chiou
A differential variable gain low noise amplifier (DVGLNA) using the 0.35 /spl mu/m 3P3M SiGe BiCMOS process is described in this work. The differential LNA with gain control and high linearity has been developed for WCDMA applications. Using this gain control topology, differential variable gain LNA remains its input and output return loss in both high gain and low gain mode. The circuit measurement is performed by using a FR-4 PCB test fixture. The differential LNA achieves gain of 16.5 dB, noise figure of 2.1 dB, the third-order intercept point of -2 dBm, and the gain control range of 11 dB.
{"title":"A differential variable gain SiGe BiCMOS LNA design using current splitting and feedback techniques","authors":"Chiung-Feng Tai, Chih-Yu Tsai, H. Chiou","doi":"10.1109/RFIT.2005.1598905","DOIUrl":"https://doi.org/10.1109/RFIT.2005.1598905","url":null,"abstract":"A differential variable gain low noise amplifier (DVGLNA) using the 0.35 /spl mu/m 3P3M SiGe BiCMOS process is described in this work. The differential LNA with gain control and high linearity has been developed for WCDMA applications. Using this gain control topology, differential variable gain LNA remains its input and output return loss in both high gain and low gain mode. The circuit measurement is performed by using a FR-4 PCB test fixture. The differential LNA achieves gain of 16.5 dB, noise figure of 2.1 dB, the third-order intercept point of -2 dBm, and the gain control range of 11 dB.","PeriodicalId":337918,"journal":{"name":"2005 IEEE International Wkshp on Radio-Frequency Integration Technology: Integrated Circuits for Wideband Comm & Wireless Sensor Networks","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133565965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RFIT.2005.1598913
S. Thuries, É. Tournier
A phase-to-amplitude converter using a bipolar transistor differential pair with an 8-bits digital-to-analog converter is reported. This technique provides significant saving in power consumption and die size due to the elimination of the ROM and/or complex compute circuit. It renders the design of direct digital synthesizer usable for microwave wireless systems. The circuit has been processed in 0.25 /spl mu/ BiCMOS SiGe: C technology. The measured rejection for the first and the second harmonic is respectively -37 dBc and -63 dBc. The 8-bits D/A converter integral non-linearity and differential non-linearity errors are under 1 LSB. The circuit power consumption is 115 mW and operates from a single 2.7 V supply.
{"title":"A DDS-oriented phase-to-amplitude converter using a SiGe:C bipolar transistors differential pair","authors":"S. Thuries, É. Tournier","doi":"10.1109/RFIT.2005.1598913","DOIUrl":"https://doi.org/10.1109/RFIT.2005.1598913","url":null,"abstract":"A phase-to-amplitude converter using a bipolar transistor differential pair with an 8-bits digital-to-analog converter is reported. This technique provides significant saving in power consumption and die size due to the elimination of the ROM and/or complex compute circuit. It renders the design of direct digital synthesizer usable for microwave wireless systems. The circuit has been processed in 0.25 /spl mu/ BiCMOS SiGe: C technology. The measured rejection for the first and the second harmonic is respectively -37 dBc and -63 dBc. The 8-bits D/A converter integral non-linearity and differential non-linearity errors are under 1 LSB. The circuit power consumption is 115 mW and operates from a single 2.7 V supply.","PeriodicalId":337918,"journal":{"name":"2005 IEEE International Wkshp on Radio-Frequency Integration Technology: Integrated Circuits for Wideband Comm & Wireless Sensor Networks","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133765996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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