Pub Date : 1993-10-20DOI: 10.1109/EPEP.1993.394598
C. Pao, W. Wong, W.D. Gray, C. Liu, D.C. Wang, C.P. Wen
A monolithic X-band coplanar waveguide power amplifier utilizing high yield flip chip interconnect technology has been designed and fabricated. A peak power of 2.5 watts with a power added efficiency better than 24% at 8 GHz has been achieved.<>
{"title":"Flip chip interconnect of 2.5-watt CPW power amplifier MMIC","authors":"C. Pao, W. Wong, W.D. Gray, C. Liu, D.C. Wang, C.P. Wen","doi":"10.1109/EPEP.1993.394598","DOIUrl":"https://doi.org/10.1109/EPEP.1993.394598","url":null,"abstract":"A monolithic X-band coplanar waveguide power amplifier utilizing high yield flip chip interconnect technology has been designed and fabricated. A peak power of 2.5 watts with a power added efficiency better than 24% at 8 GHz has been achieved.<<ETX>>","PeriodicalId":338671,"journal":{"name":"Proceedings of IEEE Electrical Performance of Electronic Packaging","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126842970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-20DOI: 10.1109/EPEP.1993.394596
Barry J. Rubin, S. Daijavad
A powerful code developed by the authors to solve radiation and scattering problems from arbitrary 3D dielectric-conductor structures is modified to provide the terminal characteristics of arbitrary package structures. By incorporating a general de-embedding procedure to eliminate end effects, Y- and S-parameters can be obtained for 3D transmission-line structures; other parameters such as the C and L matrices can also be obtained. Results for microstrip twin-tee and mesh-plane structures are presented and compared with results already in the literature.<>
{"title":"Calculation of multi-port parameters of electronic packages using a general purpose electromagnetics code","authors":"Barry J. Rubin, S. Daijavad","doi":"10.1109/EPEP.1993.394596","DOIUrl":"https://doi.org/10.1109/EPEP.1993.394596","url":null,"abstract":"A powerful code developed by the authors to solve radiation and scattering problems from arbitrary 3D dielectric-conductor structures is modified to provide the terminal characteristics of arbitrary package structures. By incorporating a general de-embedding procedure to eliminate end effects, Y- and S-parameters can be obtained for 3D transmission-line structures; other parameters such as the C and L matrices can also be obtained. Results for microstrip twin-tee and mesh-plane structures are presented and compared with results already in the literature.<<ETX>>","PeriodicalId":338671,"journal":{"name":"Proceedings of IEEE Electrical Performance of Electronic Packaging","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123810299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-20DOI: 10.1109/EPEP.1993.394553
J. Fang, Y. Liu, Y. Chen, Z. Wu, A. Agrawal
A new model for the simulation of power/ground plane noise which is simple in principle, accurate in its solutions, and applicable to various levels of high-speed digital electronics packaging, is given. It is found that one can obtain accurate modeling of delta-I noise in power and ground planes without resorting to full-wave electromagnetic modeling. Sample results of the simulated delta-I noise with the method are shown.<>
{"title":"Modeling of power/ground plane noise in high speed digital electronics packaging","authors":"J. Fang, Y. Liu, Y. Chen, Z. Wu, A. Agrawal","doi":"10.1109/EPEP.1993.394553","DOIUrl":"https://doi.org/10.1109/EPEP.1993.394553","url":null,"abstract":"A new model for the simulation of power/ground plane noise which is simple in principle, accurate in its solutions, and applicable to various levels of high-speed digital electronics packaging, is given. It is found that one can obtain accurate modeling of delta-I noise in power and ground planes without resorting to full-wave electromagnetic modeling. Sample results of the simulated delta-I noise with the method are shown.<<ETX>>","PeriodicalId":338671,"journal":{"name":"Proceedings of IEEE Electrical Performance of Electronic Packaging","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121276063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-20DOI: 10.1109/EPEP.1993.394550
M. Bruns, S. Pepper
Crosstalk contributes to attenuation and signal degradation on microwave transmission lines in addition to coupling signals between lines. Crosstalk is compared as an attenuation mechanism with skin effect and dielectric loss for coupled microstrip lines.<>
{"title":"Crosstalk as an attenuation mechanism in coupled microstrip transmission lines","authors":"M. Bruns, S. Pepper","doi":"10.1109/EPEP.1993.394550","DOIUrl":"https://doi.org/10.1109/EPEP.1993.394550","url":null,"abstract":"Crosstalk contributes to attenuation and signal degradation on microwave transmission lines in addition to coupling signals between lines. Crosstalk is compared as an attenuation mechanism with skin effect and dielectric loss for coupled microstrip lines.<<ETX>>","PeriodicalId":338671,"journal":{"name":"Proceedings of IEEE Electrical Performance of Electronic Packaging","volume":"267 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124343499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-20DOI: 10.1109/EPEP.1993.394554
Wendy S. Becker, B. McCredie, G. Wilkins, A. Iqbal
A methodology for obtaining a model of the power distribution of a computer package is presented. This model is suitable for determining the noise and aiding in the design of a computer package. The physical features of a typical first-level multi-layered computer package is shown. Semiconductor chips and decoupling capacitors are placed on the top surface of the package and the module is connected to a board or card for communication with other components of the computer. A schematic of the final inductance model of a multi-layered ceramic single chip module used in computer products is shown.<>
{"title":"Power distribution modelling of high performance first level computer packages","authors":"Wendy S. Becker, B. McCredie, G. Wilkins, A. Iqbal","doi":"10.1109/EPEP.1993.394554","DOIUrl":"https://doi.org/10.1109/EPEP.1993.394554","url":null,"abstract":"A methodology for obtaining a model of the power distribution of a computer package is presented. This model is suitable for determining the noise and aiding in the design of a computer package. The physical features of a typical first-level multi-layered computer package is shown. Semiconductor chips and decoupling capacitors are placed on the top surface of the package and the module is connected to a board or card for communication with other components of the computer. A schematic of the final inductance model of a multi-layered ceramic single chip module used in computer products is shown.<<ETX>>","PeriodicalId":338671,"journal":{"name":"Proceedings of IEEE Electrical Performance of Electronic Packaging","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125632285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-20DOI: 10.1109/EPEP.1993.394571
P. Kok, D. De Zutter
A quasi-static method is described for calculating the excess capacitance and inductance of via's. The considered via geometry contains connecting strips, pads on the via, and finite ground plane thickness. The influence of the pad size and the size of the ground plane opening on the via capacitance, inductance and impedance is examined.<>
{"title":"An integral equation approach to the prediction of the capacitance and the inductance of a via through-hole","authors":"P. Kok, D. De Zutter","doi":"10.1109/EPEP.1993.394571","DOIUrl":"https://doi.org/10.1109/EPEP.1993.394571","url":null,"abstract":"A quasi-static method is described for calculating the excess capacitance and inductance of via's. The considered via geometry contains connecting strips, pads on the via, and finite ground plane thickness. The influence of the pad size and the size of the ground plane opening on the via capacitance, inductance and impedance is examined.<<ETX>>","PeriodicalId":338671,"journal":{"name":"Proceedings of IEEE Electrical Performance of Electronic Packaging","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114306585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-20DOI: 10.1109/EPEP.1993.394563
L. Silveira, I. Elfadel, J. White
A state-space algorithm for model-order reduction based on the balancing of a system realization is presented, with the important characteristic that the reduced order model is guaranteed to be stable. Results are presented demonstrating that the balanced-realization approach generates accurate, stable models, whereas the Pade method is unstable.<>
{"title":"A guaranteed stable order reduction algorithm for packaging and interconnect simulation","authors":"L. Silveira, I. Elfadel, J. White","doi":"10.1109/EPEP.1993.394563","DOIUrl":"https://doi.org/10.1109/EPEP.1993.394563","url":null,"abstract":"A state-space algorithm for model-order reduction based on the balancing of a system realization is presented, with the important characteristic that the reduced order model is guaranteed to be stable. Results are presented demonstrating that the balanced-realization approach generates accurate, stable models, whereas the Pade method is unstable.<<ETX>>","PeriodicalId":338671,"journal":{"name":"Proceedings of IEEE Electrical Performance of Electronic Packaging","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128262049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-20DOI: 10.1109/EPEP.1993.394597
H.-H. Chen, S. Chung
The shielding effect of a diaphragm in a packaged microstrip line is analyzed using the mode-matching method together with the method of lines. The influence of the width and the depth of the diaphragm on the scatterings of the dominant-mode and higher-order-mode incidences is analyzed and compared.<>
{"title":"Shielding effect of a diaphragm in a packaged microstrip circuit","authors":"H.-H. Chen, S. Chung","doi":"10.1109/EPEP.1993.394597","DOIUrl":"https://doi.org/10.1109/EPEP.1993.394597","url":null,"abstract":"The shielding effect of a diaphragm in a packaged microstrip line is analyzed using the mode-matching method together with the method of lines. The influence of the width and the depth of the diaphragm on the scatterings of the dominant-mode and higher-order-mode incidences is analyzed and compared.<<ETX>>","PeriodicalId":338671,"journal":{"name":"Proceedings of IEEE Electrical Performance of Electronic Packaging","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128780073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-20DOI: 10.1109/EPEP.1993.394582
L.X. Lu, C. Wu, J. Litva
It has been shown that the finite difference time domain (FDTD) method is an accurate and flexible technique to simulate complex electromagnetic problems. A 3D-FDTD software package is introduced. It can be used to simulate electronic packaging problems from an electromagnetic field point of view.<>
{"title":"A new three dimensional finite difference time domain (3D-FDTD) simulator for modelling electronic interconnections and packaging","authors":"L.X. Lu, C. Wu, J. Litva","doi":"10.1109/EPEP.1993.394582","DOIUrl":"https://doi.org/10.1109/EPEP.1993.394582","url":null,"abstract":"It has been shown that the finite difference time domain (FDTD) method is an accurate and flexible technique to simulate complex electromagnetic problems. A 3D-FDTD software package is introduced. It can be used to simulate electronic packaging problems from an electromagnetic field point of view.<<ETX>>","PeriodicalId":338671,"journal":{"name":"Proceedings of IEEE Electrical Performance of Electronic Packaging","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126832168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-20DOI: 10.1109/EPEP.1993.394604
R. Senthinathan, A. Mehra, M. Mahalingam, Y. Doi, H. Astrain
Summary form only given, as follows. High performance CMOS device technology for 5 V and 3.3 V operations is discussed. Off-chip package delays and simultaneous switching noise (SSN) are selected as metrics to evaluate the impact due to packaging. Devices are housed in quad flat packages (QFPs) and pin grid array (PGAs) packages. With 3.3 V supply, to have a computationally comparable system, device sizes need to be changed to obtain similar current drive. Devices are scaled to achieve similar and enhanced performance for reduced supply voltage. Maintaining computational throughput (CTP) introduces comparable noise levels for 5 V and 3.3 V operations. This increases the probability of false switching in 3.3 V operation. Noise levels for lesser, comparable, and faster CTP 3.3-V packaged devices are given. False switching for 3.3 V operation is analyzed using receiver dynamic noise immunity (DNI). Trends in overall noise-to-signal ratio for further reduced supply voltages are given.<>
{"title":"Electrical packaging requirements for low voltage ICs-3.3 V High Performance CMOS devices as a case study","authors":"R. Senthinathan, A. Mehra, M. Mahalingam, Y. Doi, H. Astrain","doi":"10.1109/EPEP.1993.394604","DOIUrl":"https://doi.org/10.1109/EPEP.1993.394604","url":null,"abstract":"Summary form only given, as follows. High performance CMOS device technology for 5 V and 3.3 V operations is discussed. Off-chip package delays and simultaneous switching noise (SSN) are selected as metrics to evaluate the impact due to packaging. Devices are housed in quad flat packages (QFPs) and pin grid array (PGAs) packages. With 3.3 V supply, to have a computationally comparable system, device sizes need to be changed to obtain similar current drive. Devices are scaled to achieve similar and enhanced performance for reduced supply voltage. Maintaining computational throughput (CTP) introduces comparable noise levels for 5 V and 3.3 V operations. This increases the probability of false switching in 3.3 V operation. Noise levels for lesser, comparable, and faster CTP 3.3-V packaged devices are given. False switching for 3.3 V operation is analyzed using receiver dynamic noise immunity (DNI). Trends in overall noise-to-signal ratio for further reduced supply voltages are given.<<ETX>>","PeriodicalId":338671,"journal":{"name":"Proceedings of IEEE Electrical Performance of Electronic Packaging","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122491285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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