Pub Date : 2007-11-07DOI: 10.1109/HLDVT.2007.4392788
Tao Lv, Tong Xu, Yang Zhao, Huawei Li, Xiaowei Li
This paper presents the item-missing error model. It stems from the analysis of real bugs that are collected in two market-oriented projects: (1) the AMBA interface of a general-purpose microprocessor IP core; (2) a wireless sensor network oriented embedded processor. The bugs are analyzed via code structure comparison, and it is found that item-missing errors merit attention. The test generation method for item-missing error model is proposed. Structural information obtained from this error model is helpful to reach a greater probability of bug detection than that in random-generation verification with only functional constraints. Finally, the proposed test method is applied in verification of our designs, and experimental results demonstrate the effectiveness of this method.
{"title":"Bug analysis and corresponding error models in real designs","authors":"Tao Lv, Tong Xu, Yang Zhao, Huawei Li, Xiaowei Li","doi":"10.1109/HLDVT.2007.4392788","DOIUrl":"https://doi.org/10.1109/HLDVT.2007.4392788","url":null,"abstract":"This paper presents the item-missing error model. It stems from the analysis of real bugs that are collected in two market-oriented projects: (1) the AMBA interface of a general-purpose microprocessor IP core; (2) a wireless sensor network oriented embedded processor. The bugs are analyzed via code structure comparison, and it is found that item-missing errors merit attention. The test generation method for item-missing error model is proposed. Structural information obtained from this error model is helpful to reach a greater probability of bug detection than that in random-generation verification with only functional constraints. Finally, the proposed test method is applied in verification of our designs, and experimental results demonstrate the effectiveness of this method.","PeriodicalId":339324,"journal":{"name":"2007 IEEE International High Level Design Validation and Test Workshop","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134148108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-07DOI: 10.1109/HLDVT.2007.4392805
O. Guzey, Li-C. Wang
Generating tests to achieve high coverage in simulation-based functional verification can be very challenging. Constrained-random and coverage-directed test generation methods have been proposed and shown with various degrees of success. In this paper, we propose a new tool built on top of an existing constrained random test generation framework. The goal of this tool is to extract constraints from simulation data for improving controllability of internal signals. We present two automatic constraint extraction algorithms. Extracted constraints can be put back into constrained test-bench to generate tests for simultaneously controlling multiple signals. We demonstrate the effectiveness and scalability of the constraint extraction tool based on experiments on OpenSparc T1 microprocessor.
{"title":"Coverage-directed test generation through automatic constraint extraction","authors":"O. Guzey, Li-C. Wang","doi":"10.1109/HLDVT.2007.4392805","DOIUrl":"https://doi.org/10.1109/HLDVT.2007.4392805","url":null,"abstract":"Generating tests to achieve high coverage in simulation-based functional verification can be very challenging. Constrained-random and coverage-directed test generation methods have been proposed and shown with various degrees of success. In this paper, we propose a new tool built on top of an existing constrained random test generation framework. The goal of this tool is to extract constraints from simulation data for improving controllability of internal signals. We present two automatic constraint extraction algorithms. Extracted constraints can be put back into constrained test-bench to generate tests for simultaneously controlling multiple signals. We demonstrate the effectiveness and scalability of the constraint extraction tool based on experiments on OpenSparc T1 microprocessor.","PeriodicalId":339324,"journal":{"name":"2007 IEEE International High Level Design Validation and Test Workshop","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128136990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-07DOI: 10.1109/HLDVT.2007.4392782
Eric Cheung, H. Hsieh, F. Balarin
Multiprocessor System-on-Chip (MPSoC) has emerged as the most promising architecture for future embedded system designs, and Kahn Process Networks (KPN) have been shown to be an excellent solution to model applications for MPSoC because it allows maximum freedom in implementation. However, the effects of buffer sizing for KPN applications on MPSoC are not well investigated. Sizes for the bounded FIFOs affect the parallelism in the implementations and the performance of the systems. To the best of our knowledge, buffer sizing for performance optimization in MPSOC has not been addressed before. We propose an off-line automatic buffer sizing algorithm based on the rate constraints and the dependency information gathered from the profiled results. The algorithm can be applied to rate-constraint application such as MPEG-2 decoder to determine the minimum buffer sizes that satisfies the constraints. Our study shows that our algorithm can automatically size the buffers such that the total buffer usage is reduced by orders of magnitude for a given rate constraint.
{"title":"Automatic buffer sizing for rate-constrained KPN applications on multiprocessor system-on-chip","authors":"Eric Cheung, H. Hsieh, F. Balarin","doi":"10.1109/HLDVT.2007.4392782","DOIUrl":"https://doi.org/10.1109/HLDVT.2007.4392782","url":null,"abstract":"Multiprocessor System-on-Chip (MPSoC) has emerged as the most promising architecture for future embedded system designs, and Kahn Process Networks (KPN) have been shown to be an excellent solution to model applications for MPSoC because it allows maximum freedom in implementation. However, the effects of buffer sizing for KPN applications on MPSoC are not well investigated. Sizes for the bounded FIFOs affect the parallelism in the implementations and the performance of the systems. To the best of our knowledge, buffer sizing for performance optimization in MPSOC has not been addressed before. We propose an off-line automatic buffer sizing algorithm based on the rate constraints and the dependency information gathered from the profiled results. The algorithm can be applied to rate-constraint application such as MPEG-2 decoder to determine the minimum buffer sizes that satisfies the constraints. Our study shows that our algorithm can automatically size the buffers such that the total buffer usage is reduced by orders of magnitude for a given rate constraint.","PeriodicalId":339324,"journal":{"name":"2007 IEEE International High Level Design Validation and Test Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130836190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-07DOI: 10.1109/HLDVT.2007.4392793
Mingsong Chen, P. Mishra, Dhrubajyoti Kalita
SystemC transaction level modeling (TLM) is widely used to reduce the overall design and validation effort of complex system-on-chip (SOC) architectures. Due to lack of efficient techniques, the amount of reuse between abstraction levels is limited in many scenarios such as reuse of TLM level tests for RTL validation. This paper presents a top-down methodology for generation of RTL tests from SystemC TLM specifications. This paper makes two important contributions: automatic test generation from TLM specification using a transition-based coverage metric and automatic translation of TLM tests into RTL tests using a set of transformation rules. Our initial results using a router design demonstrate the usefulness of our approach by capturing various functional errors as well as inconsistencies in the implementation.
{"title":"Towards RTL test generation from SystemC TLM specifications","authors":"Mingsong Chen, P. Mishra, Dhrubajyoti Kalita","doi":"10.1109/HLDVT.2007.4392793","DOIUrl":"https://doi.org/10.1109/HLDVT.2007.4392793","url":null,"abstract":"SystemC transaction level modeling (TLM) is widely used to reduce the overall design and validation effort of complex system-on-chip (SOC) architectures. Due to lack of efficient techniques, the amount of reuse between abstraction levels is limited in many scenarios such as reuse of TLM level tests for RTL validation. This paper presents a top-down methodology for generation of RTL tests from SystemC TLM specifications. This paper makes two important contributions: automatic test generation from TLM specification using a transition-based coverage metric and automatic translation of TLM tests into RTL tests using a set of transformation rules. Our initial results using a router design demonstrate the usefulness of our approach by capturing various functional errors as well as inconsistencies in the implementation.","PeriodicalId":339324,"journal":{"name":"2007 IEEE International High Level Design Validation and Test Workshop","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121192020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-07DOI: 10.1109/HLDVT.2007.4392778
Kiran Ramineni, I. Harris, Shireesh Verma
Hierarchical testing requires the verification of individual processes followed by the verification of the interactions among processes. The large number of potential interactions between processes must be managed in order to make the testing process tractable. Fortunately, many potential interactions are actually infeasible and should be ignored during the verification process. Data dependency between processes indicates the potential for a feasible interaction but absolute feasibility can only be determined by evaluating control-flow paths across interacting processes. We propose a method to identify feasible interactions for testing through static analysis combined with the use of a constraint satisfaction programming (CSP) solving engine.
{"title":"Improving feasible interactions among multiple processes","authors":"Kiran Ramineni, I. Harris, Shireesh Verma","doi":"10.1109/HLDVT.2007.4392778","DOIUrl":"https://doi.org/10.1109/HLDVT.2007.4392778","url":null,"abstract":"Hierarchical testing requires the verification of individual processes followed by the verification of the interactions among processes. The large number of potential interactions between processes must be managed in order to make the testing process tractable. Fortunately, many potential interactions are actually infeasible and should be ignored during the verification process. Data dependency between processes indicates the potential for a feasible interaction but absolute feasibility can only be determined by evaluating control-flow paths across interacting processes. We propose a method to identify feasible interactions for testing through static analysis combined with the use of a constraint satisfaction programming (CSP) solving engine.","PeriodicalId":339324,"journal":{"name":"2007 IEEE International High Level Design Validation and Test Workshop","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126349139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-07DOI: 10.1109/HLDVT.2007.4392780
Eric Cheung, H. Hsieh, F. Balarin
In this paper we develop a framework for fast and accurate multiprocessor system performance simulation. Our simulation model generator generates simulation modules with accurate time deltas for software processes based on the intermediate representations generated by a compiler. The simulation modules are simulated as concurrent tasks in multiprocessor system performance simulation environment in SystemC. We use aggregated waits to reduce overhead in the simulation kernel and triple the speed of the simulation. Our study shows that we can obtain overall system performance results with less than 6% error while simulating at 150times faster than using an Instruction Set Simulator. This opens up system design space explorations that were not possible before.
{"title":"Framework for fast and accurate performance simulation of multiprocessor systems","authors":"Eric Cheung, H. Hsieh, F. Balarin","doi":"10.1109/HLDVT.2007.4392780","DOIUrl":"https://doi.org/10.1109/HLDVT.2007.4392780","url":null,"abstract":"In this paper we develop a framework for fast and accurate multiprocessor system performance simulation. Our simulation model generator generates simulation modules with accurate time deltas for software processes based on the intermediate representations generated by a compiler. The simulation modules are simulated as concurrent tasks in multiprocessor system performance simulation environment in SystemC. We use aggregated waits to reduce overhead in the simulation kernel and triple the speed of the simulation. Our study shows that we can obtain overall system performance results with less than 6% error while simulating at 150times faster than using an Instruction Set Simulator. This opens up system design space explorations that were not possible before.","PeriodicalId":339324,"journal":{"name":"2007 IEEE International High Level Design Validation and Test Workshop","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122105480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/hldvt.2007.4392787
{"title":"Session 4: Debug","authors":"","doi":"10.1109/hldvt.2007.4392787","DOIUrl":"https://doi.org/10.1109/hldvt.2007.4392787","url":null,"abstract":"","PeriodicalId":339324,"journal":{"name":"2007 IEEE International High Level Design Validation and Test Workshop","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127799468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/hldvt.2007.4392783
{"title":"Session 3: Invited Session: Post-Silicon Validation","authors":"","doi":"10.1109/hldvt.2007.4392783","DOIUrl":"https://doi.org/10.1109/hldvt.2007.4392783","url":null,"abstract":"","PeriodicalId":339324,"journal":{"name":"2007 IEEE International High Level Design Validation and Test Workshop","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124567185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/hldvt.2007.4392799
{"title":"Session 7: invited session: high level design","authors":"","doi":"10.1109/hldvt.2007.4392799","DOIUrl":"https://doi.org/10.1109/hldvt.2007.4392799","url":null,"abstract":"","PeriodicalId":339324,"journal":{"name":"2007 IEEE International High Level Design Validation and Test Workshop","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134250106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/hldvt.2007.4392779
{"title":"Session 2: Multiprocessors 11","authors":"","doi":"10.1109/hldvt.2007.4392779","DOIUrl":"https://doi.org/10.1109/hldvt.2007.4392779","url":null,"abstract":"","PeriodicalId":339324,"journal":{"name":"2007 IEEE International High Level Design Validation and Test Workshop","volume":"06 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128847154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：