Pub Date : 2007-11-07DOI: 10.1109/HLDVT.2007.4392804
Tommy Bojan, Manuel Aguilar Arreola, Eran Shlomo, Tal Shachar
Post-Silicon verification is an activity that is still maturing with respect to functional coverage methodologies. The architectural and micro-architectural feedback from silicon can be used to enhance the level of quality of the test suite, and allows monitoring the frequency of interesting micro-architectural events. For the latest Intel Corporation's multi-core processors (Intelreg CoreTM2 Duo processor, Intelreg CoreTM2 Extreme processor, Dual-Core Intelreg Xeonreg processor 5100 series, Intelreg CoreTM2 Duo mobile processor,), validation uses Random Instruction Tool (RIT) generated tests, so the need for coverage increases in importance. There are different methods that are used to understand what the RIT is exercising. In this paper, three efficient orthogonal solution and results vectors are presented: (A) Front-Side-Bus (FSB) Checker and coverage approach exploiting the re-use of mature pre-silicon tools, (B) Extended Execution Trace (EET) mechanism which uses special microcode patches for external tracking of microcode flows, and (C) Performance Monitoring Hardware used to collect frequency coverage of specific internal events. With these approaches, effective Front-Side Bus, microcode and architectural coverage was collected, analyzed and used as feedback for better tuning the RIT generation parameters. These three solutions have been put to practice in projects code named Conroe, Woodcrest, Merom, and Penryn to further improve the quality of test generated by the System Validation's (SV) RIT.
{"title":"Functional coverage measurements and results in post-Silicon validation of Core™2 duo family","authors":"Tommy Bojan, Manuel Aguilar Arreola, Eran Shlomo, Tal Shachar","doi":"10.1109/HLDVT.2007.4392804","DOIUrl":"https://doi.org/10.1109/HLDVT.2007.4392804","url":null,"abstract":"Post-Silicon verification is an activity that is still maturing with respect to functional coverage methodologies. The architectural and micro-architectural feedback from silicon can be used to enhance the level of quality of the test suite, and allows monitoring the frequency of interesting micro-architectural events. For the latest Intel Corporation's multi-core processors (Intelreg CoreTM2 Duo processor, Intelreg CoreTM2 Extreme processor, Dual-Core Intelreg Xeonreg processor 5100 series, Intelreg CoreTM2 Duo mobile processor,), validation uses Random Instruction Tool (RIT) generated tests, so the need for coverage increases in importance. There are different methods that are used to understand what the RIT is exercising. In this paper, three efficient orthogonal solution and results vectors are presented: (A) Front-Side-Bus (FSB) Checker and coverage approach exploiting the re-use of mature pre-silicon tools, (B) Extended Execution Trace (EET) mechanism which uses special microcode patches for external tracking of microcode flows, and (C) Performance Monitoring Hardware used to collect frequency coverage of specific internal events. With these approaches, effective Front-Side Bus, microcode and architectural coverage was collected, analyzed and used as feedback for better tuning the RIT generation parameters. These three solutions have been put to practice in projects code named Conroe, Woodcrest, Merom, and Penryn to further improve the quality of test generated by the System Validation's (SV) RIT.","PeriodicalId":339324,"journal":{"name":"2007 IEEE International High Level Design Validation and Test Workshop","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134015134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-07DOI: 10.1109/HLDVT.2007.4392792
D. Mathaikutty, Sumit Ahuja, A. Dingankar, S. Shukla
Functional validation of System Level Models, such as those modeled with SystemC, is an important and complex problem. One of the problems in their functional validation is the test case generation with good coverage and higher potential to find faults in the design. We propose a coverage-directed test generation framework for system level design validation by combining the synchronous language ESTEREL, and its advanced verification capability, with C++ based system level language SystemC. The main contributions of this paper are (i) the integrated framework for model-driven development and validation of system-level designs with a combination of ESTEREL, and SystemC; and (ii) the test generation framework for generating test suites to satisfy traditional coverage metrics such as the statement and branch as well as a complex metric such as modified condition/decision coverage (MCDC) employed in the validation of safety-critical software systems. The framework also generates tests that attain functional coverage using properties specified in a temporal language and assertion-based verification (namely PSL). We demonstrate the methodology with a case study by developing and validating a critical power state machine component that is used for power management in embedded systems.
{"title":"Model-driven test generation for system level validation","authors":"D. Mathaikutty, Sumit Ahuja, A. Dingankar, S. Shukla","doi":"10.1109/HLDVT.2007.4392792","DOIUrl":"https://doi.org/10.1109/HLDVT.2007.4392792","url":null,"abstract":"Functional validation of System Level Models, such as those modeled with SystemC, is an important and complex problem. One of the problems in their functional validation is the test case generation with good coverage and higher potential to find faults in the design. We propose a coverage-directed test generation framework for system level design validation by combining the synchronous language ESTEREL, and its advanced verification capability, with C++ based system level language SystemC. The main contributions of this paper are (i) the integrated framework for model-driven development and validation of system-level designs with a combination of ESTEREL, and SystemC; and (ii) the test generation framework for generating test suites to satisfy traditional coverage metrics such as the statement and branch as well as a complex metric such as modified condition/decision coverage (MCDC) employed in the validation of safety-critical software systems. The framework also generates tests that attain functional coverage using properties specified in a temporal language and assertion-based verification (namely PSL). We demonstrate the methodology with a case study by developing and validating a critical power state machine component that is used for power management in embedded systems.","PeriodicalId":339324,"journal":{"name":"2007 IEEE International High Level Design Validation and Test Workshop","volume":"259 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133070651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-07DOI: 10.1109/HLDVT.2007.4392811
M. Murciano, M. Violante
The design of complex embedded systems deployed in safety-critical or mission-critical applications mandate the availability of methods for validating the system dependability across the whole design flow. In this paper we introduce a fault-injection approach based on loadable kernel modules which can be adopted as soon as a running prototype of the systems is available. Moreover, in order to decouple dependability analysis from the hardware availability, we propose to adopt hardware virtualization for building virtual prototype. Extensive experimental results are reported showing that dependability analyzes made using virtual prototype closely match those performed on physical prototypes.
{"title":"Validating the dependability of embedded systems through fault injection by means of loadable kernel modules","authors":"M. Murciano, M. Violante","doi":"10.1109/HLDVT.2007.4392811","DOIUrl":"https://doi.org/10.1109/HLDVT.2007.4392811","url":null,"abstract":"The design of complex embedded systems deployed in safety-critical or mission-critical applications mandate the availability of methods for validating the system dependability across the whole design flow. In this paper we introduce a fault-injection approach based on loadable kernel modules which can be adopted as soon as a running prototype of the systems is available. Moreover, in order to decouple dependability analysis from the hardware availability, we propose to adopt hardware virtualization for building virtual prototype. Extensive experimental results are reported showing that dependability analyzes made using virtual prototype closely match those performed on physical prototypes.","PeriodicalId":339324,"journal":{"name":"2007 IEEE International High Level Design Validation and Test Workshop","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125607816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-07DOI: 10.1109/HLDVT.2007.4392798
N. Chabini, W. Wolf
This paper addresses the problem of computing the initial state for a retimed circuit. It focuses on solving this problem for the class of synchronous mono-phase sequential circuits that can be modeled as a single far-loop without conditional branches in its body. For this class of circuits, we suggest that to solve this problem, one can solve the problem of computing the prologue after applying retiming on the loop modeling the input circuit. The number of instructions of this prologue depends on the retiming used. We provide algorithms to compute a retiming to get a prologue with a reduced size. Having a prologue with a small size allows reducing the size of the circuitry required for putting the retimed circuit in the target initial state. We provide experimental results to test the effectiveness of the proposed algorithms.
{"title":"An approach for computing the initial state for retimed synchronous sequential circuits","authors":"N. Chabini, W. Wolf","doi":"10.1109/HLDVT.2007.4392798","DOIUrl":"https://doi.org/10.1109/HLDVT.2007.4392798","url":null,"abstract":"This paper addresses the problem of computing the initial state for a retimed circuit. It focuses on solving this problem for the class of synchronous mono-phase sequential circuits that can be modeled as a single far-loop without conditional branches in its body. For this class of circuits, we suggest that to solve this problem, one can solve the problem of computing the prologue after applying retiming on the loop modeling the input circuit. The number of instructions of this prologue depends on the retiming used. We provide algorithms to compute a retiming to get a prologue with a reduced size. Having a prologue with a small size allows reducing the size of the circuitry required for putting the retimed circuit in the target initial state. We provide experimental results to test the effectiveness of the proposed algorithms.","PeriodicalId":339324,"journal":{"name":"2007 IEEE International High Level Design Validation and Test Workshop","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132980439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-07DOI: 10.1109/HLDVT.2007.4392808
Sunil Kakkar, J. Bergeron, B. Bailey, H. Foster, I. Harris
{"title":"Panel: Unified approach leading to a seamlessly evolving test bench for all phases of a multi-core design, validation and production test","authors":"Sunil Kakkar, J. Bergeron, B. Bailey, H. Foster, I. Harris","doi":"10.1109/HLDVT.2007.4392808","DOIUrl":"https://doi.org/10.1109/HLDVT.2007.4392808","url":null,"abstract":"","PeriodicalId":339324,"journal":{"name":"2007 IEEE International High Level Design Validation and Test Workshop","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121492881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-07DOI: 10.1109/HLDVT.2007.4392784
J. Kumar, Catherine Ahlschlager, P. Isberg
In general, considerable time and resources are spent during pre-silicon verification phase to proactively minimize functional issues at first silicon. This is no different on the UltraSPARC T2 - the world's fastest commodity microprocessor. We deployed simulation, formal and emulation technologies coupled with solid methodology to cover all our bases, ensuring functional success of first silicon. A robust post-silicon verification methodology is critical to speeding up time-to-ramp and to prevent loss of product revenue. Formal verification has been deployed as one of the means to root cause silicon failure due to functional error. To ensure correct RTL fix, it is vital to be able to effectively reproduce a failure observed in silicon test and recreate it in RTL environment. One way of getting the RTL failure recreated quickly is by writing the failure scenario in terms of property and using formal tool to generate traces that lead to the failure. In this paper, we describe how simulation, formal and emulation technology coupled with capabilities instrumented in our test generators and RTL for repeatability helped isolate faults, run millions of new verification cycles to validate RTL fixes and formally prove the fixes to be error free. We also share impact of our post-silicon validation strategy on productization schedule of Sun UltraSPARC T2 processor.
{"title":"Post-silicon verification methodology on Sun’s UItraSPARC T2","authors":"J. Kumar, Catherine Ahlschlager, P. Isberg","doi":"10.1109/HLDVT.2007.4392784","DOIUrl":"https://doi.org/10.1109/HLDVT.2007.4392784","url":null,"abstract":"In general, considerable time and resources are spent during pre-silicon verification phase to proactively minimize functional issues at first silicon. This is no different on the UltraSPARC T2 - the world's fastest commodity microprocessor. We deployed simulation, formal and emulation technologies coupled with solid methodology to cover all our bases, ensuring functional success of first silicon. A robust post-silicon verification methodology is critical to speeding up time-to-ramp and to prevent loss of product revenue. Formal verification has been deployed as one of the means to root cause silicon failure due to functional error. To ensure correct RTL fix, it is vital to be able to effectively reproduce a failure observed in silicon test and recreate it in RTL environment. One way of getting the RTL failure recreated quickly is by writing the failure scenario in terms of property and using formal tool to generate traces that lead to the failure. In this paper, we describe how simulation, formal and emulation technology coupled with capabilities instrumented in our test generators and RTL for repeatability helped isolate faults, run millions of new verification cycles to validate RTL fixes and formally prove the fixes to be error free. We also share impact of our post-silicon validation strategy on productization schedule of Sun UltraSPARC T2 processor.","PeriodicalId":339324,"journal":{"name":"2007 IEEE International High Level Design Validation and Test Workshop","volume":"53 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126005023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-07DOI: 10.1109/HLDVT.2007.4392806
Shireesh Verma, I. Harris, Kiran Ramineni
Functional coverage models which measure the sufficiency of test stimuli are essential to the verification process. A key source of difficulty in their deployment emanates from the manual and imprecise nature of their development process and the lack of a sound measure of their quality. A functional coverage model can be considered complete only if it accurately reflects the behavior of the Design under Verification (DUV) as described in the specification. We present a method to automatically generate coverage models from a formal CTL description of design properties. Experimental results show that the functional coverage models generated using our technique correlate well with the detection of randomly injected errors into a design.
{"title":"Automatic generation of functional coverage models from CTL","authors":"Shireesh Verma, I. Harris, Kiran Ramineni","doi":"10.1109/HLDVT.2007.4392806","DOIUrl":"https://doi.org/10.1109/HLDVT.2007.4392806","url":null,"abstract":"Functional coverage models which measure the sufficiency of test stimuli are essential to the verification process. A key source of difficulty in their deployment emanates from the manual and imprecise nature of their development process and the lack of a sound measure of their quality. A functional coverage model can be considered complete only if it accurately reflects the behavior of the Design under Verification (DUV) as described in the specification. We present a method to automatically generate coverage models from a formal CTL description of design properties. Experimental results show that the functional coverage models generated using our technique correlate well with the detection of randomly injected errors into a design.","PeriodicalId":339324,"journal":{"name":"2007 IEEE International High Level Design Validation and Test Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131355826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-07DOI: 10.1109/HLDVT.2007.4392785
Shakti Kapoor
Recent IBM processors used in various computer systems including gaming systems are a very aggressive design, addressing three main challenges of the processor design -Memory wall, Power wall and ILP wall. To break these walls the some designs utilized multi threaded, multi core and yet high frequency. These kinds of designs increased the complexity of the test stream generation for processor verification especially in a stress test environment. Moreover Cell Broadband Engine TM (Cell/B.E.) utilizes heterogeneous multi core, multi threaded with high. This further increased the complexity of the verification. This paper describes some of the scenarios, the Post Silicon Verification team addressed in their effort of verification of the Cell/B.E. and other game processors.
{"title":"Challenges in post-silicon verification of IBM’s Cell/B.E. and other game processors","authors":"Shakti Kapoor","doi":"10.1109/HLDVT.2007.4392785","DOIUrl":"https://doi.org/10.1109/HLDVT.2007.4392785","url":null,"abstract":"Recent IBM processors used in various computer systems including gaming systems are a very aggressive design, addressing three main challenges of the processor design -Memory wall, Power wall and ILP wall. To break these walls the some designs utilized multi threaded, multi core and yet high frequency. These kinds of designs increased the complexity of the test stream generation for processor verification especially in a stress test environment. Moreover Cell Broadband Engine TM (Cell/B.E.) utilizes heterogeneous multi core, multi threaded with high. This further increased the complexity of the verification. This paper describes some of the scenarios, the Post Silicon Verification team addressed in their effort of verification of the Cell/B.E. and other game processors.","PeriodicalId":339324,"journal":{"name":"2007 IEEE International High Level Design Validation and Test Workshop","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125569648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-07DOI: 10.1109/HLDVT.2007.4392789
Kai-Hui Chang, I. Wagner, V. Bertacco, I. Markov
Recent improvements in design verification strive to automate the error-detection process and greatly enhance engineers' ability to detect functional errors. However, the process of diagnosing the cause of these errors and fixing them remains difficult and requires significant ad-hoc manual effort. Our work proposes improvements to this aspect of verification by presenting novel constructs and algorithms to automate the error-repair process at the Register-Transfer Level (RTL), where most development occurs. Our contributions include a new RTL error model and scalable error-repair algorithms. Empirical results show that our solution can diagnose and correct errors in just a handful of minutes even for complex designs o/up to several thousand lines of RTL code in minutes. This demonstrates the superior scalability and efficiency of our approach compared to previous work.
{"title":"Automatic error diagnosis and correction for RTL designs","authors":"Kai-Hui Chang, I. Wagner, V. Bertacco, I. Markov","doi":"10.1109/HLDVT.2007.4392789","DOIUrl":"https://doi.org/10.1109/HLDVT.2007.4392789","url":null,"abstract":"Recent improvements in design verification strive to automate the error-detection process and greatly enhance engineers' ability to detect functional errors. However, the process of diagnosing the cause of these errors and fixing them remains difficult and requires significant ad-hoc manual effort. Our work proposes improvements to this aspect of verification by presenting novel constructs and algorithms to automate the error-repair process at the Register-Transfer Level (RTL), where most development occurs. Our contributions include a new RTL error model and scalable error-repair algorithms. Empirical results show that our solution can diagnose and correct errors in just a handful of minutes even for complex designs o/up to several thousand lines of RTL code in minutes. This demonstrates the superior scalability and efficiency of our approach compared to previous work.","PeriodicalId":339324,"journal":{"name":"2007 IEEE International High Level Design Validation and Test Workshop","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115344309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-07DOI: 10.1109/HLDVT.2007.4392800
G. Berry
Esterel v7 is a high-level behavioral hardware design language currently used by major semiconductor companies to develop circuits and software circuit models. The language is supported by the Esterel Studio tool that supports a full flow from design capture to formal verification and generation of hardware and software models. Esterel is especially suited to control-intensive circuits such as memory and cache controllers, complex DMAs, bus interfaces and bridges, power controllers, transactors, etc. It is also used to design specialized processors and to model hardware at a higher level of abstraction (e.g., instruction set architecture).
{"title":"Circuit design and verication with Esterel v7 and Esterel Studio","authors":"G. Berry","doi":"10.1109/HLDVT.2007.4392800","DOIUrl":"https://doi.org/10.1109/HLDVT.2007.4392800","url":null,"abstract":"Esterel v7 is a high-level behavioral hardware design language currently used by major semiconductor companies to develop circuits and software circuit models. The language is supported by the Esterel Studio tool that supports a full flow from design capture to formal verification and generation of hardware and software models. Esterel is especially suited to control-intensive circuits such as memory and cache controllers, complex DMAs, bus interfaces and bridges, power controllers, transactors, etc. It is also used to design specialized processors and to model hardware at a higher level of abstraction (e.g., instruction set architecture).","PeriodicalId":339324,"journal":{"name":"2007 IEEE International High Level Design Validation and Test Workshop","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123714405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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