Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116577
R. Wiśniewski, M. Wiśniewska, M. Węgrzyn, N. Marranghello
In the paper the improvement of a traditional structure of a microprogrammed controller with sharing codes is discussed. The idea is based on the modification of internal modules and connections of the device. Such a solution permits to reduce the number of embedded memories needed for implementation of the microprogrammed controller on programmable structures, especially FPGAs.
{"title":"Design of microprogrammed controllers with address converter implemented on programmable systems with embedded memories","authors":"R. Wiśniewski, M. Wiśniewska, M. Węgrzyn, N. Marranghello","doi":"10.1109/EWDTS.2011.6116577","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116577","url":null,"abstract":"In the paper the improvement of a traditional structure of a microprogrammed controller with sharing codes is discussed. The idea is based on the modification of internal modules and connections of the device. Such a solution permits to reduce the number of embedded memories needed for implementation of the microprogrammed controller on programmable structures, especially FPGAs.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131423946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116600
V. Lesnikov, T. Naumovich, A. Chastikov, S. V. Armishev
Implementation of canonical structures of IIR digital filters demands execution of the minimum number of operations. Thus these filters can realize any transfer function. Therefore they represent considerable interest at implementation by using FPGA and ASIC. Researches have shown that except widely known classical canonical forms there are also others. They can possess better characteristics. This paper is devoted to generation of all possible canonical structures. This problem is a part of process of designing of the given class of filters.
{"title":"A generation of canonical forms for design of IIR digital filters","authors":"V. Lesnikov, T. Naumovich, A. Chastikov, S. V. Armishev","doi":"10.1109/EWDTS.2011.6116600","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116600","url":null,"abstract":"Implementation of canonical structures of IIR digital filters demands execution of the minimum number of operations. Thus these filters can realize any transfer function. Therefore they represent considerable interest at implementation by using FPGA and ASIC. Researches have shown that except widely known classical canonical forms there are also others. They can possess better characteristics. This paper is devoted to generation of all possible canonical structures. This problem is a part of process of designing of the given class of filters.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124675259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116607
K. Petrosyants, E. Vologdin, Dmitry Smirnov, R. Torgovnikov, M. Kozhukhov
Theeffects of neutron irradiation on both Si bipolar junction transistor (BJT) and SiGeheterojunction transistor (HBT) are investigated using Synopsys/ISE TCAD tool. For this purpose the carrier lifetime degradation under irradiation models are included in the program. It was established that at fluence 4·1013 cm−2 the Si BJT exhibited a degradation in current gain of 50% for high level and 80% for low level of E-B junction injection. For SiGe HBT at fluences as high as 1015 cm−2 the degradation of peak current gain is less than 40%,and the devicemaintains a peak current gain of 80 – 100 after 1015 cm−2. The cut-off and maximum oscillations frequencies are small sensitive to neutron irradiation. The simulation results are in good agreement with experimental data.
{"title":"Si BJT and SiGe HBT performance modeling after neutron radiation exposure","authors":"K. Petrosyants, E. Vologdin, Dmitry Smirnov, R. Torgovnikov, M. Kozhukhov","doi":"10.1109/EWDTS.2011.6116607","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116607","url":null,"abstract":"Theeffects of neutron irradiation on both Si bipolar junction transistor (BJT) and SiGeheterojunction transistor (HBT) are investigated using Synopsys/ISE TCAD tool. For this purpose the carrier lifetime degradation under irradiation models are included in the program. It was established that at fluence 4·10<sup>13</sup> cm<sup>−2</sup> the Si BJT exhibited a degradation in current gain of 50% for high level and 80% for low level of E-B junction injection. For SiGe HBT at fluences as high as 10<sup>15</sup> cm<sup>−2</sup> the degradation of peak current gain is less than 40%,and the devicemaintains a peak current gain of 80 – 100 after 10<sup>15</sup> cm<sup>−2</sup>. The cut-off and maximum oscillations frequencies are small sensitive to neutron irradiation. The simulation results are in good agreement with experimental data.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131070043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116409
O. Kuznietsov, O. Tsopa
A simulation model of wireless MIMO system with wiretap channel based on recommendations of standard IEEE802.11n is reviewed in the paper. The curves of system secretiveness, channel quality are shown. Obtained modeling results are compared to the theoretical. System single frequency interferer robustness graphs are shown.
{"title":"Variant of wireless MIMO channel security estimation model based on cluster approach","authors":"O. Kuznietsov, O. Tsopa","doi":"10.1109/EWDTS.2011.6116409","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116409","url":null,"abstract":"A simulation model of wireless MIMO system with wiretap channel based on recommendations of standard IEEE802.11n is reviewed in the paper. The curves of system secretiveness, channel quality are shown. Obtained modeling results are compared to the theoretical. System single frequency interferer robustness graphs are shown.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130845193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116578
M. Wiśniewska, R. Wiśniewski, M. Węgrzyn, N. Marranghello
In the paper the method of reduction of the memory size in the microprogrammed controllers with sharing codes is discussed. The idea is based on the modification of internal modules and connections of the device. Next, the reduction of the microinstruction length based on the hypergraph theory is performed, thus the total size of the memory is highly reduced.
{"title":"Reduction of the memory size in the microprogrammed controllers","authors":"M. Wiśniewska, R. Wiśniewski, M. Węgrzyn, N. Marranghello","doi":"10.1109/EWDTS.2011.6116578","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116578","url":null,"abstract":"In the paper the method of reduction of the memory size in the microprogrammed controllers with sharing codes is discussed. The idea is based on the modification of internal modules and connections of the device. Next, the reduction of the microinstruction length based on the hypergraph theory is performed, thus the total size of the memory is highly reduced.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122197797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116417
N. Dudar, V. Borzdov
The technology was proposed for fabrication of the silicon stabilitron with the stabilizing voltage of 6,5 V. There were defined substrate resistivity, phosphorus diffusion into substrate mode, ensuring the required stabilization voltage values under the conditions of room and two marginal values of temperatures (−55°C, +150°C). Comparison was made of the simulation data with the experiment results.
{"title":"Device-process simulation of discrete silicon stabilitron with the stabilizing voltage of 6,5 V","authors":"N. Dudar, V. Borzdov","doi":"10.1109/EWDTS.2011.6116417","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116417","url":null,"abstract":"The technology was proposed for fabrication of the silicon stabilitron with the stabilizing voltage of 6,5 V. There were defined substrate resistivity, phosphorus diffusion into substrate mode, ensuring the required stabilization voltage values under the conditions of room and two marginal values of temperatures (−55°C, +150°C). Comparison was made of the simulation data with the experiment results.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129208173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116414
A. Belous, V. Nelayev, S. Shvedov, V. Stempitsky, Tran Tuan Trung, A. Turtsevich
New contribution to the methodology for simulation of Deep SubMicron (DSM), nanometer-scale Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) features is proposed. The discussed approach is based on the use of traditional “compact” submicron device model. Parameters of these models are verified by means of fitting procedure to results obtained by use exact physical models taking into account quantum effects accompanying charge carriers transfer in DSM MOSFET.
{"title":"Compact DSM MOSFET model and its parameters extraction","authors":"A. Belous, V. Nelayev, S. Shvedov, V. Stempitsky, Tran Tuan Trung, A. Turtsevich","doi":"10.1109/EWDTS.2011.6116414","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116414","url":null,"abstract":"New contribution to the methodology for simulation of Deep SubMicron (DSM), nanometer-scale Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) features is proposed. The discussed approach is based on the use of traditional “compact” submicron device model. Parameters of these models are verified by means of fitting procedure to results obtained by use exact physical models taking into account quantum effects accompanying charge carriers transfer in DSM MOSFET.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130640582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116411
K. Petrosyants, E. Orekhov, D. Popov, I. Kharitonov, L. Sambursky, A. P. Yatmanov, A. Voevodin, A. Mansurov
A comparison of delay time (td) for n- and p-MOSFETs switches with silicon on sapphire (SOS), silicon on insulator (SOI) and bulk silicon structures is presented. Two step TCAD-SPICE simulation procedure was used to define td for the set of 3.0…0.25 um MOSFETs fabricated by the three mentioned technologies. It was shown that 0.5 um Peregrine UTSi SOS n- and p-MOSFET provided the td reduction of 220–240% in comparison with bulk silicon and 20–25% with SOI.
比较了蓝宝石上硅(SOS)、绝缘体上硅(SOI)和体硅结构的n- mosfet和p- mosfet开关的延迟时间(td)。采用两步TCAD-SPICE仿真程序定义了三种技术制备的3.0…0.25 um mosfet的td。结果表明，与大块硅相比，0.5 um Peregrine UTSi SOS n-和p-MOSFET的td降低了220-240%，与SOI相比降低了20-25%。
{"title":"TCAD-SPICE simulation of MOSFET switch delay time for different CMOS technologies","authors":"K. Petrosyants, E. Orekhov, D. Popov, I. Kharitonov, L. Sambursky, A. P. Yatmanov, A. Voevodin, A. Mansurov","doi":"10.1109/EWDTS.2011.6116411","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116411","url":null,"abstract":"A comparison of delay time (td) for n- and p-MOSFETs switches with silicon on sapphire (SOS), silicon on insulator (SOI) and bulk silicon structures is presented. Two step TCAD-SPICE simulation procedure was used to define td for the set of 3.0…0.25 um MOSFETs fabricated by the three mentioned technologies. It was shown that 0.5 um Peregrine UTSi SOS n- and p-MOSFET provided the td reduction of 220–240% in comparison with bulk silicon and 20–25% with SOI.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"459 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124343440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116603
N. Levchenko, A. Okunev, D. Yakhontov, D. Zmejev
The paper describes the new tools for dynamic display of the computational process for modeling a dataflow parallel computing system that implements non-traditional architecture. These tools allow evaluating the effectiveness of program and localization functions during the task.
{"title":"Debugging and testing features of the dataflow parallel computing system components and devices","authors":"N. Levchenko, A. Okunev, D. Yakhontov, D. Zmejev","doi":"10.1109/EWDTS.2011.6116603","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116603","url":null,"abstract":"The paper describes the new tools for dynamic display of the computational process for modeling a dataflow parallel computing system that implements non-traditional architecture. These tools allow evaluating the effectiveness of program and localization functions during the task.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124979054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116606
A. Drozd, V. Kharchenko, S. Antoshchuk, Y. Sulima, M. Drozd
Particularities of on-line testing for digital components in safety-critical Instrumentation and Control systems (I&CS) are analyzed. A problem of on-line testing associated with insufficient checkability of the digital components in safety-critical I&CS (reactor trip system) is considered. A method of checkability estimation is offered. An example of comparator checkability assessment is shown. An approach to increase checkability of the digital components is proposed.
{"title":"Checkability of the digital components in safety-critical systems: Problems and solutions","authors":"A. Drozd, V. Kharchenko, S. Antoshchuk, Y. Sulima, M. Drozd","doi":"10.1109/EWDTS.2011.6116606","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116606","url":null,"abstract":"Particularities of on-line testing for digital components in safety-critical Instrumentation and Control systems (I&CS) are analyzed. A problem of on-line testing associated with insufficient checkability of the digital components in safety-critical I&CS (reactor trip system) is considered. A method of checkability estimation is offered. An example of comparator checkability assessment is shown. An approach to increase checkability of the digital components is proposed.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123611415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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