Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116587
Y. Bekhtin
It is proposed an adaptive, data-driven wavelet-based method for lossy compression of noisy images. The suggested method uses a common criterion to simultaneously estimate the values of threshold and quantization interval. The results of modeling show the advantage of the designed codec comparing to well-known codecs in the sense of PSNR and SSIM criteria.
{"title":"Adaptive wavelet codec for noisy image compression","authors":"Y. Bekhtin","doi":"10.1109/EWDTS.2011.6116587","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116587","url":null,"abstract":"It is proposed an adaptive, data-driven wavelet-based method for lossy compression of noisy images. The suggested method uses a common criterion to simultaneously estimate the values of threshold and quantization interval. The results of modeling show the advantage of the designed codec comparing to well-known codecs in the sense of PSNR and SSIM criteria.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133744903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116576
V. Djigan
The paper considers the processing of constant modulus signals in multi-beam adaptive arrays. The processing is based on the substitution of multi-extreme cost-function of the adaptive filtering process by a linearly constrained quadratic one and the decomposition of the signal processing algorithm for multi-beam array on a number of separate algorithms, related to each sub-array. The simulation demonstrates the signal processing efficiency in the rejection of the interferences.
{"title":"Adaptive signal processing in multi-beam arrays","authors":"V. Djigan","doi":"10.1109/EWDTS.2011.6116576","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116576","url":null,"abstract":"The paper considers the processing of constant modulus signals in multi-beam adaptive arrays. The processing is based on the substitution of multi-extreme cost-function of the adaptive filtering process by a linearly constrained quadratic one and the decomposition of the signal processing algorithm for multi-beam array on a number of separate algorithms, related to each sub-array. The simulation demonstrates the signal processing efficiency in the rejection of the interferences.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"146 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123820975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116586
V. Barinov, A. Smirnov, Danila Migalin
Emerging network systems require specific medium access layer and routing protocols to be suitable in a high speed environment. We present modified 802.11 MAC and OLSR protocols for medium access and multihop routing in highly dynamic ad-hoc networks. Modified 802.11 algorithms use power and smart antenna management. A modified OLSR protocol uses node location, speed and trajectory analyses heuristics. The analysis of OPNET™ simulations shows that our proposed algorithms have several advantages over other MANET protocols in terms of packet delivery ratio, delay and overhead.
{"title":"Modified protocol for data transmission in ad-hoc networks with high speed objects using directional antennas","authors":"V. Barinov, A. Smirnov, Danila Migalin","doi":"10.1109/EWDTS.2011.6116586","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116586","url":null,"abstract":"Emerging network systems require specific medium access layer and routing protocols to be suitable in a high speed environment. We present modified 802.11 MAC and OLSR protocols for medium access and multihop routing in highly dynamic ad-hoc networks. Modified 802.11 algorithms use power and smart antenna management. A modified OLSR protocol uses node location, speed and trajectory analyses heuristics. The analysis of OPNET™ simulations shows that our proposed algorithms have several advantages over other MANET protocols in terms of packet delivery ratio, delay and overhead.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131112789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116416
V. Hahanov, W. Gharibi, Dong-Won Park, E. Litvinova
This article describes an infrastructure and technologies for analyzing information space, based on virtual cybercomputer. A model and metrics for cyberspace, where subjects are the interacting processes or phenomena with the physical carrier in the form of computer systems and networks, are proposed. The structural model of high-speed multimatrix processor designed for fast and accurate search of information objects in cyberspace is described.
{"title":"Cybercomputer for information space analysis","authors":"V. Hahanov, W. Gharibi, Dong-Won Park, E. Litvinova","doi":"10.1109/EWDTS.2011.6116416","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116416","url":null,"abstract":"This article describes an infrastructure and technologies for analyzing information space, based on virtual cybercomputer. A model and metrics for cyberspace, where subjects are the interacting processes or phenomena with the physical carrier in the form of computer systems and networks, are proposed. The structural model of high-speed multimatrix processor designed for fast and accurate search of information objects in cyberspace is described.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122472737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116429
Jack H. Arabian
It is costly to have defective networks and nodes. There are many factors involved in the cost of defective design of networks. The size of development team, stage of development when the defect occurs, routing protocols and subtlety of the defect are only a few of the possibilities. Testing software, therefore has to be designed to detect the defect, and as early as possible in the design cycle. Otherwise the costs can be overwhelming. This is yet another compelling argument for QA engineers to justify up-front test costs similar to the electronics design programs of JTAG (Joint Test Action Group for boundary scan) or BIST (Built-in Self Test) circuitry.
{"title":"Software testing of a simple network","authors":"Jack H. Arabian","doi":"10.1109/EWDTS.2011.6116429","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116429","url":null,"abstract":"It is costly to have defective networks and nodes. There are many factors involved in the cost of defective design of networks. The size of development team, stage of development when the defect occurs, routing protocols and subtlety of the defect are only a few of the possibilities. Testing software, therefore has to be designed to detect the defect, and as early as possible in the design cycle. Otherwise the costs can be overwhelming. This is yet another compelling argument for QA engineers to justify up-front test costs similar to the electronics design programs of JTAG (Joint Test Action Group for boundary scan) or BIST (Built-in Self Test) circuitry.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126884743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116421
S. Carlo, Giulio Gambardella, Marco Indaco, Daniele Rolfo, P. Prinetto
The paper presents a new unifying formalism introduced to effectively support the automatic generation of assembly test programs to be used as SBST (Software Based Self-Testing) for both data and instruction cache memories. In particular, the new formalism allows the description of the target memory, of the selected March Test algorithm, and the way this has to be customize to adapt it to the selected cache.
{"title":"A unifying formalism to support automated synthesis of SBSTs for embedded caches","authors":"S. Carlo, Giulio Gambardella, Marco Indaco, Daniele Rolfo, P. Prinetto","doi":"10.1109/EWDTS.2011.6116421","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116421","url":null,"abstract":"The paper presents a new unifying formalism introduced to effectively support the automatic generation of assembly test programs to be used as SBST (Software Based Self-Testing) for both data and instruction cache memories. In particular, the new formalism allows the description of the target memory, of the selected March Test algorithm, and the way this has to be customize to adapt it to the selected cache.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132184201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116415
A. Artamonov, V. Nelayev, I. Shelibak, A. Turtsevich
Power semiconductor devices are important microelectronic components determined by the efficiency, size, and cost of electronic systems for energy application. Insulated Gate Bipolar Transistor (IGBT) is popular device from series of microelectronics elements base for power energetic applications. Exact design of the modern element base for microelectronics provides reliable operation of the system. The paper presents and discusses the results of IGBT manufacturing technology and device design. These results were obtained by means of Silvaco software package intended for technology/device simulation.
{"title":"IGBT technology design and device optimization","authors":"A. Artamonov, V. Nelayev, I. Shelibak, A. Turtsevich","doi":"10.1109/EWDTS.2011.6116415","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116415","url":null,"abstract":"Power semiconductor devices are important microelectronic components determined by the efficiency, size, and cost of electronic systems for energy application. Insulated Gate Bipolar Transistor (IGBT) is popular device from series of microelectronics elements base for power energetic applications. Exact design of the modern element base for microelectronics provides reliable operation of the system. The paper presents and discusses the results of IGBT manufacturing technology and device design. These results were obtained by means of Silvaco software package intended for technology/device simulation.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128505781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116589
V. Tverdokhlebov
In paper is offered to represent lows of functioning of discrete determined automatons with finite or infinite set of states by points on geometrical curves. For this automata mapping located on analytically defined geometrical curve. The class of failures is defined by family of automatons mappings. Diagnostic procedures are defined by the equations and the inequalities, constructed with use of analytical tasks of curves.
{"title":"Geometrical approach to technical diagnosing of automatons","authors":"V. Tverdokhlebov","doi":"10.1109/EWDTS.2011.6116589","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116589","url":null,"abstract":"In paper is offered to represent lows of functioning of discrete determined automatons with finite or infinite set of states by points on geometrical curves. For this automata mapping located on analytically defined geometrical curve. The class of failures is defined by family of automatons mappings. Diagnostic procedures are defined by the equations and the inequalities, constructed with use of analytical tasks of curves.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114468447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116575
A. Barkalov, L. Titarenko, O. Hebda
The method is proposed for reduction of the area of matrix implementation of the circuit of the Moore finite state machine (FSM). The method is based on optimal state coding and decomposition of a matrix of terms on two sub-matrixes. Thus classes of the pseudoequivalent states are used. Such approach allows to reduce number of lines of the table of transitions of Moore FSM up to this value of the equivalent Mealy FSM. As a result the area of the matrixes forming excitation function of a states memory register is optimized. An example of the proposed method application is given.
{"title":"Hardware reduction for matrix circuit of control Moore automaton","authors":"A. Barkalov, L. Titarenko, O. Hebda","doi":"10.1109/EWDTS.2011.6116575","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116575","url":null,"abstract":"The method is proposed for reduction of the area of matrix implementation of the circuit of the Moore finite state machine (FSM). The method is based on optimal state coding and decomposition of a matrix of terms on two sub-matrixes. Thus classes of the pseudoequivalent states are used. Such approach allows to reduce number of lines of the table of transitions of Moore FSM up to this value of the equivalent Mealy FSM. As a result the area of the matrixes forming excitation function of a states memory register is optimized. An example of the proposed method application is given.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125372926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116605
Ngene Christopher Umerah, Hahanov Vladimir Ivanovich
The design of System-on-Chip (SoC) is becoming more difficult by the day with the increase in complexity of consumer requirements and time-to-market pressures. The use of HDLs in the design of digital system has become more ubiquitous and challenging as ever if timely delivery of product with increased yield is to be achieved. A technological and process-efficient models and methods for diagnosis of functional violations in software and/ or hardware products are proposed. The assertion-based transaction graph used in this model can be transformed into a tabular data structure that focuses on parallel execution of logic operations when searching for defective components or blocks with functional violation in HDL models.
{"title":"A diagnostic model for detecting functional violation in HDL-code of System-on-Chip","authors":"Ngene Christopher Umerah, Hahanov Vladimir Ivanovich","doi":"10.1109/EWDTS.2011.6116605","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116605","url":null,"abstract":"The design of System-on-Chip (SoC) is becoming more difficult by the day with the increase in complexity of consumer requirements and time-to-market pressures. The use of HDLs in the design of digital system has become more ubiquitous and challenging as ever if timely delivery of product with increased yield is to be achieved. A technological and process-efficient models and methods for diagnosis of functional violations in software and/ or hardware products are proposed. The assertion-based transaction graph used in this model can be transformed into a tabular data structure that focuses on parallel execution of logic operations when searching for defective components or blocks with functional violation in HDL models.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125388886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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