Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116595
T. Mohamadi
This paper presents a Real Time Operating System (RTOS) for using in AVR microcontrollers. Using RTOS can result to eliminating processor waiting without doing any applicable work. By using RTOS a lot of tasks can be run independently and simultaneously. So the CPU's efficiency will be higher than conventional systems with infinite loops. Although there are too many RTOS like QNX, they are not free and cheep. Others like μC/OS-II need too much memory space rather than simple microcontroller such as AVR microcontrollers. This paper describes a compact and efficient RTOS for AVR microcontrollers. This RTOS is preemptive multitasking. The design has good performance, small code size, and low memory usage as the design was specifically implemented for AVR devices. Finally a practical algorithm with its suitable circuit with atmega32 is presented to test this information about the designed RTOS.
{"title":"Real Time Operating System for AVR microcontrollers","authors":"T. Mohamadi","doi":"10.1109/EWDTS.2011.6116595","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116595","url":null,"abstract":"This paper presents a Real Time Operating System (RTOS) for using in AVR microcontrollers. Using RTOS can result to eliminating processor waiting without doing any applicable work. By using RTOS a lot of tasks can be run independently and simultaneously. So the CPU's efficiency will be higher than conventional systems with infinite loops. Although there are too many RTOS like QNX, they are not free and cheep. Others like μC/OS-II need too much memory space rather than simple microcontroller such as AVR microcontrollers. This paper describes a compact and efficient RTOS for AVR microcontrollers. This RTOS is preemptive multitasking. The design has good performance, small code size, and low memory usage as the design was specifically implemented for AVR devices. Finally a practical algorithm with its suitable circuit with atmega32 is presented to test this information about the designed RTOS.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130812113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116412
A. Kamkin
Simulation-based verification is a widely-spread approach to ensure functional correctness of hardware designs [1,2]. It is usually done by co-simulating a design under verification with an independently created reference model and checking conformance of their reactions. To reduce verification expenses, abstract models are commonly used (they are simpler, less error-prone and more reusable). Design timing (decomposition of operations into micro-operations and scheduling of those micro-operations) is the main object for abstraction. However, there are several problems in using time-abstract reference models for simulation-based verification. The paper discusses some of the problems and suggests simple, practice-oriented techniques to solve them.
{"title":"Simulation-based hardware verification with time-abstract models","authors":"A. Kamkin","doi":"10.1109/EWDTS.2011.6116412","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116412","url":null,"abstract":"Simulation-based verification is a widely-spread approach to ensure functional correctness of hardware designs [1,2]. It is usually done by co-simulating a design under verification with an independently created reference model and checking conformance of their reactions. To reduce verification expenses, abstract models are commonly used (they are simpler, less error-prone and more reusable). Design timing (decomposition of operations into micro-operations and scheduling of those micro-operations) is the main object for abstraction. However, there are several problems in using time-abstract reference models for simulation-based verification. The paper discusses some of the problems and suggests simple, practice-oriented techniques to solve them.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123655390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116602
M.Yu. Balanov, Olga Mamedova
Continuous phase spread spectrum signal optimization problem is considered. The key optimization parameter in the paper is number of information symbol intervals before merging phase trajectories for different information sequences. This optimization is good at least for two reasons: 1) it defines the information symbol depth at which the minimum square Euclidean distance can reach upper bound; 2) it defines Viterbi algorithm depth analysis in a receiver. The case of rational modulation index continuous phase spread spectrum signal is separately considered. Optimization results for some simple signal formats were found.
{"title":"Optimization some characteristics of continuous phase spread spectrum signal","authors":"M.Yu. Balanov, Olga Mamedova","doi":"10.1109/EWDTS.2011.6116602","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116602","url":null,"abstract":"Continuous phase spread spectrum signal optimization problem is considered. The key optimization parameter in the paper is number of information symbol intervals before merging phase trajectories for different information sequences. This optimization is good at least for two reasons: 1) it defines the information symbol depth at which the minimum square Euclidean distance can reach upper bound; 2) it defines Viterbi algorithm depth analysis in a receiver. The case of rational modulation index continuous phase spread spectrum signal is separately considered. Optimization results for some simple signal formats were found.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129090865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116579
Victor Zviagin
ATPG (Automatic Test Pattern Generation) for arbitrary digital circuit is not possible without previously verification feature been realized at first and without testability been estimated and changed to appropriate level as second. ATPG for arbitrary digital circuit is not possible without hazard free sequences generation at third. At forth ATPG is divided into two versions: for verification test pattern generation and for hardware test pattern generation. CAD combined all four listed features is denoted as the Testware CAD. Our Testware CAD provides Design for Test & Test for Design technology (in brief DFT & TFD). Data about such kind system are described here and more completely at site http://twcad.ifmo.ru
{"title":"The Testware CAD","authors":"Victor Zviagin","doi":"10.1109/EWDTS.2011.6116579","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116579","url":null,"abstract":"ATPG (Automatic Test Pattern Generation) for arbitrary digital circuit is not possible without previously verification feature been realized at first and without testability been estimated and changed to appropriate level as second. ATPG for arbitrary digital circuit is not possible without hazard free sequences generation at third. At forth ATPG is divided into two versions: for verification test pattern generation and for hardware test pattern generation. CAD combined all four listed features is denoted as the Testware CAD. Our Testware CAD provides Design for Test & Test for Design technology (in brief DFT & TFD). Data about such kind system are described here and more completely at site http://twcad.ifmo.ru","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129286519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：