Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116581
S. Berdyshev, V. Boykov, Y. Gimpilevich, Yuri Iskiv, Gilad Keren, Denis Muratov, Igor Smirnov, V. Vertegel
Practical experience of pre-silicon verification of the processor core is presented. The proposed methodology gives good results, good coverage, and requires a short verification time period.
{"title":"Methodology of the pre-silicon verification of the processor core","authors":"S. Berdyshev, V. Boykov, Y. Gimpilevich, Yuri Iskiv, Gilad Keren, Denis Muratov, Igor Smirnov, V. Vertegel","doi":"10.1109/EWDTS.2011.6116581","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116581","url":null,"abstract":"Practical experience of pre-silicon verification of the processor core is presented. The proposed methodology gives good results, good coverage, and requires a short verification time period.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129313870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116570
N. Levchenko, A. Okunev, D. Yakhontov
The paper reviews the architecture of dataflow parallel computing system, describes the operation mechanisms of one of the main system modules - the mapping unit. The pipeline mode of mapping unit is considered; an increasing of the capacity associated with the introduction of the pipeline is estimated. The process of step-by-step optimization of pipeline with a description of the bottlenecks and ways to bypass them is shown.
{"title":"Organization of pipeline operations in mapping unit of the dataflow parallel computing system","authors":"N. Levchenko, A. Okunev, D. Yakhontov","doi":"10.1109/EWDTS.2011.6116570","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116570","url":null,"abstract":"The paper reviews the architecture of dataflow parallel computing system, describes the operation mechanisms of one of the main system modules - the mapping unit. The pipeline mode of mapping unit is considered; an increasing of the capacity associated with the introduction of the pipeline is estimated. The process of step-by-step optimization of pipeline with a description of the bottlenecks and ways to bypass them is shown.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127187165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116596
V. Andreeva
In this paper a procedure of compaction a test set for combinational circuits is considered. The compaction procedure is oriented to a test set that represented as set of test cubes. The main idea of compaction a test cubes is to find all maximally compatible subsets by constructing decomposition tree. An irredundant cover of test cubes by all maximally compatible subsets allows finding minimal or close to minimal size of test pattern setting. Experimental results for benchmark circuits demonstrate the efficiency of the suggested compaction procedure.
{"title":"Test set compaction procedure for combinational circuits based on decomposition tree","authors":"V. Andreeva","doi":"10.1109/EWDTS.2011.6116596","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116596","url":null,"abstract":"In this paper a procedure of compaction a test set for combinational circuits is considered. The compaction procedure is oriented to a test set that represented as set of test cubes. The main idea of compaction a test cubes is to find all maximally compatible subsets by constructing decomposition tree. An irredundant cover of test cubes by all maximally compatible subsets allows finding minimal or close to minimal size of test pattern setting. Experimental results for benchmark circuits demonstrate the efficiency of the suggested compaction procedure.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116588518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116584
P. Manikandan, Bjørn B. Larsen, E. Aas, Mohammad Areef
This paper presents a programmable built-in self-test (PBIST) methodology for embedded SRAMs. The BIST logic adapts the test controller with micro code encoding technique in order to control test operation sequences. The macro codes are used to select any of seven MARCH algorithms, and detect different faults of the memory under test (MUT). This BIST supports both the test and normal operation modes. The experimental results show that this work gives 17–47% improved area overhead and 16–41% enhanced speed compared to three published results.
{"title":"A programmable BIST with macro and micro codes for embedded SRAMs","authors":"P. Manikandan, Bjørn B. Larsen, E. Aas, Mohammad Areef","doi":"10.1109/EWDTS.2011.6116584","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116584","url":null,"abstract":"This paper presents a programmable built-in self-test (PBIST) methodology for embedded SRAMs. The BIST logic adapts the test controller with micro code encoding technique in order to control test operation sequences. The macro codes are used to select any of seven MARCH algorithms, and detect different faults of the memory under test (MUT). This BIST supports both the test and normal operation modes. The experimental results show that this work gives 17–47% improved area overhead and 16–41% enhanced speed compared to three published results.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126953615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116582
S. Krutchinsky, Mikhail S. Tsybin
Universal procedure of schematic design of compensating feedback loops is offered. The synthesis schemes algorithm with cancellation is formulated. Examples of high-stable circuit with cancellation design are considered and appropriateness of use and development of multidefferential OA as new type of IP blocks of active components is shown.
{"title":"Optimal schematic design of low-Q IP blocks","authors":"S. Krutchinsky, Mikhail S. Tsybin","doi":"10.1109/EWDTS.2011.6116582","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116582","url":null,"abstract":"Universal procedure of schematic design of compensating feedback loops is offered. The synthesis schemes algorithm with cancellation is formulated. Examples of high-stable circuit with cancellation design are considered and appropriateness of use and development of multidefferential OA as new type of IP blocks of active components is shown.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"287 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132603971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116420
B. Konorev, V. Sergiyenko, G. Chertkov
The results of development of the techniques which form the scenario of target technology ≪Evidential independent verification of I&C Systems Software of critical application≫ and utilities of the scenario support at information, analytical and organizational levels are presented in the article. The result of the scenario implementation is the quantitative definition of latent faults probability and completeness of test coverage for critical software. This technology can be used by I&C systems developers, certification and regulation bodies to carry out independent verification (or certification) during modernization and modification of critical software directly on client objects without intruding (interrupting) in technological processes.
{"title":"The evidential independent verification of software of information and control systems, critical to safety: Functional model of scenario","authors":"B. Konorev, V. Sergiyenko, G. Chertkov","doi":"10.1109/EWDTS.2011.6116420","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116420","url":null,"abstract":"The results of development of the techniques which form the scenario of target technology ≪Evidential independent verification of I&C Systems Software of critical application≫ and utilities of the scenario support at information, analytical and organizational levels are presented in the article. The result of the scenario implementation is the quantitative definition of latent faults probability and completeness of test coverage for critical software. This technology can be used by I&C systems developers, certification and regulation bodies to carry out independent verification (or certification) during modernization and modification of critical software directly on client objects without intruding (interrupting) in technological processes.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134245311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116571
A. Lotfi, P. Kabiri, Z. Navabi
The number of memory components in today's chips is increasing considerably. Through the limitations on area and number of test pins, it is not feasible to use a separate BIST architecture for testing every memory on the chip. Therefore, it is essential to have a configurable BIST architecture. In this paper, a configurable memory BIST architecture that can test different memories having different sizes and configurations with an arbitrary test algorithm is proposed.
{"title":"Configurable architecture for memory BIST","authors":"A. Lotfi, P. Kabiri, Z. Navabi","doi":"10.1109/EWDTS.2011.6116571","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116571","url":null,"abstract":"The number of memory components in today's chips is increasing considerably. Through the limitations on area and number of test pins, it is not feasible to use a separate BIST architecture for testing every memory on the chip. Therefore, it is essential to have a configurable BIST architecture. In this paper, a configurable memory BIST architecture that can test different memories having different sizes and configurations with an arbitrary test algorithm is proposed.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114305910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116580
Denis Muratov, V. Boykov, Yuri Iskiv, Igor Smirnov, V. Vertegel, S. Berdyshev, Y. Gimpilevich, Gilad Keren
The following article describes a new ASIC hardware platform (MX76k), which will be used to launch current audio enhancement algorithms from Waves Audio (MaxxAudio 3) on a variety of consumer electronics devices. This platform can also be extended for usage in other audio applications.
{"title":"High performance audio processing SoC platform","authors":"Denis Muratov, V. Boykov, Yuri Iskiv, Igor Smirnov, V. Vertegel, S. Berdyshev, Y. Gimpilevich, Gilad Keren","doi":"10.1109/EWDTS.2011.6116580","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116580","url":null,"abstract":"The following article describes a new ASIC hardware platform (MX76k), which will be used to launch current audio enhancement algorithms from Waves Audio (MaxxAudio 3) on a variety of consumer electronics devices. This platform can also be extended for usage in other audio applications.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"298 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116592607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116424
Tarun Kumar Goyal, Amarpal Singh, R. Aggarwal
Design for Test (DFT) introduces certain elements such as buffers, inverter-pairs etc, though inconsequential, are integral part of a digital design. However, while debugging a circuit schematically, they waste precious real estate when a designer is mostly interested in the logical design elements. At the same time, it is important that these inconsequential elements are not discarded altogether as they could play an important role in the DFT debugging process such as buffer at pin output that fans out to multiple gates preserving the pin's hierarchical information when a design is flattened into primitives. This paper presents a novel approach that allows a designer to efficiently compact/un-compact inconsequential design components both completely/selectively in the design schematic, thus aiding the structural debugging process.
{"title":"Efficient selective compaction and un-compaction of inconsequential logical design units in the schematic representation of a design","authors":"Tarun Kumar Goyal, Amarpal Singh, R. Aggarwal","doi":"10.1109/EWDTS.2011.6116424","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116424","url":null,"abstract":"Design for Test (DFT) introduces certain elements such as buffers, inverter-pairs etc, though inconsequential, are integral part of a digital design. However, while debugging a circuit schematically, they waste precious real estate when a designer is mostly interested in the logical design elements. At the same time, it is important that these inconsequential elements are not discarded altogether as they could play an important role in the DFT debugging process such as buffer at pin output that fans out to multiple gates preserving the pin's hierarchical information when a design is flattened into primitives. This paper presents a novel approach that allows a designer to efficiently compact/un-compact inconsequential design components both completely/selectively in the design schematic, thus aiding the structural debugging process.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"2012 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114548969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116430
A. Barkalov, L. Titarenko, S. Chmielewski
The method of decrease in the number of PAL macrocells in logic circuit of Moore finite-state-machine (FSM) is proposed. Some peculiarities of Moore FSM such as existence of pseudoequivalent states and dependence of output functions on states as well as a wide fan-in of PAL macrocells are used to optimize the hardware amount (the number of PAL macrocells). It allows hardware amount decrease without decreasing in performance of the controlled digital system. The method is based on simultaneous application of optimal state assignment and transformation of the codes of pseudoequivalent states into codes of their classes. The proposed approach permits to decrease the hardware amount without decrease of digital system performance. An example of proposed method application is given, as well as the results of its investigation.
{"title":"Synthesis of control unit with refined state encoding for CPLD devices","authors":"A. Barkalov, L. Titarenko, S. Chmielewski","doi":"10.1109/EWDTS.2011.6116430","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116430","url":null,"abstract":"The method of decrease in the number of PAL macrocells in logic circuit of Moore finite-state-machine (FSM) is proposed. Some peculiarities of Moore FSM such as existence of pseudoequivalent states and dependence of output functions on states as well as a wide fan-in of PAL macrocells are used to optimize the hardware amount (the number of PAL macrocells). It allows hardware amount decrease without decreasing in performance of the controlled digital system. The method is based on simultaneous application of optimal state assignment and transformation of the codes of pseudoequivalent states into codes of their classes. The proposed approach permits to decrease the hardware amount without decrease of digital system performance. An example of proposed method application is given, as well as the results of its investigation.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129924667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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