Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116569
M. Almadi, Diaa Moamar, V. Ryabtsev
For synthesis of algorithms and tests programs of memory diagnosing a system of visualization of algorithms of the tests, containing a control device, a square matrix of memory cells and four heads of record/reading is offered. An example of synthesis by means of the given system of march_PS test. The reduction of labour input of design works is resulted provided at the expense of dynamic visualization of sequence of carried out diagnostic operations.
{"title":"New methods and tools for design of tests memory","authors":"M. Almadi, Diaa Moamar, V. Ryabtsev","doi":"10.1109/EWDTS.2011.6116569","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116569","url":null,"abstract":"For synthesis of algorithms and tests programs of memory diagnosing a system of visualization of algorithms of the tests, containing a control device, a square matrix of memory cells and four heads of record/reading is offered. An example of synthesis by means of the given system of march_PS test. The reduction of labour input of design works is resulted provided at the expense of dynamic visualization of sequence of carried out diagnostic operations.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117041237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116592
A. Zemliak, A. Michua, T. Markina
The problem of optimization of analog circuit for a minimal computer time has been formulated as the functional minimization problem of the control theory. The process of circuit optimization is formulated as the controllable dynamic system. The conception of the Lyapunov function was proposed to analyze the behavior of the process of circuit optimization. The special function that is a combination of the Lyapunov function and its time derivative was proposed to predict the design time of any strategy. This approach gives us the possibility to select the best strategy from the complete structural basis analyzing the initial part of the total optimization process only.
{"title":"Lyapunov function analysis for different strategies of circuit optimization","authors":"A. Zemliak, A. Michua, T. Markina","doi":"10.1109/EWDTS.2011.6116592","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116592","url":null,"abstract":"The problem of optimization of analog circuit for a minimal computer time has been formulated as the functional minimization problem of the control theory. The process of circuit optimization is formulated as the controllable dynamic system. The conception of the Lyapunov function was proposed to analyze the behavior of the process of circuit optimization. The special function that is a combination of the Lyapunov function and its time derivative was proposed to predict the design time of any strategy. This approach gives us the possibility to select the best strategy from the complete structural basis analyzing the initial part of the total optimization process only.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130143500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116413
A. Matrosova, Alexey Melnikov, Ruslan Mukhamedov, Virendra Singh
Structural scan based delay testing is used to detect delay faults. Because of the architectural limitations not each test pair v1, v2 can be applied by scan delay testing. That declines test coverage. Partial enhanced scan approach based on selection of flip-flops was suggested to permit using arbitrary test pairs v1, v2. The problem of selection of flip-flops may be solved with applying estimations of controllability and observability of the state variables corresponding to the flip-flops. Calculation of controllability and observability estimations is based on 2-length combinational equivalent analyses and PDF testing.
{"title":"Selection of the state variables for partial enhanced scan techniques","authors":"A. Matrosova, Alexey Melnikov, Ruslan Mukhamedov, Virendra Singh","doi":"10.1109/EWDTS.2011.6116413","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116413","url":null,"abstract":"Structural scan based delay testing is used to detect delay faults. Because of the architectural limitations not each test pair v1, v2 can be applied by scan delay testing. That declines test coverage. Partial enhanced scan approach based on selection of flip-flops was suggested to permit using arbitrary test pairs v1, v2. The problem of selection of flip-flops may be solved with applying estimations of controllability and observability of the state variables corresponding to the flip-flops. Calculation of controllability and observability estimations is based on 2-length combinational equivalent analyses and PDF testing.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122207619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116410
G. Mois, M. Hulea, S. Folea, L. Miclea
This paper presents a solution for the Wi-Fi reconfiguration of FPGAs. A design that manages the reconfiguration process of a Xilinx Spartan-3 FPGA by using a Wi-Fi Tag4M device that receives reconfiguration data wirelessly from a Configuration Server was developed. This research is especially important for adding self-healing capabilities to large and complex digital systems.
{"title":"Self-healing capabilities through wireless reconfiguration of FPGAs","authors":"G. Mois, M. Hulea, S. Folea, L. Miclea","doi":"10.1109/EWDTS.2011.6116410","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116410","url":null,"abstract":"This paper presents a solution for the Wi-Fi reconfiguration of FPGAs. A design that manages the reconfiguration process of a Xilinx Spartan-3 FPGA by using a Wi-Fi Tag4M device that receives reconfiguration data wirelessly from a Configuration Server was developed. This research is especially important for adding self-healing capabilities to large and complex digital systems.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128501331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116430
A. Barkalov, L. Titarenko, S. Chmielewski
The method of decrease in the number of PAL macrocells in logic circuit of Moore finite-state-machine (FSM) is proposed. Some peculiarities of Moore FSM such as existence of pseudoequivalent states and dependence of output functions on states as well as a wide fan-in of PAL macrocells are used to optimize the hardware amount (the number of PAL macrocells). It allows hardware amount decrease without decreasing in performance of the controlled digital system. The method is based on simultaneous application of optimal state assignment and transformation of the codes of pseudoequivalent states into codes of their classes. The proposed approach permits to decrease the hardware amount without decrease of digital system performance. An example of proposed method application is given, as well as the results of its investigation.
{"title":"Synthesis of control unit with refined state encoding for CPLD devices","authors":"A. Barkalov, L. Titarenko, S. Chmielewski","doi":"10.1109/EWDTS.2011.6116430","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116430","url":null,"abstract":"The method of decrease in the number of PAL macrocells in logic circuit of Moore finite-state-machine (FSM) is proposed. Some peculiarities of Moore FSM such as existence of pseudoequivalent states and dependence of output functions on states as well as a wide fan-in of PAL macrocells are used to optimize the hardware amount (the number of PAL macrocells). It allows hardware amount decrease without decreasing in performance of the controlled digital system. The method is based on simultaneous application of optimal state assignment and transformation of the codes of pseudoequivalent states into codes of their classes. The proposed approach permits to decrease the hardware amount without decrease of digital system performance. An example of proposed method application is given, as well as the results of its investigation.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129924667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116594
T. Mohamadi
one of the most important industrial computers' bus is Industry Standard Architecture (ISA) gap. At lost ISA could communicate with 8 bits data but nowadays it can communicate with much data bits. Only 8 bits has been used in this article, because the data are in one-byte formats. With ISA gap of the computer an interface circuit could be designed between computer and systems such as temperature control system. For this work, first an address is given to the system, and then circuit communicates with that system by means of an address and a data decoder. In this paper a system has been designed that can be used in every industrial work, because it has enough input and output (I/O) pins for most of systems. After introducing ISA slot main design has been presented. This circuit can be used in each kind of industrial work that interfaces with computer, DC, AC and Stepper motor controls and serial interface with computer.
{"title":"Designing ISA card with easy interface","authors":"T. Mohamadi","doi":"10.1109/EWDTS.2011.6116594","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116594","url":null,"abstract":"one of the most important industrial computers' bus is Industry Standard Architecture (ISA) gap. At lost ISA could communicate with 8 bits data but nowadays it can communicate with much data bits. Only 8 bits has been used in this article, because the data are in one-byte formats. With ISA gap of the computer an interface circuit could be designed between computer and systems such as temperature control system. For this work, first an address is given to the system, and then circuit communicates with that system by means of an address and a data decoder. In this paper a system has been designed that can be used in every industrial work, because it has enough input and output (I/O) pins for most of systems. After introducing ISA slot main design has been presented. This circuit can be used in each kind of industrial work that interfaces with computer, DC, AC and Stepper motor controls and serial interface with computer.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126045297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116572
Vazgen Melikyan, A. Durgaryan
In this paper a programmable highly linear voltage-to-current conversion technique for low noise, wide tunable frequency range voltage controlled oscillator (VCO) is presented. The effect of VCO gain on phase locked loop (PLL) phase noise and frequency stability characteristics is addressed. The proposed solution offers digital calibration of VCO gain and frequency, using binary weighted thick oxide MOS devices. Results of simulations in deep submicron CMOS technology are presented and discussed.
{"title":"Programmable current biasing for low noise voltage controlled oscillators","authors":"Vazgen Melikyan, A. Durgaryan","doi":"10.1109/EWDTS.2011.6116572","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116572","url":null,"abstract":"In this paper a programmable highly linear voltage-to-current conversion technique for low noise, wide tunable frequency range voltage controlled oscillator (VCO) is presented. The effect of VCO gain on phase locked loop (PLL) phase noise and frequency stability characteristics is addressed. The proposed solution offers digital calibration of VCO gain and frequency, using binary weighted thick oxide MOS devices. Results of simulations in deep submicron CMOS technology are presented and discussed.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"8 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132708156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116427
Kirill A. Sorudeykin
Trying to be effective (no matter who exactly and in what field) a person face the problem which inevitably destroys all our attempts to easily get to a desired goal. The problem is the existence of some insuperable barriers for our mind, another words barriers for principles of thinking. They are our clue and main reason for research. Here we investigate these barriers and their features exposing the nature of mental process. We start from special structures which reflect the ways to define relations between objects. Then we came to realizing about what is the material our mind uses to build thoughts, to make conclusions, to understand, to form reasoning, etc. This can be called a mental dynamics. After this the nature of mental barriers on the required level of abstraction as well as the ways to pass through them became clear. We begin to understand why thinking flows in such a way, with such specifics and with such limitations we can observe in reality. This can help us to be more optimal. At the final step we start to understand, what mathematical models can be applied to such a picture. We start to express our thoughts in a language of mathematics, developing an apparatus for our Spatial Theory of Mind, suitable to represent processes and infrastructure of thinking. We use abstract algebra and stay invariant in relation to the nature of objects.
{"title":"A model of spatial thinking for computational intelligence","authors":"Kirill A. Sorudeykin","doi":"10.1109/EWDTS.2011.6116427","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116427","url":null,"abstract":"Trying to be effective (no matter who exactly and in what field) a person face the problem which inevitably destroys all our attempts to easily get to a desired goal. The problem is the existence of some insuperable barriers for our mind, another words barriers for principles of thinking. They are our clue and main reason for research. Here we investigate these barriers and their features exposing the nature of mental process. We start from special structures which reflect the ways to define relations between objects. Then we came to realizing about what is the material our mind uses to build thoughts, to make conclusions, to understand, to form reasoning, etc. This can be called a mental dynamics. After this the nature of mental barriers on the required level of abstraction as well as the ways to pass through them became clear. We begin to understand why thinking flows in such a way, with such specifics and with such limitations we can observe in reality. This can help us to be more optimal. At the final step we start to understand, what mathematical models can be applied to such a picture. We start to express our thoughts in a language of mathematics, developing an apparatus for our Spatial Theory of Mind, suitable to represent processes and infrastructure of thinking. We use abstract algebra and stay invariant in relation to the nature of objects.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133510015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116591
D. Velychko, Y. I. Vdovychenko
This paper presents a calculation of a digital filter for the retransmission meter, rejecting parasitic signal spectrum components appeared during transformation in the retransmitter. FPGA programmed in VHDL is being used in the filter.
{"title":"A calculation of parasitic signal components digital filtration for the retransmission meter on the basis of FPGA","authors":"D. Velychko, Y. I. Vdovychenko","doi":"10.1109/EWDTS.2011.6116591","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116591","url":null,"abstract":"This paper presents a calculation of a digital filter for the retransmission meter, rejecting parasitic signal spectrum components appeared during transformation in the retransmitter. FPGA programmed in VHDL is being used in the filter.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129752237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-09DOI: 10.1109/EWDTS.2011.6116573
A. Barkalov, L. Titarenko, Lukasz Smolinski
The method of hardware reduction is proposed which is oriented on compositional microprogram control units with code sharing and PAL-based CPLD chips. The method is based on a wide fan-in of PAL macrocells allowing using more than one source for codes of operational linear chains. An example of the proposed method application is given.
{"title":"Optimization of microprogram control unit with code sharing","authors":"A. Barkalov, L. Titarenko, Lukasz Smolinski","doi":"10.1109/EWDTS.2011.6116573","DOIUrl":"https://doi.org/10.1109/EWDTS.2011.6116573","url":null,"abstract":"The method of hardware reduction is proposed which is oriented on compositional microprogram control units with code sharing and PAL-based CPLD chips. The method is based on a wide fan-in of PAL macrocells allowing using more than one source for codes of operational linear chains. An example of the proposed method application is given.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130761329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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