Pub Date : 2014-04-28DOI: 10.33899/RENGJ.2014.87338
R. A. Khalil, M. Salim
Most of the traditional digital implemented systems uses fixed point or floating point for representing and processing data. An alternative approach is to represent data as random bits that are distributed along the sequence . To be precise, stochastic logic can be considered as a solution for hardware size for application that consume physical area like neural networks as it uses logic gates to implement complex operations and its inherits resistance to bit flips noise. To avoid some of the problems that this type of processing suffers from, a combination of stochastic logic and classical logic (fixed point) is used to implement a neural networks (Fully connected feed-forwards) that is characterized by FPGA large size consuming. The stochastic logic is utilized have to implement part of the multiplication operations in the hidden layers of network and LFSR is used as a random generator forconversion of weights and activation functions outputs. The hardware utilization of Spartan 3E-500K FPGA results are compared with another network of the same size. A discussion of some of the issues that related to this methodology faces is also presented. Key words: Artificial neural networks, LFSR, Probabilistic computation, Stochastic arithmetic, FPGA, Stochastic logic.
{"title":"Enhanced Hardware Implementation of Hybrid Stochastic Neural Network using FPGA","authors":"R. A. Khalil, M. Salim","doi":"10.33899/RENGJ.2014.87338","DOIUrl":"https://doi.org/10.33899/RENGJ.2014.87338","url":null,"abstract":"Most of the traditional digital implemented systems uses fixed point or floating point for representing and processing data. An alternative approach is to represent data as random bits that are distributed along the sequence . To be precise, stochastic logic can be considered as a solution for hardware size for application that consume physical area like neural networks as it uses logic gates to implement complex operations and its inherits resistance to bit flips noise. To avoid some of the problems that this type of processing suffers from, a combination of stochastic logic and classical logic (fixed point) is used to implement a neural networks (Fully connected feed-forwards) that is characterized by FPGA large size consuming. The stochastic logic is utilized have to implement part of the multiplication operations in the hidden layers of network and LFSR is used as a random generator forconversion of weights and activation functions outputs. The hardware utilization of Spartan 3E-500K FPGA results are compared with another network of the same size. A discussion of some of the issues that related to this methodology faces is also presented. Key words: Artificial neural networks, LFSR, Probabilistic computation, Stochastic arithmetic, FPGA, Stochastic logic.","PeriodicalId":339890,"journal":{"name":"AL Rafdain Engineering Journal","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115835477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.33899/RENGJ.2014.87323
J. Abdul-Jabbar, Z. Al-Mokhtar
In this paper, an FPGA implementation of a 2-dimenional discrete wavelet transform (2-D DWT) is proposed to efficiently construct the corresponding two-dimensional architecture by using the raster-scan image method for any given hardware architecture of one dimensional (1-D) wavelet transform filter. The proposed method is based on lifting scheme architecture. The resulting architectures are simple, modular and regular for computation of one or multilevel 2-D DWT. These architectures perform both low pass and high pass filter with multiplierless coefficients calculation. In addition they require a small on-chip area to download the architectures on FPGA Board (Spartan-3E). The proposed 2-D architecture consists of: external memory, Row 1-D arithmetic module, column 1-D arithmetic module and internal memory unit. The row and column 1-D arithmetic units are designed utilizing Biorthogonal filters (5/3 and 9/7). Keywords: 2-D DWT, FPGA implementation, Lifting scheme architecture, Raster-scan method .
{"title":"Design and FPGA Implementation of Two-Dimensional Discrete Wavelet Transform Architectures Using Raster-Scan Method","authors":"J. Abdul-Jabbar, Z. Al-Mokhtar","doi":"10.33899/RENGJ.2014.87323","DOIUrl":"https://doi.org/10.33899/RENGJ.2014.87323","url":null,"abstract":"In this paper, an FPGA implementation of a 2-dimenional discrete wavelet transform (2-D DWT) is proposed to efficiently construct the corresponding two-dimensional architecture by using the raster-scan image method for any given hardware architecture of one dimensional (1-D) wavelet transform filter. The proposed method is based on lifting scheme architecture. The resulting architectures are simple, modular and regular for computation of one or multilevel 2-D DWT. These architectures perform both low pass and high pass filter with multiplierless coefficients calculation. In addition they require a small on-chip area to download the architectures on FPGA Board (Spartan-3E). The proposed 2-D architecture consists of: external memory, Row 1-D arithmetic module, column 1-D arithmetic module and internal memory unit. The row and column 1-D arithmetic units are designed utilizing Biorthogonal filters (5/3 and 9/7). Keywords: 2-D DWT, FPGA implementation, Lifting scheme architecture, Raster-scan method .","PeriodicalId":339890,"journal":{"name":"AL Rafdain Engineering Journal","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128209388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.33899/rengj.2014.87317
Q. Ali, Alnawars Mohammed
In this paper, a neuro-based predictor is proposed with a prediction algorithm to estimate the required number of active servers simulating the Green Networking objectives. The inputs of such predictor are the CPU utilization of the servers in the data center and the variations of the incoming demands with the number of users’ variation. During the work, different demand profiles of ClarkNet traffic traces are simulated on OPNET14.5 Modeler to obtain the required training values of servers’ CPU utilization and clients’ throughput. Also, Green Networking objectives are defined to maintain the Power Management Criteria (PMC) which guaranteed that all CPU utilization must be greater than 30%. Taking into account that a maximum number of 100 servers are used in such local data center, an ON/OFF control algorithm is then suggested for the power management of different servers in data center to fulfill the previous Green objectives. The Power saving is finally evaluated since it has been noticed that the power saving percentage can be increased from 17.33% to 85.33% of a total power of 75 k watts when the number of the operating servers is decreased from 80% to 5% of the overall servers.
{"title":"Optimization of Power Consumption in Cloud Data Centers Using Green Networking Techniques","authors":"Q. Ali, Alnawars Mohammed","doi":"10.33899/rengj.2014.87317","DOIUrl":"https://doi.org/10.33899/rengj.2014.87317","url":null,"abstract":"In this paper, a neuro-based predictor is proposed with a prediction algorithm to estimate the required number of active servers simulating the Green Networking objectives. The inputs of such predictor are the CPU utilization of the servers in the data center and the variations of the incoming demands with the number of users’ variation. During the work, different demand profiles of ClarkNet traffic traces are simulated on OPNET14.5 Modeler to obtain the required training values of servers’ CPU utilization and clients’ throughput. Also, Green Networking objectives are defined to maintain the Power Management Criteria (PMC) which guaranteed that all CPU utilization must be greater than 30%. Taking into account that a maximum number of 100 servers are used in such local data center, an ON/OFF control algorithm is then suggested for the power management of different servers in data center to fulfill the previous Green objectives. The Power saving is finally evaluated since it has been noticed that the power saving percentage can be increased from 17.33% to 85.33% of a total power of 75 k watts when the number of the operating servers is decreased from 80% to 5% of the overall servers.","PeriodicalId":339890,"journal":{"name":"AL Rafdain Engineering Journal","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122827142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.33899/rengj.2014.87322
B. S. Mahmood, Sarmad F. Ismael
The architectural design of the random number generators for uniform distribution, normal distribution, exponential distribution and Rayleigh distribution using Box-Muller and inverse transformation method has been hardware implemented on FPGA. Any of the random number generators can generate one sample every clock cycle. The generators have been implemented on Xilinx Spartan 3E XC3S500E FPGA. The designed generators work properly up to maximum frequency of 418.41MHz .The outcome results of the generators have been tested by the chi-square test at a 5% level of significance which provided the correct required distributions. Keyword: Box-mulle, Chi-square, Inverse transformation, FPGA. ةيئاوشعلا ماقرلاا ديلوتل ةيرامعم ميمصت ايدام اهذيفنتو ليعامسإ نيدلا رخف دمرس .د دومحم ركش لساب بوساحلا ةسدنه مسق / لصوملا ةعماج تاينورتكللأأ ةسدنه ةيلك صخلملا ا ديلوتل ةممصملا ةيرامعملا و يعيبط عيزوتو مظتنم عيزوتب ةيئاوشعلا ماقرلا عيزوتو يسا عيزوت لا ةقيرط مادختساب ) يليار( ـ ( Box-muller لا مادختساب ايدام اهءانب مت يسكعلا ليوحتلا ةقيرطو ) FPGA . ىلع اهءانب مت تادلوملا .ةرود لك يف دحاو مقر دلوت نا نكمم ةيئاوشعلا ماقرلاا تادلوم نم دحاو يا Xilinx Spartan 3E XC3S500E FPGA . هرادقم ددرتب لمعلل ةبسانم ةممصملا تادلوملا 418.41MHz ىوتسمب ياك عبرم صحف ةطساوب اهرابتخا مت تادلوملا نم اهيلع لوصحلا مت يتلا جئاتنلا ةيمها اهرادقم 5 .بولطملا عيزوتلا تققح يتلاو % Received: 9 – 5 2013 Accepted: 10 – 10 2013 Al-Rafidain Engineering Vol.22 No. 2 March 2014 51
{"title":"Architectural Design of Random Number Generators and Their Hardware Implementations","authors":"B. S. Mahmood, Sarmad F. Ismael","doi":"10.33899/rengj.2014.87322","DOIUrl":"https://doi.org/10.33899/rengj.2014.87322","url":null,"abstract":"The architectural design of the random number generators for uniform distribution, normal distribution, exponential distribution and Rayleigh distribution using Box-Muller and inverse transformation method has been hardware implemented on FPGA. Any of the random number generators can generate one sample every clock cycle. The generators have been implemented on Xilinx Spartan 3E XC3S500E FPGA. The designed generators work properly up to maximum frequency of 418.41MHz .The outcome results of the generators have been tested by the chi-square test at a 5% level of significance which provided the correct required distributions. Keyword: Box-mulle, Chi-square, Inverse transformation, FPGA. ةيئاوشعلا ماقرلاا ديلوتل ةيرامعم ميمصت ايدام اهذيفنتو ليعامسإ نيدلا رخف دمرس .د دومحم ركش لساب بوساحلا ةسدنه مسق / لصوملا ةعماج تاينورتكللأأ ةسدنه ةيلك صخلملا ا ديلوتل ةممصملا ةيرامعملا و يعيبط عيزوتو مظتنم عيزوتب ةيئاوشعلا ماقرلا عيزوتو يسا عيزوت لا ةقيرط مادختساب ) يليار( ـ ( Box-muller لا مادختساب ايدام اهءانب مت يسكعلا ليوحتلا ةقيرطو ) FPGA . ىلع اهءانب مت تادلوملا .ةرود لك يف دحاو مقر دلوت نا نكمم ةيئاوشعلا ماقرلاا تادلوم نم دحاو يا Xilinx Spartan 3E XC3S500E FPGA . هرادقم ددرتب لمعلل ةبسانم ةممصملا تادلوملا 418.41MHz ىوتسمب ياك عبرم صحف ةطساوب اهرابتخا مت تادلوملا نم اهيلع لوصحلا مت يتلا جئاتنلا ةيمها اهرادقم 5 .بولطملا عيزوتلا تققح يتلاو % Received: 9 – 5 2013 Accepted: 10 – 10 2013 Al-Rafidain Engineering Vol.22 No. 2 March 2014 51","PeriodicalId":339890,"journal":{"name":"AL Rafdain Engineering Journal","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126464151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.33899/RENGJ.2014.87312
Talaat I. M. Al-Aane
{"title":"The Attributes of Architectural Form of Traditional House Internal Facades of Mosul's Traditional House as a Case-study","authors":"Talaat I. M. Al-Aane","doi":"10.33899/RENGJ.2014.87312","DOIUrl":"https://doi.org/10.33899/RENGJ.2014.87312","url":null,"abstract":"","PeriodicalId":339890,"journal":{"name":"AL Rafdain Engineering Journal","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114600271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.33899/RENGJ.2014.87334
Ayman A. Abdul-Mawjoud, Gandhi G. Sofia
Passing on rural two-lane highways is one of the most important driving tasks. More than 28000 vehicles were observed and the passing maneuvers were recorded of 10 two-lane highways in northern Iraq during June and July months of 2005. It was found that the number of passing maneuver increase as the flow rate for both directions increase up to 1500 veh/hr flow rate. The passing maneuvers decreases with the increase in flow rate. The increase in flow rate causes an increase in demand of passing and decrease in passing supply. Volume of around 212 veh/hr gives a balance between demand of passing and passing supply.
{"title":"Passing Behavior on Rural Two-Lane Highways","authors":"Ayman A. Abdul-Mawjoud, Gandhi G. Sofia","doi":"10.33899/RENGJ.2014.87334","DOIUrl":"https://doi.org/10.33899/RENGJ.2014.87334","url":null,"abstract":"Passing on rural two-lane highways is one of the most important driving tasks. More than 28000 vehicles were observed and the passing maneuvers were recorded of 10 two-lane highways in northern Iraq during June and July months of 2005. It was found that the number of passing maneuver increase as the flow rate for both directions increase up to 1500 veh/hr flow rate. The passing maneuvers decreases with the increase in flow rate. The increase in flow rate causes an increase in demand of passing and decrease in passing supply. Volume of around 212 veh/hr gives a balance between demand of passing and passing supply.","PeriodicalId":339890,"journal":{"name":"AL Rafdain Engineering Journal","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129949246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.33899/RENGJ.2014.87333
M. Al-Layla, Dr.Qutayba Nazar Al-Saffar
The aim of this study is to improve the engineering properties of gypseous soils, located in Bajii city (160 km South of Mosul city) using the Field Dynamic Compaction (FDC) techniques. This technique consist of dropping a reinforced concrete block (1x1x1 m) weighing (2.4 Tons) from different heights on a gypseous soil of thickness varaing from (0.5-2.4 m) and underlain by sub-base material. The effect of FDC on the gypseous soil was investigated using SPT in the field and using the conventional laboratory apparatus in the laboratory tests. The results showed that the unit weight increased (14-32%) for one drop of the weight. The effective angle of internal friction (ϕˉ ) increased from (32 o ) to about (36 o ) while the compression index (Cc) decreased from (0.24) to about (0.07-0.1). The results of this study indicated that about (60-80 %) of the improvement was achieved from the first blow in loose to meduime soils. However about (25 %) of the improvement was reached in dense soils. The FDC is a promising technique for improving the engineering properties of gypseous soil and overcome most of the gypseous soil problems. Key words: Dynamic compaction , Gypseous soil, Soil Improving and SPT-Test
{"title":"Improving The Engineering Properties of The Gypseous Soil Using Dynamic Compaction Method","authors":"M. Al-Layla, Dr.Qutayba Nazar Al-Saffar","doi":"10.33899/RENGJ.2014.87333","DOIUrl":"https://doi.org/10.33899/RENGJ.2014.87333","url":null,"abstract":"The aim of this study is to improve the engineering properties of gypseous soils, located in Bajii city (160 km South of Mosul city) using the Field Dynamic Compaction (FDC) techniques. This technique consist of dropping a reinforced concrete block (1x1x1 m) weighing (2.4 Tons) from different heights on a gypseous soil of thickness varaing from (0.5-2.4 m) and underlain by sub-base material. The effect of FDC on the gypseous soil was investigated using SPT in the field and using the conventional laboratory apparatus in the laboratory tests. The results showed that the unit weight increased (14-32%) for one drop of the weight. The effective angle of internal friction (ϕˉ ) increased from (32 o ) to about (36 o ) while the compression index (Cc) decreased from (0.24) to about (0.07-0.1). The results of this study indicated that about (60-80 %) of the improvement was achieved from the first blow in loose to meduime soils. However about (25 %) of the improvement was reached in dense soils. The FDC is a promising technique for improving the engineering properties of gypseous soil and overcome most of the gypseous soil problems. Key words: Dynamic compaction , Gypseous soil, Soil Improving and SPT-Test","PeriodicalId":339890,"journal":{"name":"AL Rafdain Engineering Journal","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121855752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.33899/RENGJ.2014.87319
M. F. Al-kababjie, Nuaimy, Dhafer. A . Al, Nuaimy Dhafer. A . Al
The normal distance relay face many challenges in a series compensated transmission lines the distance relay may give incorrect decision. This paper present a digital distance relay designed by using wavelet transform (WT) to work with this compensated transmission lines. The relay have another features to recognize between fault and disturbance cases , classify fault types and giving the trip signal to circuit breaker in a time less than period quarter. The relay has been tested for both simulation cases and practically cases by simulation transmission lines board in the lab. Index Terms: Distance relay , fault detection , Series-Compensated Lines Protect ion, wavelet transform, MOV
{"title":"Enhancement of Distance Relay Performance in Transmission Line Compensated by Series Capacitor Protected by MOV","authors":"M. F. Al-kababjie, Nuaimy, Dhafer. A . Al, Nuaimy Dhafer. A . Al","doi":"10.33899/RENGJ.2014.87319","DOIUrl":"https://doi.org/10.33899/RENGJ.2014.87319","url":null,"abstract":"The normal distance relay face many challenges in a series compensated transmission lines the distance relay may give incorrect decision. This paper present a digital distance relay designed by using wavelet transform (WT) to work with this compensated transmission lines. The relay have another features to recognize between fault and disturbance cases , classify fault types and giving the trip signal to circuit breaker in a time less than period quarter. The relay has been tested for both simulation cases and practically cases by simulation transmission lines board in the lab. Index Terms: Distance relay , fault detection , Series-Compensated Lines Protect ion, wavelet transform, MOV","PeriodicalId":339890,"journal":{"name":"AL Rafdain Engineering Journal","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121869254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-02-28DOI: 10.33899/rengj.2014.87017
M. Jaber, Azal Refa, Alaa Dahham
{"title":"Finite Element Analysis of Draw Beads in Deep Drawing Processes","authors":"M. Jaber, Azal Refa, Alaa Dahham","doi":"10.33899/rengj.2014.87017","DOIUrl":"https://doi.org/10.33899/rengj.2014.87017","url":null,"abstract":"","PeriodicalId":339890,"journal":{"name":"AL Rafdain Engineering Journal","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115709334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-02-28DOI: 10.33899/rengj.2014.86994
Abdul Jabbar, Z. Farej, Dr. A. I. A. Jabbar
Multiple access interferences are the major limiting factors for the performance of multihop WiMAX based Mesh Network (WMN). The routing algorithms play an important role in reducing such interferences among the nodes of the WMN. In this paper a new Routing Tree Construction Algorithm (RTCA) which is based on Balancing the data and Parallelizing the routes of the data from nodes to BS is proposed and called BalancedParalleled RTCA (Bala-Para-RTCA). This algorithm has a new Down-Node Group Testing (DNGT) feature. This feature increases the conversion of primary into secondary interferences which (in conjunction with directivity) can be avoided significantly by the Modified Fair Relay Centralized Scheduling (MFRCS) algorithm, as a result concurrent transmissions over a certain slot will be increased. So system performance is enhanced in terms of scheduling length, links concurrency ratio (LCR) and average transmission delay (ATD). Without directivity and relative to the standard Breadth First Tree (BFT) RTCA, the simulation results of the proposed RTCA show concurrency ratio enhancement of 15.38% and 19.4% without and with DNGT respectively.
{"title":"WiMAX Mesh Topology with Modified Fair Centralized Scheduling and Routing Algorithms Based on Testing Feature of Down-Node Group","authors":"Abdul Jabbar, Z. Farej, Dr. A. I. A. Jabbar","doi":"10.33899/rengj.2014.86994","DOIUrl":"https://doi.org/10.33899/rengj.2014.86994","url":null,"abstract":"Multiple access interferences are the major limiting factors for the performance of multihop WiMAX based Mesh Network (WMN). The routing algorithms play an important role in reducing such interferences among the nodes of the WMN. In this paper a new Routing Tree Construction Algorithm (RTCA) which is based on Balancing the data and Parallelizing the routes of the data from nodes to BS is proposed and called BalancedParalleled RTCA (Bala-Para-RTCA). This algorithm has a new Down-Node Group Testing (DNGT) feature. This feature increases the conversion of primary into secondary interferences which (in conjunction with directivity) can be avoided significantly by the Modified Fair Relay Centralized Scheduling (MFRCS) algorithm, as a result concurrent transmissions over a certain slot will be increased. So system performance is enhanced in terms of scheduling length, links concurrency ratio (LCR) and average transmission delay (ATD). Without directivity and relative to the standard Breadth First Tree (BFT) RTCA, the simulation results of the proposed RTCA show concurrency ratio enhancement of 15.38% and 19.4% without and with DNGT respectively.","PeriodicalId":339890,"journal":{"name":"AL Rafdain Engineering Journal","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130141310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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