This paper presents measurements of the number of thermal cycles to failure for eutectic solder bumps in flip-chip-on-board (FCOB) circuits with and without underfill. The bump lifetime is measured as a function of the distance to the chip centre for two different underfill materials. The results show that the lifetime of the solder bumps under thermal cycling from -55-145/spl deg/C decreases with increasing thermal expansion coefficient (CTE) of the underfill material. For a filled epoxy underfill with CTE=28 ppm/K, nearly matched to the CTE of solder, the measurements so far indicate that the number of cycles to failure is around 2000, compared to 50-80 cycles for devices without underfill. For a pure epoxy underfill (CTE=58 ppm/K) the measured lifetime of the solder bumps is 400-500 cycles. The lifetime measurements are compared to an analytical model of the number of cycles to failure based on calculations of axial and shear solder strain. For devices without underfill and with the underfill with the highest CTE, the measured number of cycles to failure are around 50% higher than predicted by the model. For the underfill with the lowest CTE, preliminary results indicate that the lifetime is close to or slightly higher than the predicted values. For both samples, there is only a small variation of lifetime with the distance to the chip centre. This indicates that axial strain plays a dominant role in the mechanical wearout of the solder bumps.
{"title":"Measurements of solder bump lifetime as a function of underfill material properties","authors":"J. Nysaether, P. Lundstrom, J. Liu","doi":"10.1109/PEP.1997.656504","DOIUrl":"https://doi.org/10.1109/PEP.1997.656504","url":null,"abstract":"This paper presents measurements of the number of thermal cycles to failure for eutectic solder bumps in flip-chip-on-board (FCOB) circuits with and without underfill. The bump lifetime is measured as a function of the distance to the chip centre for two different underfill materials. The results show that the lifetime of the solder bumps under thermal cycling from -55-145/spl deg/C decreases with increasing thermal expansion coefficient (CTE) of the underfill material. For a filled epoxy underfill with CTE=28 ppm/K, nearly matched to the CTE of solder, the measurements so far indicate that the number of cycles to failure is around 2000, compared to 50-80 cycles for devices without underfill. For a pure epoxy underfill (CTE=58 ppm/K) the measured lifetime of the solder bumps is 400-500 cycles. The lifetime measurements are compared to an analytical model of the number of cycles to failure based on calculations of axial and shear solder strain. For devices without underfill and with the underfill with the highest CTE, the measured number of cycles to failure are around 50% higher than predicted by the model. For the underfill with the lowest CTE, preliminary results indicate that the lifetime is close to or slightly higher than the predicted values. For both samples, there is only a small variation of lifetime with the distance to the chip centre. This indicates that axial strain plays a dominant role in the mechanical wearout of the solder bumps.","PeriodicalId":340973,"journal":{"name":"Proceedings. The First IEEE International Symposium on Polymeric Electronics Packaging, PEP '97 (Cat. No.97TH8268)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127133560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Flip chip, ball grid array (BGA), and /spl mu/-BGA technology has been investigated by large and small European electronics companies, and the technology is already used in production by some. There are three major applications: (1) SMT compatible use of flip chip on printed boards; (2) flip chip technology for special applications where no other packaging can meet the requirements; (3) low cost flip chip technology. Assembly and bonding equipment is an important concern for all of these applications for the development of low-cost flip chip technology and bumping technology. However, the heavy cost of assembly and bonding equipment, and difficulties in finding systems which are flexible enough to cover the wide range of demands, are blocking the way for smaller, innovative companies. A modular flexible bonding workstation for a wide variety of flip chip applications is presented and explained in this paper. The workstation is based on a simple but very precise principle for optical face-down chip alignment. Special features realised as modular options enable this workstation to cover a wide range of different bonding processes with all parameters. The paper explains how to perform different bonding processes with the system.
{"title":"Equipment for placement and bonding","authors":"F. Rusander","doi":"10.1109/PEP.1997.656498","DOIUrl":"https://doi.org/10.1109/PEP.1997.656498","url":null,"abstract":"Flip chip, ball grid array (BGA), and /spl mu/-BGA technology has been investigated by large and small European electronics companies, and the technology is already used in production by some. There are three major applications: (1) SMT compatible use of flip chip on printed boards; (2) flip chip technology for special applications where no other packaging can meet the requirements; (3) low cost flip chip technology. Assembly and bonding equipment is an important concern for all of these applications for the development of low-cost flip chip technology and bumping technology. However, the heavy cost of assembly and bonding equipment, and difficulties in finding systems which are flexible enough to cover the wide range of demands, are blocking the way for smaller, innovative companies. A modular flexible bonding workstation for a wide variety of flip chip applications is presented and explained in this paper. The workstation is based on a simple but very precise principle for optical face-down chip alignment. Special features realised as modular options enable this workstation to cover a wide range of different bonding processes with all parameters. The paper explains how to perform different bonding processes with the system.","PeriodicalId":340973,"journal":{"name":"Proceedings. The First IEEE International Symposium on Polymeric Electronics Packaging, PEP '97 (Cat. No.97TH8268)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129849571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Ansorge, K. Becker, R. Ehrlich, G. Azdasht, V. Bader, R. Aschenbrenner, H. Reichl
During semiconductor industry development, almost the whole packaging segment has shifted to the far east. Only a few packagers remained in Europe, focused on large scale production. At the Fraunhofer IZM, Berlin, Germany, a plastic packaging line was designed for fast, flexible and qualified service in low scale packaging and prototyping. The line consists of an epoxy multi-chip die bonder, wire bonder, flip chip placement system, multi-plunger moulding system, laser marking/trimming station, lead forming and lead soldering. For solder ball placement of both flip chips and ball grid array (BGA) packages, a laser solder ball placer is used. This machine can place and simultaneously reflow solder balls of various materials and diameters. The IZM mould and assembly line was installed to offer small/medium sized production to industry. This center can also be used for package development. In this paper, recent applications such as mechatronics and combination of multichip flip chip processes on different carriers including encapsulation by moulding are demonstrated. For production of CSPs and tape-BGA, the fiber-push connection method was used as a key technology. All packages are subject to detailed reliability investigations. The paper focuses on the moisture sensitivity of underfill and moulding compounds. Results of accelerated aging tests and the failure mechanisms for chip scale packages and few-chip micro-BGAs are demonstrated. Improvements for processing conditions and material selection and design are discussed, in order to achieve packages with high reliability for harsh environmental conditions in automotive use.
{"title":"Recent progress in flexible moulding and reliability investigation of CSP and BGA-packages using advanced interconnection technology","authors":"F. Ansorge, K. Becker, R. Ehrlich, G. Azdasht, V. Bader, R. Aschenbrenner, H. Reichl","doi":"10.1109/PEP.1997.656468","DOIUrl":"https://doi.org/10.1109/PEP.1997.656468","url":null,"abstract":"During semiconductor industry development, almost the whole packaging segment has shifted to the far east. Only a few packagers remained in Europe, focused on large scale production. At the Fraunhofer IZM, Berlin, Germany, a plastic packaging line was designed for fast, flexible and qualified service in low scale packaging and prototyping. The line consists of an epoxy multi-chip die bonder, wire bonder, flip chip placement system, multi-plunger moulding system, laser marking/trimming station, lead forming and lead soldering. For solder ball placement of both flip chips and ball grid array (BGA) packages, a laser solder ball placer is used. This machine can place and simultaneously reflow solder balls of various materials and diameters. The IZM mould and assembly line was installed to offer small/medium sized production to industry. This center can also be used for package development. In this paper, recent applications such as mechatronics and combination of multichip flip chip processes on different carriers including encapsulation by moulding are demonstrated. For production of CSPs and tape-BGA, the fiber-push connection method was used as a key technology. All packages are subject to detailed reliability investigations. The paper focuses on the moisture sensitivity of underfill and moulding compounds. Results of accelerated aging tests and the failure mechanisms for chip scale packages and few-chip micro-BGAs are demonstrated. Improvements for processing conditions and material selection and design are discussed, in order to achieve packages with high reliability for harsh environmental conditions in automotive use.","PeriodicalId":340973,"journal":{"name":"Proceedings. The First IEEE International Symposium on Polymeric Electronics Packaging, PEP '97 (Cat. No.97TH8268)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131099190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
There is growing interest in using anisotropically conductive adhesives (ACAs) not only for interconnections between LCDs and PCBs but also in higher current contacts such as flip chip and rigid-flex interconnects, for example in automotive applications. 1/f noise measurements are a common diagnostic tool for investigation of chip metallization lifetime. Resistance fluctuations (which mean noise) are induced by electron mobility fluctuations due to, for example, scattering on moving atoms (electromigration). Another noise source is resistance fluctuations that are dominated by current constriction in a point contact. Both mechanisms play a role in ACA contacts. A technology to prepare anisotropically conductive interconnections with only a few conducting particles per contact to separate different failure mechanisms and to realize the noise measurements is presented. Samples are exposed to current, and noise is measured before and after these damaging processes. Measurements show that anisotropically conductive contacts exhibit a transition from mixed film/spot contact behaviour to film dominated contacts when the gap between the contact pads is increased, transgressing the diameter of the conducting particles. After current damaging, we find a noise spectrum consisting of a 1/f portion and an additional 1/f/sup 2/ component, which is relaxed during a following zero current period. The increase in noise power after damaging is significantly higher than the increase of resistance. The tests were carried out on FR-4 substrates with Cu traces and Ni/Au metallization. Adhesives were filled with Au particles.
{"title":"Characterization of anisotropically conductive adhesive interconnections by 1/f noise measurements","authors":"U. Behner, R. Haug, R. Schutz, H. Hartnagel","doi":"10.1109/PEP.1997.656496","DOIUrl":"https://doi.org/10.1109/PEP.1997.656496","url":null,"abstract":"There is growing interest in using anisotropically conductive adhesives (ACAs) not only for interconnections between LCDs and PCBs but also in higher current contacts such as flip chip and rigid-flex interconnects, for example in automotive applications. 1/f noise measurements are a common diagnostic tool for investigation of chip metallization lifetime. Resistance fluctuations (which mean noise) are induced by electron mobility fluctuations due to, for example, scattering on moving atoms (electromigration). Another noise source is resistance fluctuations that are dominated by current constriction in a point contact. Both mechanisms play a role in ACA contacts. A technology to prepare anisotropically conductive interconnections with only a few conducting particles per contact to separate different failure mechanisms and to realize the noise measurements is presented. Samples are exposed to current, and noise is measured before and after these damaging processes. Measurements show that anisotropically conductive contacts exhibit a transition from mixed film/spot contact behaviour to film dominated contacts when the gap between the contact pads is increased, transgressing the diameter of the conducting particles. After current damaging, we find a noise spectrum consisting of a 1/f portion and an additional 1/f/sup 2/ component, which is relaxed during a following zero current period. The increase in noise power after damaging is significantly higher than the increase of resistance. The tests were carried out on FR-4 substrates with Cu traces and Ni/Au metallization. Adhesives were filled with Au particles.","PeriodicalId":340973,"journal":{"name":"Proceedings. The First IEEE International Symposium on Polymeric Electronics Packaging, PEP '97 (Cat. No.97TH8268)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126632546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In the field of flat panel displays, packaging technology has a significant influence on display performance. The electrical interconnect between the LCD and the LCD driver circuit is an area that needs improvement to achieve finer pitch, easier assembly and greater connection reliability. For LCD driver packaging, the ideal assembly process would possess the following characteristics: low processing cost; reliability suitable to the final application; high-density, fine pitch capability; low product profile; acceptable joint resistance; ease of inspection; and reworkability. The overall trend in LCD driver IC packaging has been to move the driver IC closer to the LCD itself. At present, TAB is the predominant packaging approach for large area LCDs. In most cases, the TAB is directly connected to the ITO traces on the glass using anisotropic conductive adhesive (ACA). In chip-on-glass (COG) technology, the driver LSI chips have moved all the way on to the LCD glass itself. COG is typically done by flip chip, also often with the use of conductive adhesives. ITO traces fan out from the IC to the display area, as well as to the point where a polyimide flexible circuit is connected to the glass substrate to supply power and picture information. COG mounting is currently being used in a number of products, in particular when the pixel density is high.
{"title":"Overview of conductive adhesive interconnection technologies for LCD's","authors":"Helge Kristiansen, Johan Liu","doi":"10.1109/PEP.1997.656494","DOIUrl":"https://doi.org/10.1109/PEP.1997.656494","url":null,"abstract":"In the field of flat panel displays, packaging technology has a significant influence on display performance. The electrical interconnect between the LCD and the LCD driver circuit is an area that needs improvement to achieve finer pitch, easier assembly and greater connection reliability. For LCD driver packaging, the ideal assembly process would possess the following characteristics: low processing cost; reliability suitable to the final application; high-density, fine pitch capability; low product profile; acceptable joint resistance; ease of inspection; and reworkability. The overall trend in LCD driver IC packaging has been to move the driver IC closer to the LCD itself. At present, TAB is the predominant packaging approach for large area LCDs. In most cases, the TAB is directly connected to the ITO traces on the glass using anisotropic conductive adhesive (ACA). In chip-on-glass (COG) technology, the driver LSI chips have moved all the way on to the LCD glass itself. COG is typically done by flip chip, also often with the use of conductive adhesives. ITO traces fan out from the IC to the display area, as well as to the point where a polyimide flexible circuit is connected to the glass substrate to supply power and picture information. COG mounting is currently being used in a number of products, in particular when the pixel density is high.","PeriodicalId":340973,"journal":{"name":"Proceedings. The First IEEE International Symposium on Polymeric Electronics Packaging, PEP '97 (Cat. No.97TH8268)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114364189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Parametric analytical studies are conducted to investigate whether the reliability of flip chip solder interconnects are affected by underfill inhomogeneities, such as settling of the filler particles. The property gradation caused by filler settling is modelled with a micromechanical formulation. The predicted property gradients are then utilized in a finite element simulation of the flip chip assembly, to assess the impact on solder interconnect reliability.
{"title":"Impact of underfill filler particles on reliability of flip chip interconnects","authors":"K. Darbha, J. Okura, A. Dasgupta","doi":"10.1109/PEP.1997.656501","DOIUrl":"https://doi.org/10.1109/PEP.1997.656501","url":null,"abstract":"Parametric analytical studies are conducted to investigate whether the reliability of flip chip solder interconnects are affected by underfill inhomogeneities, such as settling of the filler particles. The property gradation caused by filler settling is modelled with a micromechanical formulation. The predicted property gradients are then utilized in a finite element simulation of the flip chip assembly, to assess the impact on solder interconnect reliability.","PeriodicalId":340973,"journal":{"name":"Proceedings. The First IEEE International Symposium on Polymeric Electronics Packaging, PEP '97 (Cat. No.97TH8268)","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114527100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Electronic equipment is becoming increasingly simple to operate, more compact and lighter in weight, with higher performance and multi-functional capabilities. Semiconductor devices used in this equipment are required to have an ultra-large scale of integration, with ultra-high circuit density on a submicron level and large 64 Mbit and 256 Mbit capacities. Based on composite technologies fostered through development of device structures, process technologies, and manufacturing equipment and materials, we are continuously creating excellent new products that are among the most advanced in the world, using such technologies as the recombination, composition and fusion of materials or raw materials. In this paper, we show trends in semiconductor devices and packaging technologies. We then introduce the relationship between these technologies and our commercial products in brief.
{"title":"Progress toward polymeric materials for electronic applications","authors":"S. Hayashida","doi":"10.1109/PEP.1997.656465","DOIUrl":"https://doi.org/10.1109/PEP.1997.656465","url":null,"abstract":"Electronic equipment is becoming increasingly simple to operate, more compact and lighter in weight, with higher performance and multi-functional capabilities. Semiconductor devices used in this equipment are required to have an ultra-large scale of integration, with ultra-high circuit density on a submicron level and large 64 Mbit and 256 Mbit capacities. Based on composite technologies fostered through development of device structures, process technologies, and manufacturing equipment and materials, we are continuously creating excellent new products that are among the most advanced in the world, using such technologies as the recombination, composition and fusion of materials or raw materials. In this paper, we show trends in semiconductor devices and packaging technologies. We then introduce the relationship between these technologies and our commercial products in brief.","PeriodicalId":340973,"journal":{"name":"Proceedings. The First IEEE International Symposium on Polymeric Electronics Packaging, PEP '97 (Cat. No.97TH8268)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117034687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Anisotropic conductive films (ACF) composed of an adhesive resin and fine conductive fillers such as metallic particles or metal-coated polymer balls are key materials for fine pitch chip-on-film (COF) and chip-on-glass (COG) LCD packaging. To understand and design better quality ACF materials, a conduction model with a physical contact mechanism was simulated and experimentally proved. To understand the contact area changes, two pressure dependent models - (1) elastic/plastic deformation and (2) FEM - were developed and proved by testing various ACFs. Experimental variables such as bonding pressure, and the number, size, mechanical and electrical properties of Ni powders and Au-coated polymer conductive particles were applied. The models agreed well with experimental results, except at higher bonding pressures. In general, as bonding pressure increases, sharp decrease in contact resistance followed by a constant value is observed after reaching a critical bonding pressure. However, excessive bonding pressure inversely increased the ACF connection resistance. If more conductive particles were added, the connection resistance rapidly decreased to a constant. This is the counter-effect of two opposing factors: resistance increase by decrease in contact area per particle and resistance decrease by increased conduction path numbers. Also, environmental effects on contact resistance and adhesion strength such as thermal aging, temperature/humidity aging and temperature cycling were also investigated. As a whole, better design of ACF materials can be achieved by understanding the ACF conduction mechanism.
{"title":"Design and understanding of anisotropic conductive films (ACFs) for LCD packaging","authors":"M. Yim, K. Paik","doi":"10.1109/PEP.1997.656495","DOIUrl":"https://doi.org/10.1109/PEP.1997.656495","url":null,"abstract":"Anisotropic conductive films (ACF) composed of an adhesive resin and fine conductive fillers such as metallic particles or metal-coated polymer balls are key materials for fine pitch chip-on-film (COF) and chip-on-glass (COG) LCD packaging. To understand and design better quality ACF materials, a conduction model with a physical contact mechanism was simulated and experimentally proved. To understand the contact area changes, two pressure dependent models - (1) elastic/plastic deformation and (2) FEM - were developed and proved by testing various ACFs. Experimental variables such as bonding pressure, and the number, size, mechanical and electrical properties of Ni powders and Au-coated polymer conductive particles were applied. The models agreed well with experimental results, except at higher bonding pressures. In general, as bonding pressure increases, sharp decrease in contact resistance followed by a constant value is observed after reaching a critical bonding pressure. However, excessive bonding pressure inversely increased the ACF connection resistance. If more conductive particles were added, the connection resistance rapidly decreased to a constant. This is the counter-effect of two opposing factors: resistance increase by decrease in contact area per particle and resistance decrease by increased conduction path numbers. Also, environmental effects on contact resistance and adhesion strength such as thermal aging, temperature/humidity aging and temperature cycling were also investigated. As a whole, better design of ACF materials can be achieved by understanding the ACF conduction mechanism.","PeriodicalId":340973,"journal":{"name":"Proceedings. The First IEEE International Symposium on Polymeric Electronics Packaging, PEP '97 (Cat. No.97TH8268)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126058071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The application scope of conductive adhesives increases continuously, requiring new and improved properties. In general, isotropic conductivity is achieved by loading a resistive polymer (mainly epoxy resins) with 70-80 wt% metal filler particles. During cure, resin shrinkage lowers contact resistance between neighbouring particles, giving a conductive 3D network. However, at high currents, local current density at neighbouring particle contact spots may be a limiting factor. Due to the filler content percolation effect, electrons flow through very small contact spot areas, so local current density cannot be calculated from applied current and adhesive bond geometry. This may lead to electromigration, resulting in Ag atom transport within the filler particles and then by diffusion through the polymer. This effect occurs even if self-heating is neglected. In this study, early-stage resistance degradation for bisphenol-A type and cycloaliphalic resins, loaded with Ag flakes and porous Ag powder respectively, is examined using adhesive stripe samples on FR-4. Resistance is measured by a four-point technique. Samples are held at constant temperature in an inert liquid, and a pulsed DC-current is applied. Tests with temperatures from 80-130/spl deg/C and 2-33 A/mm/sup 2/ current densities are performed. A linear increase or decrease in resistance with time is observed for flake and porous Ag filled adhesives, respectively, due to current application, whereby a sintering process for the porous Ag must be taken into account. Current density and temperature dependences for various parameters are discussed; a degradation model is proposed.
{"title":"Current-induced degradation of isotropically conductive adhesives","authors":"S. Kotthaus, R. Haug, H. Schafer, O. Hennemann","doi":"10.1109/PEP.1997.656474","DOIUrl":"https://doi.org/10.1109/PEP.1997.656474","url":null,"abstract":"The application scope of conductive adhesives increases continuously, requiring new and improved properties. In general, isotropic conductivity is achieved by loading a resistive polymer (mainly epoxy resins) with 70-80 wt% metal filler particles. During cure, resin shrinkage lowers contact resistance between neighbouring particles, giving a conductive 3D network. However, at high currents, local current density at neighbouring particle contact spots may be a limiting factor. Due to the filler content percolation effect, electrons flow through very small contact spot areas, so local current density cannot be calculated from applied current and adhesive bond geometry. This may lead to electromigration, resulting in Ag atom transport within the filler particles and then by diffusion through the polymer. This effect occurs even if self-heating is neglected. In this study, early-stage resistance degradation for bisphenol-A type and cycloaliphalic resins, loaded with Ag flakes and porous Ag powder respectively, is examined using adhesive stripe samples on FR-4. Resistance is measured by a four-point technique. Samples are held at constant temperature in an inert liquid, and a pulsed DC-current is applied. Tests with temperatures from 80-130/spl deg/C and 2-33 A/mm/sup 2/ current densities are performed. A linear increase or decrease in resistance with time is observed for flake and porous Ag filled adhesives, respectively, due to current application, whereby a sintering process for the porous Ag must be taken into account. Current density and temperature dependences for various parameters are discussed; a degradation model is proposed.","PeriodicalId":340973,"journal":{"name":"Proceedings. The First IEEE International Symposium on Polymeric Electronics Packaging, PEP '97 (Cat. No.97TH8268)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126845675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. Cotts, T. Driscoll, N. Guydosh, G. Lehmann, P. Li
In flip-chip packaging, an underfill mixture is placed into the chip-to-substrate stand-off created by the array of solder bumps, using a capillary flow process. The underfill mixture is densely filled with solid silica particles to achieve the desired effective coefficient of thermal expansion. Thus, during the flow process, the underfill mixture is a dense suspension of solid particles in a liquid carrier. The flow behaviour is a complex function of the mixture properties, the wetting properties, and the flow geometry. The determination of the correct metrics to characterize the flow behaviour is a major goal of our ongoing DARPA funded investigation of the underfill flow process. This paper reports on the use of a plane channel capillary flow to characterize underfill materials. We define and explore a metric termed the flow parameter which scales as /spl sigma/cos(/spl theta/)//spl mu//sub app/. The measured flow behaviour provides evidence that both the contact angle (/spl theta/) and the suspension viscosity (/spl mu//sub app/) vary with time under the influence of changing flow conditions. The flow parameter is useful in detecting both of these phenomena. The contact angle variation is consistent with the literature on wetting dynamics, where /spl theta/ is observed to be a function of the contact line speed. Nonlinear fluid behaviour is evident for both model suspensions and commercial underfill materials.
{"title":"Underflow process for direct-chip-attachment packaging","authors":"E. Cotts, T. Driscoll, N. Guydosh, G. Lehmann, P. Li","doi":"10.1109/PEP.1997.656500","DOIUrl":"https://doi.org/10.1109/PEP.1997.656500","url":null,"abstract":"In flip-chip packaging, an underfill mixture is placed into the chip-to-substrate stand-off created by the array of solder bumps, using a capillary flow process. The underfill mixture is densely filled with solid silica particles to achieve the desired effective coefficient of thermal expansion. Thus, during the flow process, the underfill mixture is a dense suspension of solid particles in a liquid carrier. The flow behaviour is a complex function of the mixture properties, the wetting properties, and the flow geometry. The determination of the correct metrics to characterize the flow behaviour is a major goal of our ongoing DARPA funded investigation of the underfill flow process. This paper reports on the use of a plane channel capillary flow to characterize underfill materials. We define and explore a metric termed the flow parameter which scales as /spl sigma/cos(/spl theta/)//spl mu//sub app/. The measured flow behaviour provides evidence that both the contact angle (/spl theta/) and the suspension viscosity (/spl mu//sub app/) vary with time under the influence of changing flow conditions. The flow parameter is useful in detecting both of these phenomena. The contact angle variation is consistent with the literature on wetting dynamics, where /spl theta/ is observed to be a function of the contact line speed. Nonlinear fluid behaviour is evident for both model suspensions and commercial underfill materials.","PeriodicalId":340973,"journal":{"name":"Proceedings. The First IEEE International Symposium on Polymeric Electronics Packaging, PEP '97 (Cat. No.97TH8268)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127295686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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