Flip chip attach provides the highest interconnection density possible, making this technology attractive for use with high density flex substrates. This paper presents three approaches to a flip chip adhesive process based on flexible polyimide and polyester substrates using Au, Ni-Au and Au stud bumps with anisotropic adhesives, isotropic conductive adhesives and nonconductive adhesives. Isotropic conductive adhesives conduct equally in all directions. For flip chip application of such adhesives, the material must be applied precisely on the points to be electrically connected and not allowed to flow and short circuit between circuit lines. Anisotropically conductive adhesives are prepared by dispersing conductive particles in an adhesive matrix at high enough concentration to assure reliable conductivity between substrate and IC electrodes. Another possibility is the use of nonconductive adhesives and Au-bumped chips, which are bonded via thermocompression to the substrate. During bonding, the bumps pierce a nonconducting adhesive foil and make electrical contact while the adhesive supplies mechanical stability. Moreover, the adhesive fills the gap between chip and substrate, relieving the bumps of mechanical stress due to the different CTEs. Reliability evaluation was performed with specific regard to the interface reactions between polymers and metal surfaces in adhesive contacts. The electrical and mechanical performance of the adhesive bonds were studied by evaluating initial contact resistance as a function of temperature and humidity.
{"title":"Adhesive flip chip bonding on flexible substrates","authors":"R. Aschenbrenner, R. Miessner, H. Reichl","doi":"10.1109/PEP.1997.656478","DOIUrl":"https://doi.org/10.1109/PEP.1997.656478","url":null,"abstract":"Flip chip attach provides the highest interconnection density possible, making this technology attractive for use with high density flex substrates. This paper presents three approaches to a flip chip adhesive process based on flexible polyimide and polyester substrates using Au, Ni-Au and Au stud bumps with anisotropic adhesives, isotropic conductive adhesives and nonconductive adhesives. Isotropic conductive adhesives conduct equally in all directions. For flip chip application of such adhesives, the material must be applied precisely on the points to be electrically connected and not allowed to flow and short circuit between circuit lines. Anisotropically conductive adhesives are prepared by dispersing conductive particles in an adhesive matrix at high enough concentration to assure reliable conductivity between substrate and IC electrodes. Another possibility is the use of nonconductive adhesives and Au-bumped chips, which are bonded via thermocompression to the substrate. During bonding, the bumps pierce a nonconducting adhesive foil and make electrical contact while the adhesive supplies mechanical stability. Moreover, the adhesive fills the gap between chip and substrate, relieving the bumps of mechanical stress due to the different CTEs. Reliability evaluation was performed with specific regard to the interface reactions between polymers and metal surfaces in adhesive contacts. The electrical and mechanical performance of the adhesive bonds were studied by evaluating initial contact resistance as a function of temperature and humidity.","PeriodicalId":340973,"journal":{"name":"Proceedings. The First IEEE International Symposium on Polymeric Electronics Packaging, PEP '97 (Cat. No.97TH8268)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114661036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper reviews the traditional use of thermoset (epoxy) polymer adhesives and highlights some of the limitations for current microelectronic applications. The development of thermoplastic materials offers many advantages in material options in terms of form and processing. The past two or three years has seen a rapid uptake of these new thermoplastic adhesive materials for attaching large area silicon to a wide range of substrate and package materials. Furthermore, new innovative concepts in die attach, ranging from dry adhesive preform, ribbon and extruded rod processes have been developed in both the USA and Far East, and this paper outlines the techniques used for some of these process options. An outline of some equipment developments to use these new adhesive technologies especially for die attach is given and summary data on "end user" case histories is also presented. The paper concludes with a prediction for the future in that even more novel thermoplastic adhesive materials will be developed, offering a range of both isotropic and anisotropic form options.
{"title":"Innovations in thermoplastic die attach adhesives for microelectronic packaging","authors":"S. Corbett, P. Ongley","doi":"10.1109/PEP.1997.656488","DOIUrl":"https://doi.org/10.1109/PEP.1997.656488","url":null,"abstract":"This paper reviews the traditional use of thermoset (epoxy) polymer adhesives and highlights some of the limitations for current microelectronic applications. The development of thermoplastic materials offers many advantages in material options in terms of form and processing. The past two or three years has seen a rapid uptake of these new thermoplastic adhesive materials for attaching large area silicon to a wide range of substrate and package materials. Furthermore, new innovative concepts in die attach, ranging from dry adhesive preform, ribbon and extruded rod processes have been developed in both the USA and Far East, and this paper outlines the techniques used for some of these process options. An outline of some equipment developments to use these new adhesive technologies especially for die attach is given and summary data on \"end user\" case histories is also presented. The paper concludes with a prediction for the future in that even more novel thermoplastic adhesive materials will be developed, offering a range of both isotropic and anisotropic form options.","PeriodicalId":340973,"journal":{"name":"Proceedings. The First IEEE International Symposium on Polymeric Electronics Packaging, PEP '97 (Cat. No.97TH8268)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131395616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The microvia, based on nonmechanical drilling techniques, has been introduced to the PCB market during the last few years. The available techniques provide reduced via dimensions and land sizes that give increased packaging density and improved routing possibilities for high density packages. The method of building the boards is based on a thin dielectric and sequential board build-up. In comparison with conventional PCB techniques, the number of process steps is reduced. This fact in combination with increased packaging density affects the environmental influence positively. Compatibility with conventional FR4 processing is in general good. The availability of this technique is set to increase in the market, and it has great potential for cost-effectiveness in comparison with conventional techniques.
{"title":"Microvia technique for PCB manufacturing - a technique meeting the requirement of high interconnect density","authors":"T. Lindahl","doi":"10.1109/PEP.1997.656472","DOIUrl":"https://doi.org/10.1109/PEP.1997.656472","url":null,"abstract":"The microvia, based on nonmechanical drilling techniques, has been introduced to the PCB market during the last few years. The available techniques provide reduced via dimensions and land sizes that give increased packaging density and improved routing possibilities for high density packages. The method of building the boards is based on a thin dielectric and sequential board build-up. In comparison with conventional PCB techniques, the number of process steps is reduced. This fact in combination with increased packaging density affects the environmental influence positively. Compatibility with conventional FR4 processing is in general good. The availability of this technique is set to increase in the market, and it has great potential for cost-effectiveness in comparison with conventional techniques.","PeriodicalId":340973,"journal":{"name":"Proceedings. The First IEEE International Symposium on Polymeric Electronics Packaging, PEP '97 (Cat. No.97TH8268)","volume":"266 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132112929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Parylene is a conformal polymer film that has been used as a protective conformal coating for more than 25 years. It provides environmental and dielectric isolation in a variety of applications, industrial and automotive sensors, electronic circuits, hybrids, various medical substrates, and is also used extensively for corrosion protection and electrical insulation of ferrites and magnets. The most important performance specifications for a conformal coating are (1) uniformity and completeness of coverage, and (2) physical, electrical, chemical, mechanical, and barrier properties. Parylene offers significant performance capabilities in both of these areas. As a nonsolvent based coating, parylene is not affected by volatile organic compound (VOC) restrictions, and it is not implicated in the ozone depletion concerns of the Montreal Protocol and other environmental legislation. The parylene vacuum condensation process is now also capable of producing a dissipative parylene 'C-shield' that allows packaging of microelectronics with both the environmental protection offered by parylene and the dissipation of undesired stray EM radiation. This eliminates encapsulation with metal boxes and allows major cost and weight savings.
{"title":"C-shield parylene allows major weight saving for EM shielding of microelectronics","authors":"J. Noordegraaf, H. Hull","doi":"10.1109/PEP.1997.656489","DOIUrl":"https://doi.org/10.1109/PEP.1997.656489","url":null,"abstract":"Parylene is a conformal polymer film that has been used as a protective conformal coating for more than 25 years. It provides environmental and dielectric isolation in a variety of applications, industrial and automotive sensors, electronic circuits, hybrids, various medical substrates, and is also used extensively for corrosion protection and electrical insulation of ferrites and magnets. The most important performance specifications for a conformal coating are (1) uniformity and completeness of coverage, and (2) physical, electrical, chemical, mechanical, and barrier properties. Parylene offers significant performance capabilities in both of these areas. As a nonsolvent based coating, parylene is not affected by volatile organic compound (VOC) restrictions, and it is not implicated in the ozone depletion concerns of the Montreal Protocol and other environmental legislation. The parylene vacuum condensation process is now also capable of producing a dissipative parylene 'C-shield' that allows packaging of microelectronics with both the environmental protection offered by parylene and the dissipation of undesired stray EM radiation. This eliminates encapsulation with metal boxes and allows major cost and weight savings.","PeriodicalId":340973,"journal":{"name":"Proceedings. The First IEEE International Symposium on Polymeric Electronics Packaging, PEP '97 (Cat. No.97TH8268)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132968898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The characteristics of conductive particles in anisotropically conductive adhesives (ACA) were studied by optical microscopy observation and nano indenter measurements. The indentation measurement was performed at the particles in ACA joints using different bonding forces. The load-displacement curves and microhardness values are obtained, which indicate that the nano indenter could be used for quantitative estimation of the electrical and mechanical characteristics of conductive particles in ACAs.
{"title":"Quantitative estimate of the characteristics of conductive particles in ACA by using nano indenter","authors":"X. Wang, Y. Wang, G. Chen, J. Liu, Z. Lai","doi":"10.1109/PEP.1997.656480","DOIUrl":"https://doi.org/10.1109/PEP.1997.656480","url":null,"abstract":"The characteristics of conductive particles in anisotropically conductive adhesives (ACA) were studied by optical microscopy observation and nano indenter measurements. The indentation measurement was performed at the particles in ACA joints using different bonding forces. The load-displacement curves and microhardness values are obtained, which indicate that the nano indenter could be used for quantitative estimation of the electrical and mechanical characteristics of conductive particles in ACAs.","PeriodicalId":340973,"journal":{"name":"Proceedings. The First IEEE International Symposium on Polymeric Electronics Packaging, PEP '97 (Cat. No.97TH8268)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131442495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Printed circuit boards with unfavourable deflection have been considered for better mechanical design. During the reflow process, the PCB has experienced a temperature range between ambient temperature and peak furnace temperature. Out of plane deflection is generated due to the thermal properties mismatch of the material composition. The combination of board materials and copper plating is researched for investigation of the cause of the trouble and for design improvements. The effects of soldering and mounted component weight are ignored due to the input data complexity. A set of real PCBs has been exposed in a reflow process and deflection data is collected for comparison. As part of the analysis procedure, a finite element model for board deflection was proposed.
{"title":"Finite element modeling of printed circuit board for structural analysis","authors":"M. Lee","doi":"10.1109/PEP.1997.656471","DOIUrl":"https://doi.org/10.1109/PEP.1997.656471","url":null,"abstract":"Printed circuit boards with unfavourable deflection have been considered for better mechanical design. During the reflow process, the PCB has experienced a temperature range between ambient temperature and peak furnace temperature. Out of plane deflection is generated due to the thermal properties mismatch of the material composition. The combination of board materials and copper plating is researched for investigation of the cause of the trouble and for design improvements. The effects of soldering and mounted component weight are ignored due to the input data complexity. A set of real PCBs has been exposed in a reflow process and deflection data is collected for comparison. As part of the analysis procedure, a finite element model for board deflection was proposed.","PeriodicalId":340973,"journal":{"name":"Proceedings. The First IEEE International Symposium on Polymeric Electronics Packaging, PEP '97 (Cat. No.97TH8268)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125849298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Various adhesives were tested for MLC capacitors and ICs as lead solder replacements from the viewpoints of contact resistance and adhesion strength. I-V and frequency characteristics were also measured. On the whole, the contact resistance depended on the volume resistivity of each adhesive. Different termination and bump materials gave different contact resistance values. In particular, Sn plated terminations tended to give higher contact resistance. The adhesion strength was also influenced by the types of adhesives, and the electrode, termination and bump materials. Although Ni filled adhesive, which had good adhesion strength and did not cause electromigration, had higher volume resistivity, it gave good I-V characteristics at low current.
{"title":"Conductive adhesive materials for lead solder replacement","authors":"K. Suzuki, O. Suzuki, M. Komagata","doi":"10.1109/PEP.1997.656476","DOIUrl":"https://doi.org/10.1109/PEP.1997.656476","url":null,"abstract":"Various adhesives were tested for MLC capacitors and ICs as lead solder replacements from the viewpoints of contact resistance and adhesion strength. I-V and frequency characteristics were also measured. On the whole, the contact resistance depended on the volume resistivity of each adhesive. Different termination and bump materials gave different contact resistance values. In particular, Sn plated terminations tended to give higher contact resistance. The adhesion strength was also influenced by the types of adhesives, and the electrode, termination and bump materials. Although Ni filled adhesive, which had good adhesion strength and did not cause electromigration, had higher volume resistivity, it gave good I-V characteristics at low current.","PeriodicalId":340973,"journal":{"name":"Proceedings. The First IEEE International Symposium on Polymeric Electronics Packaging, PEP '97 (Cat. No.97TH8268)","volume":"277 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133013540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Nguyen, L. Hoang, P. Fine, S. Shi, M. Vincent, L. Wang, C. Wong, Q. Tong, B. Ma, R. Humphreys, A. Savoca
The typical underfill enhances the solder life of flip chip structures by up to an order of magnitude. With increasing packaging applications requiring flip chip interconnection, much industry interest has been devoted to the development of better underfill materials, which are more cost-effective and provide better performance than current commercial materials. This paper presents the highlights of a recent DARPA-funded program to develop new underfill materials for low-cost flip chip applications.
{"title":"High performance underfills development - materials, processes, and reliability","authors":"L. Nguyen, L. Hoang, P. Fine, S. Shi, M. Vincent, L. Wang, C. Wong, Q. Tong, B. Ma, R. Humphreys, A. Savoca","doi":"10.1109/PEP.1997.656503","DOIUrl":"https://doi.org/10.1109/PEP.1997.656503","url":null,"abstract":"The typical underfill enhances the solder life of flip chip structures by up to an order of magnitude. With increasing packaging applications requiring flip chip interconnection, much industry interest has been devoted to the development of better underfill materials, which are more cost-effective and provide better performance than current commercial materials. This paper presents the highlights of a recent DARPA-funded program to develop new underfill materials for low-cost flip chip applications.","PeriodicalId":340973,"journal":{"name":"Proceedings. The First IEEE International Symposium on Polymeric Electronics Packaging, PEP '97 (Cat. No.97TH8268)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129794839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Finite element (FE) simulations represent a useful tool to evaluate the thermomechanical behaviour of electronic packages. However, the use of the FE-method generates special difficulties, with particular regard to the proper constitutive modelling of materials used in the assembly. One more general problem in the numerical investigations of encapsulated silicon chips is the occurrence of interfaces between the dissimilar materials. Due to the assumption of sharp interface edges and interface crack tips, stress singularities arise which might be accounted for only approximately in the FE-calculation. The paper intends to show solutions of these simulation difficulties, also by means of materials testing. The complex material behaviour is discussed for different filled epoxy materials, with particular regard to the influence of filler content. A new solution method for the interfacial edge problem is briefly introduced. As an example, the pull strength test is used and the asymptotic solution for an interface edge is presented.
{"title":"FE-simulation for polymeric packaging materials","authors":"R. Dudek, M. Scherzer, A. Schubert, B. Michel","doi":"10.1109/PEP.1997.656484","DOIUrl":"https://doi.org/10.1109/PEP.1997.656484","url":null,"abstract":"Finite element (FE) simulations represent a useful tool to evaluate the thermomechanical behaviour of electronic packages. However, the use of the FE-method generates special difficulties, with particular regard to the proper constitutive modelling of materials used in the assembly. One more general problem in the numerical investigations of encapsulated silicon chips is the occurrence of interfaces between the dissimilar materials. Due to the assumption of sharp interface edges and interface crack tips, stress singularities arise which might be accounted for only approximately in the FE-calculation. The paper intends to show solutions of these simulation difficulties, also by means of materials testing. The complex material behaviour is discussed for different filled epoxy materials, with particular regard to the influence of filler content. A new solution method for the interfacial edge problem is briefly introduced. As an example, the pull strength test is used and the asymptotic solution for an interface edge is presented.","PeriodicalId":340973,"journal":{"name":"Proceedings. The First IEEE International Symposium on Polymeric Electronics Packaging, PEP '97 (Cat. No.97TH8268)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128871457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents the development and application of a computer-aided engineering tool, EPACK(TM), for hygro-thermal-mechanical performance and reliability evaluation of plastic IC packages. With this user-friendly and fully automated tool, a packaging engineer can perform reliability evaluation of a plastic IC package in minutes.
{"title":"Hygrothermal reliability evaluation of plastic IC packages with computer-aided engineering tools","authors":"A. Kuo, L. Nguyen","doi":"10.1109/PEP.1997.656486","DOIUrl":"https://doi.org/10.1109/PEP.1997.656486","url":null,"abstract":"This paper presents the development and application of a computer-aided engineering tool, EPACK(TM), for hygro-thermal-mechanical performance and reliability evaluation of plastic IC packages. With this user-friendly and fully automated tool, a packaging engineer can perform reliability evaluation of a plastic IC package in minutes.","PeriodicalId":340973,"journal":{"name":"Proceedings. The First IEEE International Symposium on Polymeric Electronics Packaging, PEP '97 (Cat. No.97TH8268)","volume":"147 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121319846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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