The curing conditions and material properties such as the coefficient of thermal expansion, glass transition temperature, Young's modulus, and moisture content of four different underfill encapsulants with different size and content of filler and epoxy are measured. The effects of these underfills on the flow rate, mechanical performance, and electrical performance of a solder-bumped functional flip chip on an organic substrate are studied.
{"title":"Effects of underfill encapsulant on the mechanical and electrical performance of a functional flip chip device","authors":"J. Lau, C. Chang, R. Chen","doi":"10.1109/PEP.1997.656499","DOIUrl":"https://doi.org/10.1109/PEP.1997.656499","url":null,"abstract":"The curing conditions and material properties such as the coefficient of thermal expansion, glass transition temperature, Young's modulus, and moisture content of four different underfill encapsulants with different size and content of filler and epoxy are measured. The effects of these underfills on the flow rate, mechanical performance, and electrical performance of a solder-bumped functional flip chip on an organic substrate are studied.","PeriodicalId":340973,"journal":{"name":"Proceedings. The First IEEE International Symposium on Polymeric Electronics Packaging, PEP '97 (Cat. No.97TH8268)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127654715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Recently, several low cost alternatives for flip-chip interconnection technology have been investigated. The scope of this paper is a reliability study of flip-chip assemblies on various substrates (mainly FR4). The deterioration (characterised by the electrical resistance) of isotropically conductive adhesive and of solder (63Sn37Pb, 96.5Sn3.5Ag) bumps caused by both thermal cycling and thermal shocks are described. These investigations confirm that in low cost flip-chip technology, there is practically no reliable bump interconnection without using underfill material.
{"title":"The beneficial effect of underfilling on the reliability of flip-chip joints","authors":"B. Roesner","doi":"10.1109/PEP.1997.656506","DOIUrl":"https://doi.org/10.1109/PEP.1997.656506","url":null,"abstract":"Recently, several low cost alternatives for flip-chip interconnection technology have been investigated. The scope of this paper is a reliability study of flip-chip assemblies on various substrates (mainly FR4). The deterioration (characterised by the electrical resistance) of isotropically conductive adhesive and of solder (63Sn37Pb, 96.5Sn3.5Ag) bumps caused by both thermal cycling and thermal shocks are described. These investigations confirm that in low cost flip-chip technology, there is practically no reliable bump interconnection without using underfill material.","PeriodicalId":340973,"journal":{"name":"Proceedings. The First IEEE International Symposium on Polymeric Electronics Packaging, PEP '97 (Cat. No.97TH8268)","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117175052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper discusses the selection of a suitable isotropically conductive adhesive for flip chip bonding of a micromachined component. The adhesive must have adequate electrical conductivity and mechanical bonding strength. Most commercial adhesives possess these qualities. In addition, small bumps of spherical shape need to be dispensed evenly and repeatedly. Eight adhesives were studied and one suitable candidate was found. The manufacture of the spectrometers proceeded successfully. The interferometer was fixed on top of a silicon detector by a flip chip technique using an isotropically conductive adhesive. Two prototype series with a total of 25 spectrometers have been produced, and 23 of them passed operational testing.
{"title":"Adhesive flip chip bonding in a miniaturised spectrometer","authors":"O. Rusanen, K. Keranen, M. Blomberg, A. Lehto","doi":"10.1109/PEP.1997.656479","DOIUrl":"https://doi.org/10.1109/PEP.1997.656479","url":null,"abstract":"This paper discusses the selection of a suitable isotropically conductive adhesive for flip chip bonding of a micromachined component. The adhesive must have adequate electrical conductivity and mechanical bonding strength. Most commercial adhesives possess these qualities. In addition, small bumps of spherical shape need to be dispensed evenly and repeatedly. Eight adhesives were studied and one suitable candidate was found. The manufacture of the spectrometers proceeded successfully. The interferometer was fixed on top of a silicon detector by a flip chip technique using an isotropically conductive adhesive. Two prototype series with a total of 25 spectrometers have been produced, and 23 of them passed operational testing.","PeriodicalId":340973,"journal":{"name":"Proceedings. The First IEEE International Symposium on Polymeric Electronics Packaging, PEP '97 (Cat. No.97TH8268)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116667469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. N. Oguibe, S. Mannan, D. Whalley, D.J. Williams
This paper explores experimentally and through analytical and computational models, the mechanisms of conduction in flip chip interconnects using anisotropic conducting adhesives. A large number of assemblies were constructed with geometries in the 200-500 /spl mu/m range, and wide variations in joint resistance were found to occur both within the same assembly and between assemblies under the same experimental conditions. In order to explain the origin of these unsatisfactory connections, a series of tests to measure the contact resistance linearity of both high and low resistance joints were made. The results from these measurements show that a large number of low resistance joints are ohmic, while most joints of relatively high resistance show resistive heating. However, in some of the initially high resistance joints there is an initial ohmic behaviour which is followed by a breakdown of a dielectric or insulating film, resulting in lower resistance. In addition to linearity measurements, computational models of metallic conduction in solid and polymer core particles were constructed to help understand the conduction mechanism. These models, which are based on the finite element method, represent typical conductor particles trapped between appropriate substrate and component metallisation. The model results show that the contact area required to explain high resistances is small and that the likelihood of obtaining a high resistance through such a small area of metal-to-metal contact is small, thus giving a strong indication of the presence of high resistivity films at the joint contact surfaces.
{"title":"Conduction mechanisms in anisotropic conducting adhesive assembly","authors":"C. N. Oguibe, S. Mannan, D. Whalley, D.J. Williams","doi":"10.1109/PEP.1997.656497","DOIUrl":"https://doi.org/10.1109/PEP.1997.656497","url":null,"abstract":"This paper explores experimentally and through analytical and computational models, the mechanisms of conduction in flip chip interconnects using anisotropic conducting adhesives. A large number of assemblies were constructed with geometries in the 200-500 /spl mu/m range, and wide variations in joint resistance were found to occur both within the same assembly and between assemblies under the same experimental conditions. In order to explain the origin of these unsatisfactory connections, a series of tests to measure the contact resistance linearity of both high and low resistance joints were made. The results from these measurements show that a large number of low resistance joints are ohmic, while most joints of relatively high resistance show resistive heating. However, in some of the initially high resistance joints there is an initial ohmic behaviour which is followed by a breakdown of a dielectric or insulating film, resulting in lower resistance. In addition to linearity measurements, computational models of metallic conduction in solid and polymer core particles were constructed to help understand the conduction mechanism. These models, which are based on the finite element method, represent typical conductor particles trapped between appropriate substrate and component metallisation. The model results show that the contact area required to explain high resistances is small and that the likelihood of obtaining a high resistance through such a small area of metal-to-metal contact is small, thus giving a strong indication of the presence of high resistivity films at the joint contact surfaces.","PeriodicalId":340973,"journal":{"name":"Proceedings. The First IEEE International Symposium on Polymeric Electronics Packaging, PEP '97 (Cat. No.97TH8268)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117025597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A novel base technology that is applicable to all major packaging and redistribution elements in an electronic module is presented. A single family of polymer/metal composite conductors can be used for chip packaging redistribution layers, MCM or multilayer PWB interconnects, and SMT assembly. High density multilayer circuits with landless blind and buried vias can be fabricated by filling conductor paste into photoimaged dielectrics and thermal processing. Via layers are prepared directly on the inherently planarized circuit layer in identical fashion. Building up layers sequentially in this manner results in multilayer circuits built on a single substrate layer and minimizes the number of interfaces between dissimilar materials. As these composite materials are applied in an additive fabrication method, metal substrates can be employed for high thermal dissipation and excellent CTE control over a wide temperature range. Two variants of the composite conductor can successfully replace solder for surface mount and chip on board assembly. These reliable, highly thermally and electrically conductive materials are compatible with standard metal finishes and can be adopted piecemeal as desired; however, the largest reliability and cost benefit is realized when all of the elements are used in conjunction. The conductor materials are based on interpenetrating polymer and metal networks that are formed in situ from metal particles and a thermosetting flux/binder.
{"title":"A fully additive, polymeric process for the fabrication and assembly of substrate and component level packaging","authors":"C. Gallagher, P. Gandhi, G. Matijasevic","doi":"10.1109/PEP.1997.656473","DOIUrl":"https://doi.org/10.1109/PEP.1997.656473","url":null,"abstract":"A novel base technology that is applicable to all major packaging and redistribution elements in an electronic module is presented. A single family of polymer/metal composite conductors can be used for chip packaging redistribution layers, MCM or multilayer PWB interconnects, and SMT assembly. High density multilayer circuits with landless blind and buried vias can be fabricated by filling conductor paste into photoimaged dielectrics and thermal processing. Via layers are prepared directly on the inherently planarized circuit layer in identical fashion. Building up layers sequentially in this manner results in multilayer circuits built on a single substrate layer and minimizes the number of interfaces between dissimilar materials. As these composite materials are applied in an additive fabrication method, metal substrates can be employed for high thermal dissipation and excellent CTE control over a wide temperature range. Two variants of the composite conductor can successfully replace solder for surface mount and chip on board assembly. These reliable, highly thermally and electrically conductive materials are compatible with standard metal finishes and can be adopted piecemeal as desired; however, the largest reliability and cost benefit is realized when all of the elements are used in conjunction. The conductor materials are based on interpenetrating polymer and metal networks that are formed in situ from metal particles and a thermosetting flux/binder.","PeriodicalId":340973,"journal":{"name":"Proceedings. The First IEEE International Symposium on Polymeric Electronics Packaging, PEP '97 (Cat. No.97TH8268)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121053556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Direct chip attach (DCA) flip chip assembly offers many advantages in terms of signal speed and performance, compactness, weight and long term cost savings. The growth of portable electronics has focused attention on the use of flip chip attach, where all of these virtues are attractive. Selection of uniquely compatible materials for advanced assembly and packaging is rarely possible and a compromise is nearly always needed. This is particularly the case with DCA of complex Si devices using bumped technology for interconnection and mechanical attachment to the substrate. While there is considerable interest in the use of specialised conductive polymer adhesives, the implementation of DCA mainly relies on metallurgical connection between chip and substrate pad, whether it be the C4 solder bump process or the recent Au stud technique. The inevitable CTE mismatch between chip and composite substrate must be managed for long term joint reliability. Early work in DCA/flip chip development has shown clearly the possibility of joint dislocation and failure when the device is thermally stressed, particularly under extended rapid temperature cycling. Polymer-based underfill encapsulant materials have been developed and formulated to minimise the effect of /spl Delta/CTE induced stresses which manage the problem effectively by acting as a mechanical compensator layer between chip and substrate. This paper outlines the basic requirements of the underfill material, the effects of CTE mismatch and methods of application. An overview of typical problems with flip chip/underfill encapsulants is also presented.
{"title":"Underfill encapsulant technology for flip chip assembly","authors":"K. Gilleo, G. Nicholls, P. Ongley","doi":"10.1109/PEP.1997.656505","DOIUrl":"https://doi.org/10.1109/PEP.1997.656505","url":null,"abstract":"Direct chip attach (DCA) flip chip assembly offers many advantages in terms of signal speed and performance, compactness, weight and long term cost savings. The growth of portable electronics has focused attention on the use of flip chip attach, where all of these virtues are attractive. Selection of uniquely compatible materials for advanced assembly and packaging is rarely possible and a compromise is nearly always needed. This is particularly the case with DCA of complex Si devices using bumped technology for interconnection and mechanical attachment to the substrate. While there is considerable interest in the use of specialised conductive polymer adhesives, the implementation of DCA mainly relies on metallurgical connection between chip and substrate pad, whether it be the C4 solder bump process or the recent Au stud technique. The inevitable CTE mismatch between chip and composite substrate must be managed for long term joint reliability. Early work in DCA/flip chip development has shown clearly the possibility of joint dislocation and failure when the device is thermally stressed, particularly under extended rapid temperature cycling. Polymer-based underfill encapsulant materials have been developed and formulated to minimise the effect of /spl Delta/CTE induced stresses which manage the problem effectively by acting as a mechanical compensator layer between chip and substrate. This paper outlines the basic requirements of the underfill material, the effects of CTE mismatch and methods of application. An overview of typical problems with flip chip/underfill encapsulants is also presented.","PeriodicalId":340973,"journal":{"name":"Proceedings. The First IEEE International Symposium on Polymeric Electronics Packaging, PEP '97 (Cat. No.97TH8268)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129764004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents the time domain measurements of current and electromagnetic fields generated by electrostatic discharges (ESD). Electromagnetic fields a few centimetres away from the ESD were measured in time domain using passive near field probes. The time domain signals were converted into the frequency domain by FFT, and antenna correction factors were applied. The ESD current was generated by an ESD generator. A typical ESD current of 10 A with 25 ns rise time can create a magnetic field of the order of 70 /spl mu/T at a distance of 10 mm from the ESD and an electric field of the order of 6 kV/m at a distance of 30 mm from the ESD. The variation of these electromagnetic fields with distance from the discharge is also investigated.
{"title":"Time varying electromagnetic fields generated by electrostatic discharges","authors":"J. Bendjamin, R. Thottappillil, V. Scuka","doi":"10.1109/PEP.1997.656490","DOIUrl":"https://doi.org/10.1109/PEP.1997.656490","url":null,"abstract":"This paper presents the time domain measurements of current and electromagnetic fields generated by electrostatic discharges (ESD). Electromagnetic fields a few centimetres away from the ESD were measured in time domain using passive near field probes. The time domain signals were converted into the frequency domain by FFT, and antenna correction factors were applied. The ESD current was generated by an ESD generator. A typical ESD current of 10 A with 25 ns rise time can create a magnetic field of the order of 70 /spl mu/T at a distance of 10 mm from the ESD and an electric field of the order of 6 kV/m at a distance of 30 mm from the ESD. The variation of these electromagnetic fields with distance from the discharge is also investigated.","PeriodicalId":340973,"journal":{"name":"Proceedings. The First IEEE International Symposium on Polymeric Electronics Packaging, PEP '97 (Cat. No.97TH8268)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131064041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The increasing miniaturisation in electronics production with simultaneous increase in functionality leads to finer structures and larger chip-size high pin count components. The enlargement of the component size increases the danger of component damage due to moisture absorption. To avoid potential component failure through tears at the compound or through subsequent corrosion, these cracking-endangered components are delivered in specific containers, drypacks, and are stored in nitrogen set. Furthermore, the user normally retests the components before releasing them in a series of destructive, cost- and time-consuming tests. Despite these extensive measures, components often fail during reflow soldering but are mostly recognised later, during use. The existing damage model describes the connection between storage conditions and its effects with component quality during processing inadequately. In this paper, the influence of different storage conditions on cracking behaviour of high pin count components is examined. The aim is to register all relevant influential parameters in an expanded damage model and to quantify effects on later processing of the components. Effective strategies can be developed based on the new damage model for component storage and transportation. It was validated that over a component-specific relative longitudinal change (approx. 3%), cracking is registered. Whether this limit is exceeded depends on the maximum soldering temperature, the moisture absorbed by the component, its general tensile stress behaviour and the heating rate.
{"title":"Influences of storage conditions on component cracking","authors":"K. Feldmann, R. Feuerstein, K. Gotz","doi":"10.1109/PEP.1997.656469","DOIUrl":"https://doi.org/10.1109/PEP.1997.656469","url":null,"abstract":"The increasing miniaturisation in electronics production with simultaneous increase in functionality leads to finer structures and larger chip-size high pin count components. The enlargement of the component size increases the danger of component damage due to moisture absorption. To avoid potential component failure through tears at the compound or through subsequent corrosion, these cracking-endangered components are delivered in specific containers, drypacks, and are stored in nitrogen set. Furthermore, the user normally retests the components before releasing them in a series of destructive, cost- and time-consuming tests. Despite these extensive measures, components often fail during reflow soldering but are mostly recognised later, during use. The existing damage model describes the connection between storage conditions and its effects with component quality during processing inadequately. In this paper, the influence of different storage conditions on cracking behaviour of high pin count components is examined. The aim is to register all relevant influential parameters in an expanded damage model and to quantify effects on later processing of the components. Effective strategies can be developed based on the new damage model for component storage and transportation. It was validated that over a component-specific relative longitudinal change (approx. 3%), cracking is registered. Whether this limit is exceeded depends on the maximum soldering temperature, the moisture absorbed by the component, its general tensile stress behaviour and the heating rate.","PeriodicalId":340973,"journal":{"name":"Proceedings. The First IEEE International Symposium on Polymeric Electronics Packaging, PEP '97 (Cat. No.97TH8268)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133963620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Robertsson, A. Dabek, G. Gustafsson, O. Hagel, M. Popall
Photopatternable inorganic-organic copolymers (ormocers, or organically modified ceramics) with negative resist behaviour have been developed and tested as thin film materials for electrical and/or optical packaging purposes, e.g. MCM-L/D and optoelectronic MCM packaging. Good processability in combination with a much lower post-curing temperature (120/spl deg/C-170/spl deg/C) than alternative materials such as polyimide and benzocyclobutene enables the use of low cost glass fiber reinforced polymer substrates such as FR-4 and BT. The good electrical, optical and other properties are presented and discussed. The process and tentative design-rules for multilayer MCM-L/Ds are described and some test-vehicles are presented, emphasizing the versatility and low-cost potential of the new materials.
具有负抗蚀性能的可光制模无机-有机共聚物(或有机改性陶瓷)已被开发和测试为用于电气和/或光学封装目的的薄膜材料，例如MCM- l /D和光电子MCM封装。与聚酰亚胺和苯并环丁烯等替代材料相比，良好的可加工性和更低的固化后温度(120/spl℃-170/spl℃)使得FR-4和BT等低成本玻璃纤维增强聚合物基板具有良好的电学、光学和其他性能。介绍了多层MCM-L/ d的工艺和初步设计规则，并介绍了一些试验车辆，强调了新材料的多功能性和低成本潜力。
{"title":"New patternable dielectric and optical materials for MCM-L/D- and o/e-MCM-packaging","authors":"M. Robertsson, A. Dabek, G. Gustafsson, O. Hagel, M. Popall","doi":"10.1109/PEP.1997.656491","DOIUrl":"https://doi.org/10.1109/PEP.1997.656491","url":null,"abstract":"Photopatternable inorganic-organic copolymers (ormocers, or organically modified ceramics) with negative resist behaviour have been developed and tested as thin film materials for electrical and/or optical packaging purposes, e.g. MCM-L/D and optoelectronic MCM packaging. Good processability in combination with a much lower post-curing temperature (120/spl deg/C-170/spl deg/C) than alternative materials such as polyimide and benzocyclobutene enables the use of low cost glass fiber reinforced polymer substrates such as FR-4 and BT. The good electrical, optical and other properties are presented and discussed. The process and tentative design-rules for multilayer MCM-L/Ds are described and some test-vehicles are presented, emphasizing the versatility and low-cost potential of the new materials.","PeriodicalId":340973,"journal":{"name":"Proceedings. The First IEEE International Symposium on Polymeric Electronics Packaging, PEP '97 (Cat. No.97TH8268)","volume":"11 20","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132817644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this communication, a "transfusion bonding" (TFB) technique for electronic components is briefly explained and illustrated in the context of FC-on-flex, FC-on-FR4 and flex-on-rigid board assemblies utilising either adhesive or underfill. The TFB technique with well-controlled local oxide-free liquid transfusion is not based on intermetallic formation as in conventional soldering, but on the generation of ductile Sn-based solid solution joints. The joint composition is controlled by the relative thicknesses of Sn-based undercoating and Bi overcoating which are deposited on conductors either chemically or electrochemically. The technique is 100% fluxless and is especially suitable for joining temperature-sensitive flexible substrate materials, because the bonding temperatures are well below the melting points of conventional Pb-containing solders. The TFB technique differs from the conventional soldering also in that the remelting temperatures are clearly higher than the bonding temperatures. By combining the TFB technique with adhesive joining, it is possible to increase assembly mechanical integrity and to protect the assemblies during the operational life. Different ageing and cycling tests showed that TF-bonded microjoints to flexible and rigid substrates are reliable and allow the usage of low cost flexible circuits.
{"title":"A low temperature interconnection method for electronics assembly","authors":"K. Kulojarvi, J. Kivilahti","doi":"10.1109/PEP.1997.656475","DOIUrl":"https://doi.org/10.1109/PEP.1997.656475","url":null,"abstract":"In this communication, a \"transfusion bonding\" (TFB) technique for electronic components is briefly explained and illustrated in the context of FC-on-flex, FC-on-FR4 and flex-on-rigid board assemblies utilising either adhesive or underfill. The TFB technique with well-controlled local oxide-free liquid transfusion is not based on intermetallic formation as in conventional soldering, but on the generation of ductile Sn-based solid solution joints. The joint composition is controlled by the relative thicknesses of Sn-based undercoating and Bi overcoating which are deposited on conductors either chemically or electrochemically. The technique is 100% fluxless and is especially suitable for joining temperature-sensitive flexible substrate materials, because the bonding temperatures are well below the melting points of conventional Pb-containing solders. The TFB technique differs from the conventional soldering also in that the remelting temperatures are clearly higher than the bonding temperatures. By combining the TFB technique with adhesive joining, it is possible to increase assembly mechanical integrity and to protect the assemblies during the operational life. Different ageing and cycling tests showed that TF-bonded microjoints to flexible and rigid substrates are reliable and allow the usage of low cost flexible circuits.","PeriodicalId":340973,"journal":{"name":"Proceedings. The First IEEE International Symposium on Polymeric Electronics Packaging, PEP '97 (Cat. No.97TH8268)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132985736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：