Pub Date : 2023-04-05DOI: 10.1109/ICEEICT56924.2023.10157620
D. Vaithiyanathan, Britto Pari James, K. Mariammal
Emerging technologies in VLSI signal processing systems demand FIR filters' optimal design to support a wide range of applications. This study presents the architectures for single-channel and multichannel FIR filters employing the Time-division multiplexing (TDM) scheme. The studied architecture is associated with one multiplication and addition unit to handle a wide range of channels and filter taps to have efficient resource utilization. Further accumulator-based Radix-4 multiplier, shift and add multiplication, and parallel pipelined multiplication operations involved in the architectures effectively utilize the resources to a considerable extent. The studied 16-tap multiple channel FIR filter design is simulated using Verilog Hardware Description Language (HDL) and synthesis is carried out using Xilinx Vertex Field Programmable Gate Array (FPGA). In addition, single multiply-accumulate (MAC) based FIR filter architectures with different multiplication-based approaches are implemented, and the results are reported. The analysis and synthesis results conclude that the studied 16 taps single MAC FIR structure offers area (slices) optimization of about 89.6% when examining with the conventional Parallel MAC FIR filter structure. Similarly, the 16-tap single MAC multichannel structure offers area (slices) minimization of about 90.01 % over the corresponding parallel MAC multichannel implementation. Further, the single MAC structure with a single-channel employing OPC (Output Product Coding) scheme offers 95% area reduction and 86% speed increment when compared to the parallel MAC structure with single-channel implementation. Also, the single MAC multichannel design with the OPC scheme offers 19.84% SDP (slice delay product) optimization when compared to the other studied architecture.
{"title":"Comparative Study of Single MAC FIR Filter Architectures with Different Multiplication Techniques","authors":"D. Vaithiyanathan, Britto Pari James, K. Mariammal","doi":"10.1109/ICEEICT56924.2023.10157620","DOIUrl":"https://doi.org/10.1109/ICEEICT56924.2023.10157620","url":null,"abstract":"Emerging technologies in VLSI signal processing systems demand FIR filters' optimal design to support a wide range of applications. This study presents the architectures for single-channel and multichannel FIR filters employing the Time-division multiplexing (TDM) scheme. The studied architecture is associated with one multiplication and addition unit to handle a wide range of channels and filter taps to have efficient resource utilization. Further accumulator-based Radix-4 multiplier, shift and add multiplication, and parallel pipelined multiplication operations involved in the architectures effectively utilize the resources to a considerable extent. The studied 16-tap multiple channel FIR filter design is simulated using Verilog Hardware Description Language (HDL) and synthesis is carried out using Xilinx Vertex Field Programmable Gate Array (FPGA). In addition, single multiply-accumulate (MAC) based FIR filter architectures with different multiplication-based approaches are implemented, and the results are reported. The analysis and synthesis results conclude that the studied 16 taps single MAC FIR structure offers area (slices) optimization of about 89.6% when examining with the conventional Parallel MAC FIR filter structure. Similarly, the 16-tap single MAC multichannel structure offers area (slices) minimization of about 90.01 % over the corresponding parallel MAC multichannel implementation. Further, the single MAC structure with a single-channel employing OPC (Output Product Coding) scheme offers 95% area reduction and 86% speed increment when compared to the parallel MAC structure with single-channel implementation. Also, the single MAC multichannel design with the OPC scheme offers 19.84% SDP (slice delay product) optimization when compared to the other studied architecture.","PeriodicalId":345324,"journal":{"name":"2023 Second International Conference on Electrical, Electronics, Information and Communication Technologies (ICEEICT)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125356412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-05DOI: 10.1109/ICEEICT56924.2023.10156987
M. Kalaiyarasi, Swaminathan Saravanan, Bharath Kumar Narukullapati, I. Kasireddy, D. S. Naga Malleswara Rao, D. Nagineni Venkata Sireesha
Speckle noise reduces the quality and nature of SAR imageries and diminishes the performance of SAR image processing. Thus, the multiplicative noise must be stifled before processing the image utilizing different image handling systems. Even though, there are number of speckle noise reduction techniques are available, all have its own merits and demerits. Therefore, noise reduction is still a major impediment in SAR image processing. In this paper, the speckle noise is reduced by using neural Network followed by the Bilateral Filter. This paper also presents the comparative analysis of two layered FFBPNN, TLFFBPNN and FLFFBPNN for speckle noise reduction of SAR images. Upon comparisons, it could be concluded that, TLFFBPNN de-speckling method provides good visual effects of SN reduction with better similarity and edging conservation metrics.
{"title":"Analysis of SAR ImagesDe-speckling using a Bilateral filter and Feed Forward Neural Networks","authors":"M. Kalaiyarasi, Swaminathan Saravanan, Bharath Kumar Narukullapati, I. Kasireddy, D. S. Naga Malleswara Rao, D. Nagineni Venkata Sireesha","doi":"10.1109/ICEEICT56924.2023.10156987","DOIUrl":"https://doi.org/10.1109/ICEEICT56924.2023.10156987","url":null,"abstract":"Speckle noise reduces the quality and nature of SAR imageries and diminishes the performance of SAR image processing. Thus, the multiplicative noise must be stifled before processing the image utilizing different image handling systems. Even though, there are number of speckle noise reduction techniques are available, all have its own merits and demerits. Therefore, noise reduction is still a major impediment in SAR image processing. In this paper, the speckle noise is reduced by using neural Network followed by the Bilateral Filter. This paper also presents the comparative analysis of two layered FFBPNN, TLFFBPNN and FLFFBPNN for speckle noise reduction of SAR images. Upon comparisons, it could be concluded that, TLFFBPNN de-speckling method provides good visual effects of SN reduction with better similarity and edging conservation metrics.","PeriodicalId":345324,"journal":{"name":"2023 Second International Conference on Electrical, Electronics, Information and Communication Technologies (ICEEICT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129358259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-05DOI: 10.1109/ICEEICT56924.2023.10157056
S. G, Sriraman S, Sruthilaya S, Ulagaraja J
Acoustic instruments produce sounds that are characterized by specific patterns and qualities, including harmonic content, attack, and decay, vibrato, resonance, and timbre. The creation and manipulation of instrumental sounds in various musical contexts are one of the most important features of acoustic instruments. Acoustic music is unamplified music that produces sound only by vibrating air and acoustic means, instead of through electronic or virtual instruments. Acoustic music emphasizes simplicity in its lyrics, harmonies, and melodies. The conversion of one musical instrumental chord to another musical instrumental chord is possible in acoustic instruments. In this paper, the Differentiable Digital Signal Processing technique is employed as a new approach to the realistic neural audio synthesis of musical instruments that combines the efficiency and interpretability of classical DSP elements such as filters, oscillators, reverberation, etc. The deep learning techniques are incorporated to train the model and produce harmonious music patterns. The generated music preserves the feature of the real play. The method also allows non-instrumentalists to process music. The model can be further developed to feed existing music. The preprocessed data is fed as input to obtain the desired instrumental chord or music.
{"title":"Orchestrate -A GAN Architectural-Based Pipeline for Musical Instrument Chord Conversion","authors":"S. G, Sriraman S, Sruthilaya S, Ulagaraja J","doi":"10.1109/ICEEICT56924.2023.10157056","DOIUrl":"https://doi.org/10.1109/ICEEICT56924.2023.10157056","url":null,"abstract":"Acoustic instruments produce sounds that are characterized by specific patterns and qualities, including harmonic content, attack, and decay, vibrato, resonance, and timbre. The creation and manipulation of instrumental sounds in various musical contexts are one of the most important features of acoustic instruments. Acoustic music is unamplified music that produces sound only by vibrating air and acoustic means, instead of through electronic or virtual instruments. Acoustic music emphasizes simplicity in its lyrics, harmonies, and melodies. The conversion of one musical instrumental chord to another musical instrumental chord is possible in acoustic instruments. In this paper, the Differentiable Digital Signal Processing technique is employed as a new approach to the realistic neural audio synthesis of musical instruments that combines the efficiency and interpretability of classical DSP elements such as filters, oscillators, reverberation, etc. The deep learning techniques are incorporated to train the model and produce harmonious music patterns. The generated music preserves the feature of the real play. The method also allows non-instrumentalists to process music. The model can be further developed to feed existing music. The preprocessed data is fed as input to obtain the desired instrumental chord or music.","PeriodicalId":345324,"journal":{"name":"2023 Second International Conference on Electrical, Electronics, Information and Communication Technologies (ICEEICT)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124636324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-05DOI: 10.1109/ICEEICT56924.2023.10157055
A. Dwivedi, Ratish Agarwal, P. Shukla
The increasing use of Internet of Things (IoT) devices in various applications has led to a growing concern about their security. Many IoT devices have limited resources such as processing power, memory, and energy, which makes them vulnerable to attacks. Encryption is a fundamental security mechanism that can be used to protect data in transit and at rest. However, traditional encryption algorithms are often too complex and resource-intensive for IoT devices. In this paper, we propose a lightweight encryption algorithm for IoT devices that is designed to provide a balance between security and resource efficiency. The Sym-BRLE (Binary Ring-Learning encryption) algorithm, based on the binary ring-learning with an error's encryption algorithm, has been proposed to improve random number selection and polynomial multiplication calculations to meet IoT communication requirements. In addition, the algorithm adds encryption security measures to achieve high security and efficiency for lightweight IoT devices. The Sym-BRLE algorithm has high communication efficiency and a small key size, and it can reduce total encryption time by 30% to 40% compared to other BRLE-based encryption algorithms. In addition, security analysis shows that Sym- BRLE can resist grid attacks, timing attacks, simple energy, and differential energy analyses.
{"title":"Post-Quantum Lightweight Encryption Algorithm for Internet of Things Devices","authors":"A. Dwivedi, Ratish Agarwal, P. Shukla","doi":"10.1109/ICEEICT56924.2023.10157055","DOIUrl":"https://doi.org/10.1109/ICEEICT56924.2023.10157055","url":null,"abstract":"The increasing use of Internet of Things (IoT) devices in various applications has led to a growing concern about their security. Many IoT devices have limited resources such as processing power, memory, and energy, which makes them vulnerable to attacks. Encryption is a fundamental security mechanism that can be used to protect data in transit and at rest. However, traditional encryption algorithms are often too complex and resource-intensive for IoT devices. In this paper, we propose a lightweight encryption algorithm for IoT devices that is designed to provide a balance between security and resource efficiency. The Sym-BRLE (Binary Ring-Learning encryption) algorithm, based on the binary ring-learning with an error's encryption algorithm, has been proposed to improve random number selection and polynomial multiplication calculations to meet IoT communication requirements. In addition, the algorithm adds encryption security measures to achieve high security and efficiency for lightweight IoT devices. The Sym-BRLE algorithm has high communication efficiency and a small key size, and it can reduce total encryption time by 30% to 40% compared to other BRLE-based encryption algorithms. In addition, security analysis shows that Sym- BRLE can resist grid attacks, timing attacks, simple energy, and differential energy analyses.","PeriodicalId":345324,"journal":{"name":"2023 Second International Conference on Electrical, Electronics, Information and Communication Technologies (ICEEICT)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128825465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-05DOI: 10.1109/ICEEICT56924.2023.10157552
Vanga Karunakar Reddy, Ravi Kumar Av
In this paper,. As we designed complexity circuit there may be any errors or faults. The faults may be stuck at ‘0’, stuck at ‘1'or may be a bridge fault. In order to identify the fault or error in circuit we need to verify each and every block to identify whether error or fault occurred. So to decrease the complexity of circuit and to identify error once after the design of circuit is completed. So to overcome the faults in circuit we are using self-checking multiplexer. Here we are designing self- repairing 2:1 multiplexer. By designing this circuit we can find and repair all kind of faults. In this paper proposing two methods in that the first method is detected and correct fault in Mux. Detect and correct faults in basic gates. New models can give 100% error accuracy. To design the proposed fast full adder here we are using hybrid logic style. This proposed method has been designed and analyzed using CMOS Mentor graphics 45nm Technology.
{"title":"Design and Simulation of Fault Tolerances in Combinational Circuits Using CMOS 45nm Technology","authors":"Vanga Karunakar Reddy, Ravi Kumar Av","doi":"10.1109/ICEEICT56924.2023.10157552","DOIUrl":"https://doi.org/10.1109/ICEEICT56924.2023.10157552","url":null,"abstract":"In this paper,. As we designed complexity circuit there may be any errors or faults. The faults may be stuck at ‘0’, stuck at ‘1'or may be a bridge fault. In order to identify the fault or error in circuit we need to verify each and every block to identify whether error or fault occurred. So to decrease the complexity of circuit and to identify error once after the design of circuit is completed. So to overcome the faults in circuit we are using self-checking multiplexer. Here we are designing self- repairing 2:1 multiplexer. By designing this circuit we can find and repair all kind of faults. In this paper proposing two methods in that the first method is detected and correct fault in Mux. Detect and correct faults in basic gates. New models can give 100% error accuracy. To design the proposed fast full adder here we are using hybrid logic style. This proposed method has been designed and analyzed using CMOS Mentor graphics 45nm Technology.","PeriodicalId":345324,"journal":{"name":"2023 Second International Conference on Electrical, Electronics, Information and Communication Technologies (ICEEICT)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127693162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-05DOI: 10.1109/ICEEICT56924.2023.10157091
Kandi Naveen, Vishnubhatla Sai Lakshmi Manonmai, Murala Sri Jaya Nikhitha, Vasireddy Pradeep, G. Kumar
In this concise a polar decoder form propagation based on belief is formulated which employ finite length LDPC systems. Here the belief sum-product Propagation (BP) is designed for LDPC system beyond affecting the binary communication erasure channels. Belief decoding is parallel and iterative in nature, as it own iteratively nature the required idleness and energy dissemination increments straightly. The prompt report stated that unstable node (VNs) is reduced during individual iteration than as BP. Declination of erased VNs reduces decoding process cause a forceful decrease in complexity, compared among polar decoder that is designed based on CSFG. CSFG is implemented with Quarter-way scheduling algorithm, a sub-factor graph reduces valuations of taken by belief decoder but due to different variable nodes used in the process it has large complication during design. To overcome this BPD with LDPC codes is designed. Simulation and synthesis results in the progressive art reveal that LDPC system drawn better in performance in contrast with belief based propagation.
{"title":"VLSI Architecture of a High Speed Polar Code Decoder using Finite Length Scaling LDPC Codes","authors":"Kandi Naveen, Vishnubhatla Sai Lakshmi Manonmai, Murala Sri Jaya Nikhitha, Vasireddy Pradeep, G. Kumar","doi":"10.1109/ICEEICT56924.2023.10157091","DOIUrl":"https://doi.org/10.1109/ICEEICT56924.2023.10157091","url":null,"abstract":"In this concise a polar decoder form propagation based on belief is formulated which employ finite length LDPC systems. Here the belief sum-product Propagation (BP) is designed for LDPC system beyond affecting the binary communication erasure channels. Belief decoding is parallel and iterative in nature, as it own iteratively nature the required idleness and energy dissemination increments straightly. The prompt report stated that unstable node (VNs) is reduced during individual iteration than as BP. Declination of erased VNs reduces decoding process cause a forceful decrease in complexity, compared among polar decoder that is designed based on CSFG. CSFG is implemented with Quarter-way scheduling algorithm, a sub-factor graph reduces valuations of taken by belief decoder but due to different variable nodes used in the process it has large complication during design. To overcome this BPD with LDPC codes is designed. Simulation and synthesis results in the progressive art reveal that LDPC system drawn better in performance in contrast with belief based propagation.","PeriodicalId":345324,"journal":{"name":"2023 Second International Conference on Electrical, Electronics, Information and Communication Technologies (ICEEICT)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126990702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-05DOI: 10.1109/ICEEICT56924.2023.10157495
Nithia Shree A C, M. R, Arul A, S. Ramesh
This study examines two different forms of energy-saving and rapid voltage level changers are designed in this research. This article provides comprehensive information on logic down shifters and logic up shifter. The placement of level shifter plays crucial role, the low to high level shifters requires single supply voltage whereas high to low level shifter requires dual supply voltage. Level shifters have been developed using gpdk 45nm technology. The level changer design described in this paper can transform input voltages from sub-threshold levels to the desired voltage supply. The level shifter can convert high voltage (VVDH) to low voltage (VVDL) and vice versa. The level shifter designed here using Widlar current mirror instead of Wilson current mirror. Due to the development of highly efficient and low power consumption application, it is important to manage a complex circuit with minimal power consumption to achieve, the best method for lowering system-level power usage is multi supply voltage domain. For interconnection of ICs and to avoid static current and to accommodate supply voltage configurations, level translators (LSs) must be used. The designed level shifters are simulated using Cadence tool
{"title":"Low power and high speed level translator using Widlar topology","authors":"Nithia Shree A C, M. R, Arul A, S. Ramesh","doi":"10.1109/ICEEICT56924.2023.10157495","DOIUrl":"https://doi.org/10.1109/ICEEICT56924.2023.10157495","url":null,"abstract":"This study examines two different forms of energy-saving and rapid voltage level changers are designed in this research. This article provides comprehensive information on logic down shifters and logic up shifter. The placement of level shifter plays crucial role, the low to high level shifters requires single supply voltage whereas high to low level shifter requires dual supply voltage. Level shifters have been developed using gpdk 45nm technology. The level changer design described in this paper can transform input voltages from sub-threshold levels to the desired voltage supply. The level shifter can convert high voltage (VVDH) to low voltage (VVDL) and vice versa. The level shifter designed here using Widlar current mirror instead of Wilson current mirror. Due to the development of highly efficient and low power consumption application, it is important to manage a complex circuit with minimal power consumption to achieve, the best method for lowering system-level power usage is multi supply voltage domain. For interconnection of ICs and to avoid static current and to accommodate supply voltage configurations, level translators (LSs) must be used. The designed level shifters are simulated using Cadence tool","PeriodicalId":345324,"journal":{"name":"2023 Second International Conference on Electrical, Electronics, Information and Communication Technologies (ICEEICT)","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116203779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-05DOI: 10.1109/ICEEICT56924.2023.10157169
K. Sankaran, M. Pradeepa, C. Chandra
Denoising is critical in medical imaging for the study of pictures, the diagnosis and treatment of illness. Image denoising approaches based on optimization are now effective, however the methods are constrained by the need for a large training set size (i.e., not successful enough for small data size). Medical picture denoising may be accomplished using the discrete wavelet transform (DWT) and a coefficient thresholding-based BAT method (CTB BAT). Denoising images by removing a residual from a noisy image yields denoised images, while most other image denoising methods start with latent clean images and work their way up to learning noise from the noisy images. Additionally, the wavelet transform is incorporated with CTB_ BAT to increase model learning accuracy and training time. Denoising strategies are compared to our model's performance in terms of peak signal-to-noise ratio and structural similarity in order to determine how well it performs compared to other medical picture denoising approaches. Our methodology outperforms other approaches in experiments, as shown by the findings.
{"title":"Medical Image Denoising Using BAT Optimization Algorithm","authors":"K. Sankaran, M. Pradeepa, C. Chandra","doi":"10.1109/ICEEICT56924.2023.10157169","DOIUrl":"https://doi.org/10.1109/ICEEICT56924.2023.10157169","url":null,"abstract":"Denoising is critical in medical imaging for the study of pictures, the diagnosis and treatment of illness. Image denoising approaches based on optimization are now effective, however the methods are constrained by the need for a large training set size (i.e., not successful enough for small data size). Medical picture denoising may be accomplished using the discrete wavelet transform (DWT) and a coefficient thresholding-based BAT method (CTB BAT). Denoising images by removing a residual from a noisy image yields denoised images, while most other image denoising methods start with latent clean images and work their way up to learning noise from the noisy images. Additionally, the wavelet transform is incorporated with CTB_ BAT to increase model learning accuracy and training time. Denoising strategies are compared to our model's performance in terms of peak signal-to-noise ratio and structural similarity in order to determine how well it performs compared to other medical picture denoising approaches. Our methodology outperforms other approaches in experiments, as shown by the findings.","PeriodicalId":345324,"journal":{"name":"2023 Second International Conference on Electrical, Electronics, Information and Communication Technologies (ICEEICT)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125340284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-05DOI: 10.1109/ICEEICT56924.2023.10156983
Yesudasu Paila, Ravi Raja A, N. S. P. Revathi Nuvvula, R. L. Durga Prasad Pandi, Pujitha Kodali, Sivarama Krishna Reddy Vanga
The Electrocardiogram (ECG), one of the biological signals, can be utilized to identify heart arrhythmias. Detecting a single irregular heartbeat that can occur alone or in repetition helps in discovering an arrhythmia. Early detection of arrhythmias and taking necessary precautions can help cure or prevent life-threatening arrhythmias. Depending on the shape and features of ECG, they are categorized into multiple arrhythmias and grouped as classes based on their threat level, such as Unknown Beats (Q), Supraventricular Ectopic Beat (SVEB), Fusion Beat (F), Ventricular Ectopic Beat (VEB) and Non-ectopic Beat (N). The openly accessible Massachusetts Institute of Technology-Beth Israel Hospital(MIT-BIH) database is considered in this paper. Three stages are suggested for detection. The first stage is pre-processing, which is done by the 1-Dimensional Wavelet Discrete Transform (1D-DWT) method. The second stage is feature extraction, carried out by the Empirical Mode Decomposition (EMD) method. Features now extracted are then fed for the classifiers. Deep Neural Network (DNN) is capable of automatically extracting features and analyzing data patterns, eliminating the need for complex signal processing. For the classification stage, the dataset considered has 20% test data and 80% trained data. The Deep Learning (DL) originated Convolutional Neural Network (CNN) is compared with K-Nearest Neighbor (KNN) algorithm, which is originated from Machine Learning (ML) for secondary confirmation. These classifiers achieved a Maximum Accuracy (MAAC) of 90.87%, Maximum Sensitivity (MASE) of 90.56%, and Maximum Specificity (MASP) of 91.18% with KNN, and a MAAC of 93.8%, MASE of 92.52%, and MASP of 95.08% with the CNN classifier.
{"title":"Detection and Analysis of Cardiac Arrhythmias from Heartbeat Classification","authors":"Yesudasu Paila, Ravi Raja A, N. S. P. Revathi Nuvvula, R. L. Durga Prasad Pandi, Pujitha Kodali, Sivarama Krishna Reddy Vanga","doi":"10.1109/ICEEICT56924.2023.10156983","DOIUrl":"https://doi.org/10.1109/ICEEICT56924.2023.10156983","url":null,"abstract":"The Electrocardiogram (ECG), one of the biological signals, can be utilized to identify heart arrhythmias. Detecting a single irregular heartbeat that can occur alone or in repetition helps in discovering an arrhythmia. Early detection of arrhythmias and taking necessary precautions can help cure or prevent life-threatening arrhythmias. Depending on the shape and features of ECG, they are categorized into multiple arrhythmias and grouped as classes based on their threat level, such as Unknown Beats (Q), Supraventricular Ectopic Beat (SVEB), Fusion Beat (F), Ventricular Ectopic Beat (VEB) and Non-ectopic Beat (N). The openly accessible Massachusetts Institute of Technology-Beth Israel Hospital(MIT-BIH) database is considered in this paper. Three stages are suggested for detection. The first stage is pre-processing, which is done by the 1-Dimensional Wavelet Discrete Transform (1D-DWT) method. The second stage is feature extraction, carried out by the Empirical Mode Decomposition (EMD) method. Features now extracted are then fed for the classifiers. Deep Neural Network (DNN) is capable of automatically extracting features and analyzing data patterns, eliminating the need for complex signal processing. For the classification stage, the dataset considered has 20% test data and 80% trained data. The Deep Learning (DL) originated Convolutional Neural Network (CNN) is compared with K-Nearest Neighbor (KNN) algorithm, which is originated from Machine Learning (ML) for secondary confirmation. These classifiers achieved a Maximum Accuracy (MAAC) of 90.87%, Maximum Sensitivity (MASE) of 90.56%, and Maximum Specificity (MASP) of 91.18% with KNN, and a MAAC of 93.8%, MASE of 92.52%, and MASP of 95.08% with the CNN classifier.","PeriodicalId":345324,"journal":{"name":"2023 Second International Conference on Electrical, Electronics, Information and Communication Technologies (ICEEICT)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126493953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-05DOI: 10.1109/ICEEICT56924.2023.10156915
K. Kousalya, K Dinesh, B. Krishnakumar, K. G, Kowsika C, Ponmathi K
Data analyzing is the process of analyzing the dataset to make inferences from the information available. The main aim is to apply statistical analysis and technologies on data to solve problems. Thus, researchers introduce various algorithms for analysis the data. But the existing algorithms have not achieve the expected outcome. Thus, the proposed work also addresses to the improve the mechanism for analysis the dataset for the prediction of an optimal algorithm for diagnosis of Chronic Obstructive Pulmonary Disease (COPD). Airflow into and out of the lungs is impeded by COPD. Long-term exposure to irritating gases or particles, most typically from cigarette smoke, is frequently the cause. People with COPD have a higher risk of developing heart disease, lung cancer, and a variety of other disorders. Here this work compares various machine learning algorithms for the huge volume of medical data with multiple attributes. The objective is to predict the algorithm which has the highest accuracy. With the help of analytics of the chosen dataset, the above-mentioned models are deployed and compared for the prediction of the algorithm with the highest accuracy rate of 97%.
{"title":"Prediction of Optimal Algorithm For Diagnosis of Chronic Obstructive Pulmonary Disease","authors":"K. Kousalya, K Dinesh, B. Krishnakumar, K. G, Kowsika C, Ponmathi K","doi":"10.1109/ICEEICT56924.2023.10156915","DOIUrl":"https://doi.org/10.1109/ICEEICT56924.2023.10156915","url":null,"abstract":"Data analyzing is the process of analyzing the dataset to make inferences from the information available. The main aim is to apply statistical analysis and technologies on data to solve problems. Thus, researchers introduce various algorithms for analysis the data. But the existing algorithms have not achieve the expected outcome. Thus, the proposed work also addresses to the improve the mechanism for analysis the dataset for the prediction of an optimal algorithm for diagnosis of Chronic Obstructive Pulmonary Disease (COPD). Airflow into and out of the lungs is impeded by COPD. Long-term exposure to irritating gases or particles, most typically from cigarette smoke, is frequently the cause. People with COPD have a higher risk of developing heart disease, lung cancer, and a variety of other disorders. Here this work compares various machine learning algorithms for the huge volume of medical data with multiple attributes. The objective is to predict the algorithm which has the highest accuracy. With the help of analytics of the chosen dataset, the above-mentioned models are deployed and compared for the prediction of the algorithm with the highest accuracy rate of 97%.","PeriodicalId":345324,"journal":{"name":"2023 Second International Conference on Electrical, Electronics, Information and Communication Technologies (ICEEICT)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129084086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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