Pub Date : 2000-09-11DOI: 10.1109/ESSDERC.2000.194781
C. Detcheverry, M. Matters
This paper presents an analytical model which describes the device characteristics of all-polymer thin-film transistors with channel lengths in the range of 5 to 20 μm. The model contains a limited number of parameters and can be easily implemented in a circuit simulator. In particular, the description of the mobility in the model includes the experimentally observed dependence of the mobility on the gate
{"title":"Device simulation of all-polymer thin-film transistors","authors":"C. Detcheverry, M. Matters","doi":"10.1109/ESSDERC.2000.194781","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194781","url":null,"abstract":"This paper presents an analytical model which describes the device characteristics of all-polymer thin-film transistors with channel lengths in the range of 5 to 20 μm. The model contains a limited number of parameters and can be easily implemented in a circuit simulator. In particular, the description of the mobility in the model includes the experimentally observed dependence of the mobility on the gate","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123817740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-11DOI: 10.1109/ESSDERC.2000.194753
C. Bermond, B. Fléchet, G. Le Carval, F. Charlet, Y. Morand, G. Angénieux, R. Salik
A full procedure to measure and simulate or predict high speed performance of single or coupled long-lossy IC interconnects is presented. Propagation constant, characteristic impedance and R, L, C, G matrix parameters are extracted from measurements and compared to values obtained by EM modeling. Next, performance in terms of delays, distortion or crosstalk of high speed signals are studied : impacts of low-K dielectrics and Al-Cu or Cu-CMP processes are shown.
{"title":"Performance Characterization of Advanced Interconnects on High Speed VLSI Circuits","authors":"C. Bermond, B. Fléchet, G. Le Carval, F. Charlet, Y. Morand, G. Angénieux, R. Salik","doi":"10.1109/ESSDERC.2000.194753","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194753","url":null,"abstract":"A full procedure to measure and simulate or predict high speed performance of single or coupled long-lossy IC interconnects is presented. Propagation constant, characteristic impedance and R, L, C, G matrix parameters are extracted from measurements and compared to values obtained by EM modeling. Next, performance in terms of delays, distortion or crosstalk of high speed signals are studied : impacts of low-K dielectrics and Al-Cu or Cu-CMP processes are shown.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115003025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-11DOI: 10.1109/ESSDERC.2000.194812
P. Steinmann, S. M. Jacobsen, R. Higgins
We demonstrate that the temperature coefficient of resistance (TCR) of NiCr thin film resistors can be effectively controlled by changing the film thickness over a certain range. We have observed a direct dependency between TCR and sheet resistance, which can be expressed by the equation: TCR(in ppm/C)=525*exp(0.01*sheet (in Ohms/sq)). This behavior can be explained by considering the transition from a bulk conductivity mechanism to a mechanism dominated by charge carrier creation and tunneling between metallic islands.
{"title":"Controlling the TCR of thin film resistors","authors":"P. Steinmann, S. M. Jacobsen, R. Higgins","doi":"10.1109/ESSDERC.2000.194812","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194812","url":null,"abstract":"We demonstrate that the temperature coefficient of resistance (TCR) of NiCr thin film resistors can be effectively controlled by changing the film thickness over a certain range. We have observed a direct dependency between TCR and sheet resistance, which can be expressed by the equation: TCR(in ppm/C)=525*exp(0.01*sheet (in Ohms/sq)). This behavior can be explained by considering the transition from a bulk conductivity mechanism to a mechanism dominated by charge carrier creation and tunneling between metallic islands.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130932311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-11DOI: 10.1109/ESSDERC.2000.194843
P. Woerlee, M. J. Knitel, R. V. Langevelde, D. Klaassen, L. Tiemeijer, A. Scholten, A. Z. Duijnhoven
The impact of scaling on the analog performance of MOS devices at RF frequencies was studied. Trends in the RF performance of nominal gate length NMOS devices from 350-nm to 50-nm CMOS technologies are presented. Both experimental data and circuit simulations with an advanced validated compact model (MOS Model 11) have been used to evaluate the RF performance. RF performance metrics such as the cutoff frequency, maximum oscillation frequency, power gain, noise figure, linearity, and 1 noise were included in the analysis. The focus of the study was on gate and drain bias conditions relevant for RF circuit design. A scaling methodology for RF-CMOS based on limited linearity degradation is proposed.
{"title":"RF-CMOS Performance Trends","authors":"P. Woerlee, M. J. Knitel, R. V. Langevelde, D. Klaassen, L. Tiemeijer, A. Scholten, A. Z. Duijnhoven","doi":"10.1109/ESSDERC.2000.194843","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194843","url":null,"abstract":"The impact of scaling on the analog performance of MOS devices at RF frequencies was studied. Trends in the RF performance of nominal gate length NMOS devices from 350-nm to 50-nm CMOS technologies are presented. Both experimental data and circuit simulations with an advanced validated compact model (MOS Model 11) have been used to evaluate the RF performance. RF performance metrics such as the cutoff frequency, maximum oscillation frequency, power gain, noise figure, linearity, and 1 noise were included in the analysis. The focus of the study was on gate and drain bias conditions relevant for RF circuit design. A scaling methodology for RF-CMOS based on limited linearity degradation is proposed.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134071204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-11DOI: 10.1109/ESSDERC.2000.194716
U. Schwalke
This contribution briefly reviews the current status on device isolation technology. Starting with conventional shallow-trench-isolation (STI), the challenges introduced by this approach are outlined. Based on this discussion, the concept of the recently developed extended trench isolation gate technology (EXTIGATE) is presented. It will be shown that EXTIGATE not only provides a relief from the drawbacks of conventional STI processing, but also offers promising alternatives for front-end process integration, device optimization and specific applications.
{"title":"Challenges and Recent Developments in Device Isolation Technology","authors":"U. Schwalke","doi":"10.1109/ESSDERC.2000.194716","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194716","url":null,"abstract":"This contribution briefly reviews the current status on device isolation technology. Starting with conventional shallow-trench-isolation (STI), the challenges introduced by this approach are outlined. Based on this discussion, the concept of the recently developed extended trench isolation gate technology (EXTIGATE) is presented. It will be shown that EXTIGATE not only provides a relief from the drawbacks of conventional STI processing, but also offers promising alternatives for front-end process integration, device optimization and specific applications.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129786240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-11DOI: 10.1109/ESSDERC.2000.194768
G. Ghidini, F. Pellizzer, N. Galbiati, D. Brazzelli, D. Peschiaroli, L. Brusaferri
{"title":"Plasma Damage Impact in 0.25 um Dual-Gate Technology","authors":"G. Ghidini, F. Pellizzer, N. Galbiati, D. Brazzelli, D. Peschiaroli, L. Brusaferri","doi":"10.1109/ESSDERC.2000.194768","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194768","url":null,"abstract":"","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132553047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-11DOI: 10.1109/ESSDERC.2000.194830
K. Cheung, A. Kamgar
Common ESD protection devices have a snap-back characteristic similar to a siliconcontrol-rectifier. The transient voltage required to trigger these devices usually is not an important design criterion as long as it is not too high. We show that when gate-oxide is thin, this voltage transient creates far more defects in the gate-oxide than the main ESD event clamped at the holding voltage. Due to difficulty in measurement, this oxide reliability degradation can lead to chip failure but not show up in simulated ESD test.
{"title":"ESD protection in deep submicron CMOS technology -- Does the transient matter?","authors":"K. Cheung, A. Kamgar","doi":"10.1109/ESSDERC.2000.194830","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194830","url":null,"abstract":"Common ESD protection devices have a snap-back characteristic similar to a siliconcontrol-rectifier. The transient voltage required to trigger these devices usually is not an important design criterion as long as it is not too high. We show that when gate-oxide is thin, this voltage transient creates far more defects in the gate-oxide than the main ESD event clamped at the holding voltage. Due to difficulty in measurement, this oxide reliability degradation can lead to chip failure but not show up in simulated ESD test.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130059317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-11DOI: 10.1109/ESSDERC.2000.194802
E. Quevy, L. Buchaillot, P. Bigotte, D. Collard
3D Polysilicon micro-parts are self-assembled by beam buckling induced by integrated Scratch Drive Actuator (SDA). With this technique, 380*250 μm2 micro-mirror were lifted 90 μm above the substrate plane. The 3D shapes were permanently kept by 2 different ways: i) mechanical locking produced by integrated clips and ii) electric field induced stiction. Subsequent to the assembling, micro-mirrors are successfully actuated by biasing underneath buried electrodes. Controlled motion up to +/15 ̊ rotation was successfully obtained even for long term experiments. This paper reports for the first time on the actuation of permanent 3D self-assembled micro-mirror for beam steering application.
{"title":"3D self-assembling and actuation of electrostatic micro-mirrors","authors":"E. Quevy, L. Buchaillot, P. Bigotte, D. Collard","doi":"10.1109/ESSDERC.2000.194802","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194802","url":null,"abstract":"3D Polysilicon micro-parts are self-assembled by beam buckling induced by integrated Scratch Drive Actuator (SDA). With this technique, 380*250 μm2 micro-mirror were lifted 90 μm above the substrate plane. The 3D shapes were permanently kept by 2 different ways: i) mechanical locking produced by integrated clips and ii) electric field induced stiction. Subsequent to the assembling, micro-mirrors are successfully actuated by biasing underneath buried electrodes. Controlled motion up to +/15 ̊ rotation was successfully obtained even for long term experiments. This paper reports for the first time on the actuation of permanent 3D self-assembled micro-mirror for beam steering application.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"53 24","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113973903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-11DOI: 10.1109/ESSDERC.2000.194762
K. Kieschnick, H. Zimmermann, P. Seegebrecht, H. Pless
An n /p-well/p-substrate photodiode (NPD) and an n /n-well/p-substrate photodiode (NND) on standard epitaxial and low doped epitaxial material were implemented in an industrial BiCMOS process. Both devices are fully BiCMOS compatible, so that no process modifications were necessary. A dB bandwidth of more than MHz was measured for the NND ( nm). Due to the modification of the epitaxial material the bandwidth of the NND is enhanced for nm, leading to a photodiode which is appropriate simultaneously for advanced CD-ROM and DVD applications.
{"title":"Integrated Photodiodes for DVD and CD-ROM Applications","authors":"K. Kieschnick, H. Zimmermann, P. Seegebrecht, H. Pless","doi":"10.1109/ESSDERC.2000.194762","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194762","url":null,"abstract":"An n /p-well/p-substrate photodiode (NPD) and an n /n-well/p-substrate photodiode (NND) on standard epitaxial and low doped epitaxial material were implemented in an industrial BiCMOS process. Both devices are fully BiCMOS compatible, so that no process modifications were necessary. A dB bandwidth of more than MHz was measured for the NND ( nm). Due to the modification of the epitaxial material the bandwidth of the NND is enhanced for nm, leading to a photodiode which is appropriate simultaneously for advanced CD-ROM and DVD applications.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132269729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-11DOI: 10.1109/ESSDERC.2000.194727
F. Nouri, G. Scott, M. Rubin, M. Manley, P. Stolk
Shallow Trench Isolation (STI) has been the isolation scheme of choice for sub0.25μm technologies. One of the challenges of scaling STI to 0.13μm and beyond is the control of Vt and Idsat of narrow devices. In this paper, we show that Idsat of narrow devices is strongly impacted by the stress due to trench processing. We also show that Vt and leakage of narrow devices (in particular NMOS devices) is impacted by dopant redistribution in the channel caused by TED (Transient Enhanced Diffusion) and boron segregation to the trench sidewalls.
{"title":"Narrow Device Issues in Deep-Submicron Technologies-the Influence of Stress, TED and Segregation on Device Performance","authors":"F. Nouri, G. Scott, M. Rubin, M. Manley, P. Stolk","doi":"10.1109/ESSDERC.2000.194727","DOIUrl":"https://doi.org/10.1109/ESSDERC.2000.194727","url":null,"abstract":"Shallow Trench Isolation (STI) has been the isolation scheme of choice for sub0.25μm technologies. One of the challenges of scaling STI to 0.13μm and beyond is the control of Vt and Idsat of narrow devices. In this paper, we show that Idsat of narrow devices is strongly impacted by the stress due to trench processing. We also show that Vt and leakage of narrow devices (in particular NMOS devices) is impacted by dopant redistribution in the channel caused by TED (Transient Enhanced Diffusion) and boron segregation to the trench sidewalls.","PeriodicalId":354721,"journal":{"name":"30th European Solid-State Device Research Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128096061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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