Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188701
V. Tomashau
Finite field arithmetic is the basis of some cryptographic and error correction algorithms. The performance of a corresponding hardware depends on the efficiency of the finite field arithmetic implementation. A good-quality finite field multiplier is needed first, since multiplication is an often-used and time consuming operation. Because FPGAs differ considerably in structure from other integrated circuits, the finite field multiplier designs, which are optimized for VLSI implementation, do not perform well on FPGAs. In this paper, some structures of a completely combinatorial GF(16) multiplier, based on 4-input LUTs and some other resources of the Xilinx FPGA, have been proposed. As a result, some improvement in area and time has been achieved by comparison with previous designs.
{"title":"Efficient 4-input LUTs FPGA implementation of combinatorial multiplier over canonical base GF(16)","authors":"V. Tomashau","doi":"10.1109/FPT.2002.1188701","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188701","url":null,"abstract":"Finite field arithmetic is the basis of some cryptographic and error correction algorithms. The performance of a corresponding hardware depends on the efficiency of the finite field arithmetic implementation. A good-quality finite field multiplier is needed first, since multiplication is an often-used and time consuming operation. Because FPGAs differ considerably in structure from other integrated circuits, the finite field multiplier designs, which are optimized for VLSI implementation, do not perform well on FPGAs. In this paper, some structures of a completely combinatorial GF(16) multiplier, based on 4-input LUTs and some other resources of the Xilinx FPGA, have been proposed. As a result, some improvement in area and time has been achieved by comparison with previous designs.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125667986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188683
Shih-Liang Chen, TingTing Hwang, C. Liu
In this paper, we propose a technology mapping algorithm for CPLD architectures. Our algorithm proceeds in two phases: mapping for single-output PLAs and packing for multiple-output PLAs. In the mapping phase we propose a look-up-table (LUT) based mapping algorithm. We will take advantage of existing LUT mapping algorithms for area and depth minimization. Benchmark results show that our algorithm produce better results in terms of area and depth as compared to TEMPLA.
{"title":"A technology mapping algorithm for CPLD architectures","authors":"Shih-Liang Chen, TingTing Hwang, C. Liu","doi":"10.1109/FPT.2002.1188683","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188683","url":null,"abstract":"In this paper, we propose a technology mapping algorithm for CPLD architectures. Our algorithm proceeds in two phases: mapping for single-output PLAs and packing for multiple-output PLAs. In the mapping phase we propose a look-up-table (LUT) based mapping algorithm. We will take advantage of existing LUT mapping algorithms for area and depth minimization. Benchmark results show that our algorithm produce better results in terms of area and depth as compared to TEMPLA.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130520062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188682
Minoru Watanabe, F. Kobayashi
A new optically differential reconfigurable gate array (ODRGA) is proposed to reduce configuration power consumption. The ODRGA has a simple architecture that adds a small circuit to conventional optically reconfigurable gate arrays (ORGAs) and uses differential configuration data stored in an optical holographic memory. In this paper configuration power consumption of ORGAs is estimated theoretically. Based on results, we show an estimation of configuration power consumption and comparative area occupied by the configuration circuit for ODRGA and conventional ORGAs.
{"title":"An optically differential reconfigurable gate array and its power consumption estimation","authors":"Minoru Watanabe, F. Kobayashi","doi":"10.1109/FPT.2002.1188682","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188682","url":null,"abstract":"A new optically differential reconfigurable gate array (ODRGA) is proposed to reduce configuration power consumption. The ODRGA has a simple architecture that adds a small circuit to conventional optically reconfigurable gate arrays (ORGAs) and uses differential configuration data stored in an optical holographic memory. In this paper configuration power consumption of ORGAs is estimated theoretically. Based on results, we show an estimation of configuration power consumption and comparative area occupied by the configuration circuit for ODRGA and conventional ORGAs.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128390852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188730
K. K. Poon, S. Wilton
Power dissipation is becoming a major concern among FPGA vendors. Recently, architectural studies have been published which attempt to quantify the effects of various architectural alternatives on the power dissipation of FPGAs. These studies are very sensitive to assumptions made during the experimentation. In this paper, we analyze the sensitivity of two of these assumptions: the primary input density and the routing algorithm. We show that both of these assumptions significantly impact the architectural results.
{"title":"Sensitivity of FPGA power evaluation","authors":"K. K. Poon, S. Wilton","doi":"10.1109/FPT.2002.1188730","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188730","url":null,"abstract":"Power dissipation is becoming a major concern among FPGA vendors. Recently, architectural studies have been published which attempt to quantify the effects of various architectural alternatives on the power dissipation of FPGAs. These studies are very sensitive to assumptions made during the experimentation. In this paper, we analyze the sensitivity of two of these assumptions: the primary input density and the routing algorithm. We show that both of these assumptions significantly impact the architectural results.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133531878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188723
Dong-U Lee, T. K. Lee, W. Luk, P. Cheung
We present an incremental approach to developing programs for reconfigurable engines, systems which contain both instruction processors and reconfigurable hardware. The purpose is to support rapid production of prototypes, as well as their further systematic refinement and adaptation when required. The key elements of our approach include abstractions and tools based on high-level descriptions, and facilities for optimizations such as domain-specific data partitioning and run-time reconfiguration. The application of our approach is illustrated using the SONIC reconfigurable engine, which contains a multi-FPGA card in a PC system designed for video image processing.
{"title":"Incremental programming for reconfigurable engines","authors":"Dong-U Lee, T. K. Lee, W. Luk, P. Cheung","doi":"10.1109/FPT.2002.1188723","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188723","url":null,"abstract":"We present an incremental approach to developing programs for reconfigurable engines, systems which contain both instruction processors and reconfigurable hardware. The purpose is to support rapid production of prototypes, as well as their further systematic refinement and adaptation when required. The key elements of our approach include abstractions and tools based on high-level descriptions, and facilities for optimizations such as domain-specific data partitioning and run-time reconfiguration. The application of our approach is illustrated using the SONIC reconfigurable engine, which contains a multi-FPGA card in a PC system designed for video image processing.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128102900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188685
A. Ye, Jonathan Rose, D. Lewis
Large circuits, whether they are arithmetic, digital signal processing, switching, or processors, typically contain a greater portion of highly regular datapath logic. Datapath synthesis algorithms preserve these regular structures, so they can be exploited by packing, placement, and routing tools for speed or density. Typical datapath synthesis algorithms, however, sacrifice area to gain regularity. Current algorithms can have as much as 30% to 40% area inflation when compared with traditional flat synthesis algorithms. This paper describes a datapath synthesis algorithm with very low area overhead, which is an enhancement to the module compaction algorithm. We propose two word-level optimizations - multiplexer tree collapsing and operation reordering. They reduce the area inflation to 3%-8% as compared with flat synthesis. Our synthesis results also retain significant amount of regularity from the original designs.
{"title":"Synthesizing datapath circuits for FPGAs with emphasis on area minimization","authors":"A. Ye, Jonathan Rose, D. Lewis","doi":"10.1109/FPT.2002.1188685","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188685","url":null,"abstract":"Large circuits, whether they are arithmetic, digital signal processing, switching, or processors, typically contain a greater portion of highly regular datapath logic. Datapath synthesis algorithms preserve these regular structures, so they can be exploited by packing, placement, and routing tools for speed or density. Typical datapath synthesis algorithms, however, sacrifice area to gain regularity. Current algorithms can have as much as 30% to 40% area inflation when compared with traditional flat synthesis algorithms. This paper describes a datapath synthesis algorithm with very low area overhead, which is an enhancement to the module compaction algorithm. We propose two word-level optimizations - multiplexer tree collapsing and operation reordering. They reduce the area inflation to 3%-8% as compared with flat synthesis. Our synthesis results also retain significant amount of regularity from the original designs.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126194569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188693
C. Torres-Huitzil, S. Maya-Rueda, M. Arias-Estrada
Recently, a growing community of researchers has used reconfigurable hardware systems to solve computationally intensive problems. Reconfigurability provides optimised processors for systems on chip designs, and makes easy to import technology to a new system through reusable modules. The main objective of this work is the investigation of a reconfigurable computer system targeted for real-time computer vision applications. The system is intended to circumvent the inherent computational load of most window-based computer vision algorithms. It aims to build a system for such tasks by providing an FPGA-based hardware architecture. Some preliminary results are presented and discussed.
{"title":"A reconfigurable vision system for real-time applications","authors":"C. Torres-Huitzil, S. Maya-Rueda, M. Arias-Estrada","doi":"10.1109/FPT.2002.1188693","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188693","url":null,"abstract":"Recently, a growing community of researchers has used reconfigurable hardware systems to solve computationally intensive problems. Reconfigurability provides optimised processors for systems on chip designs, and makes easy to import technology to a new system through reusable modules. The main objective of this work is the investigation of a reconfigurable computer system targeted for real-time computer vision applications. The system is intended to circumvent the inherent computational load of most window-based computer vision algorithms. It aims to build a system for such tasks by providing an FPGA-based hardware architecture. Some preliminary results are presented and discussed.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130166353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188684
J. Anderson, F. Najm
We present a new power-aware technology mapping technique for LUT-based FPGAs which aims to keep nets with high switching activity out of the FPGA routing network and takes an activity-conscious approach to logic replication. Logic replication is known to be crucial for optimizing depth in technology mapping; an important contribution of our work is to recognize the effect of logic replication on circuit structure and to show its consequences on power. In an experimental study, we examine the power characteristics of mapping solutions generated by several publicly available technology mappers. Results show that for a specific depth of mapping solution, the power consumption can vary considerably, depending on the technology mapping approach used. Furthermore, results show that our proposed mapping algorithm leads to circuits with substantially less power dissipation than previous approaches.
{"title":"Power-aware technology mapping for LUT-based FPGAs","authors":"J. Anderson, F. Najm","doi":"10.1109/FPT.2002.1188684","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188684","url":null,"abstract":"We present a new power-aware technology mapping technique for LUT-based FPGAs which aims to keep nets with high switching activity out of the FPGA routing network and takes an activity-conscious approach to logic replication. Logic replication is known to be crucial for optimizing depth in technology mapping; an important contribution of our work is to recognize the effect of logic replication on circuit structure and to show its consequences on power. In an experimental study, we examine the power characteristics of mapping solutions generated by several publicly available technology mappers. Results show that for a specific depth of mapping solution, the power consumption can vary considerably, depending on the technology mapping approach used. Furthermore, results show that our proposed mapping algorithm leads to circuits with substantially less power dissipation than previous approaches.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129283811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188690
P. Beckett
A fine-grained reconfigurable architecture based on double gate technology is presented. The logic function operating on the first gate of a double gate (DG) transistor is reconfigured by altering the bias on its second gate. A compact reconfigurable cell is proposed that merges two stacked 3-state resonant tunneling devices and non-silicon transistors and "hides" the cost of reconfiguration by exploiting vertical integration. Each cell in the array can act as logic or interconnect, or both - contrasting with current FPGA structures in which logic and interconnect are built and configured largely as separate items. Simulation results for a SOI DG-MOSFET implementation is presented and two alternative non-silicon device technologies, metal-insulator-metal and carbon nanotube transistors, are briefly explored Of these, carbon nanotube devices appear to offer the highest current drive at the limit of scaling and will operate into the gigahertz range but then only within architectures that are locally connected.
{"title":"A fine-grained reconfigurable logic array based on double gate transistors","authors":"P. Beckett","doi":"10.1109/FPT.2002.1188690","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188690","url":null,"abstract":"A fine-grained reconfigurable architecture based on double gate technology is presented. The logic function operating on the first gate of a double gate (DG) transistor is reconfigured by altering the bias on its second gate. A compact reconfigurable cell is proposed that merges two stacked 3-state resonant tunneling devices and non-silicon transistors and \"hides\" the cost of reconfiguration by exploiting vertical integration. Each cell in the array can act as logic or interconnect, or both - contrasting with current FPGA structures in which logic and interconnect are built and configured largely as separate items. Simulation results for a SOI DG-MOSFET implementation is presented and two alternative non-silicon device technologies, metal-insulator-metal and carbon nanotube transistors, are briefly explored Of these, carbon nanotube devices appear to offer the highest current drive at the limit of scaling and will operate into the gigahertz range but then only within architectures that are locally connected.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123960253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188658
P. Lysaght
Platform-based design is one of the key strategies that is promoted for successfully coping with the most complex, system-on-chip designs. Its basic premise is that the levels of design productivity needed to counter the intrinsic complexity of such embedded systems will only be achieved by extensive, planned design re-use. The platform concept originated with ASICs but evolved rapidly to FPGAs. In this paper, we investigate the phenomenon of FPGA platforms using the Xilinx Virtex/spl trade/-II Pro series of Platform FPGAs as our reference model. We identify and categorize their principal characteristics and seek to differentiate them from their ASIC predecessors. We make the case for regarding Platform FPGAs as meta-platforms because of the extent to which they extend the original concept of platform-based design. Looking forward, we offer some conjectures as to the nature of future FPGA platforms and some of the challenges that researchers will face.
{"title":"FPGAs as meta-platforms for embedded systems","authors":"P. Lysaght","doi":"10.1109/FPT.2002.1188658","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188658","url":null,"abstract":"Platform-based design is one of the key strategies that is promoted for successfully coping with the most complex, system-on-chip designs. Its basic premise is that the levels of design productivity needed to counter the intrinsic complexity of such embedded systems will only be achieved by extensive, planned design re-use. The platform concept originated with ASICs but evolved rapidly to FPGAs. In this paper, we investigate the phenomenon of FPGA platforms using the Xilinx Virtex/spl trade/-II Pro series of Platform FPGAs as our reference model. We identify and categorize their principal characteristics and seek to differentiate them from their ASIC predecessors. We make the case for regarding Platform FPGAs as meta-platforms because of the extent to which they extend the original concept of platform-based design. Looking forward, we offer some conjectures as to the nature of future FPGA platforms and some of the challenges that researchers will face.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124220376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：