Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188704
M. Tahoori
This paper presents a new technique for detecting resistive open defects in FPGAs. This technique is based on the reconfigurability feature of FPGAs. Using this technique, the delay of a defective path is increased several times more than the delay of the fault-free path, resulting in a higher resolution in detectability of resistive open defects in FPGAs, even at lower tester speed. Various detailed SPICE simulations are performed to validate this method. Also, a test configuration generation scheme is presented for the entire FPGA.
{"title":"Testing for resistive open defects in FPGAs","authors":"M. Tahoori","doi":"10.1109/FPT.2002.1188704","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188704","url":null,"abstract":"This paper presents a new technique for detecting resistive open defects in FPGAs. This technique is based on the reconfigurability feature of FPGAs. Using this technique, the delay of a defective path is increased several times more than the delay of the fault-free path, resulting in a higher resolution in detectability of resistive open defects in FPGAs, even at lower tester speed. Various detailed SPICE simulations are performed to validate this method. Also, a test configuration generation scheme is presented for the entire FPGA.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133601501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188709
T. K. Lee, Sherif Yusuf, W. Luk, A. Sloman, Emil C. Lupu, Naranker Dulay
High-performance firewalls can benefit from the increasing size, speed and flexibility of advanced reconfigurable hardware. However direct translation of conventional firewall rules in a router-based rule set often leads to inefficient hardware implementation. Moreover, such lowlevel description of firewall rules tends to be difficult to manage and to extend. We describe a framework, based on the high-level policy specification language Ponder for capturing firewall rules as authorization policies with user-definable constraints. Our framework supports optimisations to achieve efficient utilisation of hardware resources. A pipelined firewall implementation developed using this approach running at 10 MHz is capable of processing 2.5 million packets per second, which provides similar performance to a version without optimisation and is about 50 times faster than a software implementation running on a 700 MHz PIII processor.
{"title":"Development framework for firewall processors","authors":"T. K. Lee, Sherif Yusuf, W. Luk, A. Sloman, Emil C. Lupu, Naranker Dulay","doi":"10.1109/FPT.2002.1188709","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188709","url":null,"abstract":"High-performance firewalls can benefit from the increasing size, speed and flexibility of advanced reconfigurable hardware. However direct translation of conventional firewall rules in a router-based rule set often leads to inefficient hardware implementation. Moreover, such lowlevel description of firewall rules tends to be difficult to manage and to extend. We describe a framework, based on the high-level policy specification language Ponder for capturing firewall rules as authorization policies with user-definable constraints. Our framework supports optimisations to achieve efficient utilisation of hardware resources. A pipelined firewall implementation developed using this approach running at 10 MHz is capable of processing 2.5 million packets per second, which provides similar performance to a version without optimisation and is about 50 times faster than a software implementation running on a 700 MHz PIII processor.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133428001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188721
A. Stoica, Xin Guo, R. Zebulum, M. I. Ferguson, D. Keymeulen
The paper presents some experiments in automatic reconfiguration of field programmable devices using evolutionary algorithms. The experiments use a Field Programmable Transistor Array (FPTA), reconfigurable at transistor level. While parasitic effects of imperfect switches interconnecting transistors deteriorate performance of conventional designs when mapped to the FPTA, evolutionary algorithms are able to find a working design solution. The experiments are performed with a stand-alone board-level evolvable system (SABLES) in which the evolutionary algorithm is implemented with a DSP. SABLES can automatically configure the FPTA in tens to hundreds of seconds, time in which evaluates /spl sim/100,000 circuit candidate solutions. The paper overviews some examples of evolutionary synthesis of analog circuits on the FPTA.
{"title":"Evolution-based automated reconfiguration of field programmable analog devices","authors":"A. Stoica, Xin Guo, R. Zebulum, M. I. Ferguson, D. Keymeulen","doi":"10.1109/FPT.2002.1188721","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188721","url":null,"abstract":"The paper presents some experiments in automatic reconfiguration of field programmable devices using evolutionary algorithms. The experiments use a Field Programmable Transistor Array (FPTA), reconfigurable at transistor level. While parasitic effects of imperfect switches interconnecting transistors deteriorate performance of conventional designs when mapped to the FPTA, evolutionary algorithms are able to find a working design solution. The experiments are performed with a stand-alone board-level evolvable system (SABLES) in which the evolutionary algorithm is implemented with a DSP. SABLES can automatically configure the FPTA in tens to hundreds of seconds, time in which evaluates /spl sim/100,000 circuit candidate solutions. The paper overviews some examples of evolutionary synthesis of analog circuits on the FPTA.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"69 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113938329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188687
M. Kubo, M. Fujita
Field programmable gate arrays (FPGAs) have been widely used to realize rapid prototyping for not only control units but also arithmetic circuits. As VLSI design becomes larger and takes up much longer time, verification and debugging of logic design become the dominating part of total design period. FPGA is relatively useful in such case due to its rapid implementation. However, circuit performances are very sensitive to layout designs. Therefore minimal change of circuit structures is important. In this paper, we give a debug methodology targeting arithmetic circuits which modifies circuits locally and speeds up the total time for redesign as a result. To complete debugging, we analyze circuits, extract the erroneous parts, and replace by correct circuits.
{"title":"Debug methodology for arithmetic circuits on FPGAs","authors":"M. Kubo, M. Fujita","doi":"10.1109/FPT.2002.1188687","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188687","url":null,"abstract":"Field programmable gate arrays (FPGAs) have been widely used to realize rapid prototyping for not only control units but also arithmetic circuits. As VLSI design becomes larger and takes up much longer time, verification and debugging of logic design become the dominating part of total design period. FPGA is relatively useful in such case due to its rapid implementation. However, circuit performances are very sensitive to layout designs. Therefore minimal change of circuit structures is important. In this paper, we give a debug methodology targeting arithmetic circuits which modifies circuits locally and speeds up the total time for redesign as a result. To complete debugging, we analyze circuits, extract the erroneous parts, and replace by correct circuits.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116619733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188692
D. Sancho-Pradel, Simon R. Jones, R. Goodall
This paper presents the architecture of a System on Programmable Chip (SOPC) solution for embedded real-time control applications. It integrates a general-purpose processor, an application specific processor (CSP II), an AMBA compliant bus and a standard communication interface (Ethernet) on a single FPGA. The design supports high-speed, adaptive real-time control and integrates in a single device all the digital electronics, reducing the required external logic. The programming of the system is supported by software libraries that automatically transform the control law's equations into the processor's native Instruction Set.
{"title":"System on programmable chip for real-time control implementations","authors":"D. Sancho-Pradel, Simon R. Jones, R. Goodall","doi":"10.1109/FPT.2002.1188692","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188692","url":null,"abstract":"This paper presents the architecture of a System on Programmable Chip (SOPC) solution for embedded real-time control applications. It integrates a general-purpose processor, an application specific processor (CSP II), an AMBA compliant bus and a standard communication interface (Ethernet) on a single FPGA. The design supports high-speed, adaptive real-time control and integrates in a single device all the digital electronics, reducing the required external logic. The programming of the system is supported by software libraries that automatically transform the control law's equations into the processor's native Instruction Set.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116311725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188699
Máire O’Neill, J. McCanny
The rapid developments in the communications industry over the last decade have led to an escalation in the amount of sensitive data being transmitted over the Internet. This has resulted in an increased awareness of the need to provide security measures. Authentication is one such security measure. A novel highly efficient single-chip hardware design of the SHA-384 and SHA-512 authentication algorithms is described in this paper. The compact implementation achieves a throughput of 479 Mbits/sec utilising a shift register design approach and look-up tables (LUTs). This is believed to be the first SHA-384/SHA-512 hardware implementation to be reported in the literature.
{"title":"Efficient single-chip implementation of SHA-384 and SHA-512","authors":"Máire O’Neill, J. McCanny","doi":"10.1109/FPT.2002.1188699","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188699","url":null,"abstract":"The rapid developments in the communications industry over the last decade have led to an escalation in the amount of sensitive data being transmitted over the Internet. This has resulted in an increased awareness of the need to provide security measures. Authentication is one such security measure. A novel highly efficient single-chip hardware design of the SHA-384 and SHA-512 authentication algorithms is described in this paper. The compact implementation achieves a throughput of 479 Mbits/sec utilising a shift register design approach and look-up tables (LUTs). This is believed to be the first SHA-384/SHA-512 hardware implementation to be reported in the literature.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117042339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188659
M. Flynn
The task of computer architecture is to match a user application with a base technology. This match is realized by implementing an interpreter of some representation of the application with an efficient realization, measured in cost (area), time (performance) and power. As silicon technology becomes increasingly limited by interconnects, more efficient cellular computers are attractive. Indeed larger cells (compared to FPGAs) seem to offer an improved area /spl times/ time /spl times/ power measure. In order to effectively used them, the programmability obstacle must be overcome. The ALGE experiment showed how this might be done by creating a new class of user representation for scientific applications.
{"title":"Programmed solutions: the step beyond programmed logic [computer architecture]","authors":"M. Flynn","doi":"10.1109/FPT.2002.1188659","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188659","url":null,"abstract":"The task of computer architecture is to match a user application with a base technology. This match is realized by implementing an interpreter of some representation of the application with an efficient realization, measured in cost (area), time (performance) and power. As silicon technology becomes increasingly limited by interconnects, more efficient cellular computers are attractive. Indeed larger cells (compared to FPGAs) seem to offer an improved area /spl times/ time /spl times/ power measure. In order to effectively used them, the programmability obstacle must be overcome. The ALGE experiment showed how this might be done by creating a new class of user representation for scientific applications.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126894727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188733
Stephan Wong, Bastiaan Stougie, S. Cotofana
In multimedia processing, it is well-known that the sum-of-absolute-differences (SAD) operation is the most time-consuming operation when implemented in software running on programmable processor cores. This is mainly due to the sequential characteristic of such an implementation. In this paper, we investigate several hardware implementations of the SAD operation and map the most promising one in FPGA. Our investigation shows that an adder tree based approach yields the best results in terms of speed and area requirements and has been implemented as such by writing high-level VHDL code. The design was functionally verified by utilizing the MAX+plus II 10.1 Baseline software package from Altera Corp. and then synthesized by utilizing the LeonardoSpectrum software package from Exemplar Logic Inc. Preliminary results show that the design can be clocked at 380 MHz. This result translates into a faster than real-time full search in motion estimation for the main profile/main level of the MPEG-2 standard.
在多媒体处理中，绝对差和运算(sum-of-absolute-difference, SAD)是在可编程处理器内核上运行的软件中最耗时的运算。这主要是由于这种实现的顺序特性。在本文中，我们研究了SAD操作的几种硬件实现，并在FPGA中映射了最有前途的一种。我们的研究表明，基于加法器树的方法在速度和面积要求方面产生了最好的结果，并通过编写高级VHDL代码来实现。利用Altera公司的MAX+plus II 10.1 Baseline软件包对设计进行了功能验证，然后利用Exemplar Logic公司的LeonardoSpectrum软件包对设计进行了综合。初步结果表明，该设计可以在380mhz的频率下工作。这个结果转化为对MPEG-2标准的主要轮廓/主要级别的运动估计进行比实时更快的全搜索。
{"title":"Alternatives in FPGA-based SAD implementations","authors":"Stephan Wong, Bastiaan Stougie, S. Cotofana","doi":"10.1109/FPT.2002.1188733","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188733","url":null,"abstract":"In multimedia processing, it is well-known that the sum-of-absolute-differences (SAD) operation is the most time-consuming operation when implemented in software running on programmable processor cores. This is mainly due to the sequential characteristic of such an implementation. In this paper, we investigate several hardware implementations of the SAD operation and map the most promising one in FPGA. Our investigation shows that an adder tree based approach yields the best results in terms of speed and area requirements and has been implemented as such by writing high-level VHDL code. The design was functionally verified by utilizing the MAX+plus II 10.1 Baseline software package from Altera Corp. and then synthesized by utilizing the LeonardoSpectrum software package from Exemplar Logic Inc. Preliminary results show that the design can be clocked at 380 MHz. This result translates into a faster than real-time full search in motion estimation for the main profile/main level of the MPEG-2 standard.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129151112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188680
K. Zhou, Channakeshav, M. Chu, Jong-Ru Guo, S. Liu, R. Kraft, C. You, J. McDonald
The demand for high speed Field Programmable Gate Arrays (FPGAs) has been on a rise. These were never possible using CMOS as the basic device. People were able to achieve frequencies in the range of 70-250 MHz using CMOS. The availability of Silicon Germanium (SiGe) Heterojunction Bipolar Transistor (HBT) devices has opened the door for Gigahertz FPGAs. An FPGA with a speed of over 5 GHz was reported by B.S. Goda (2000) using SiGe 5HP technology. However in order to scale up FPGAs significantly, a serious power management scheme must be in place. Apart from this, architectural changes can be made to improve the speed and reduce the power. This paper elaborates on the architecture of the new SiGe FPGA and its advantages over the previous generation SiGe FPGAs. The entire Configuration Logic Block (CLB) has been implemented using seven Current Mode Logic (CML) trees. Apart from these, a novel power management scheme is implemented which allows the FPGA to operate at multiple modes: fast, non-critical, slow and off. The new FPGA can run in the fast mode when speed is critical or in the slow mode when power is the limiting issue. The CLB can run up to 5.96 GHz.
{"title":"Gigahertz SiGe BiCMOS FPGAs with new architectures and novel power management schemes","authors":"K. Zhou, Channakeshav, M. Chu, Jong-Ru Guo, S. Liu, R. Kraft, C. You, J. McDonald","doi":"10.1109/FPT.2002.1188680","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188680","url":null,"abstract":"The demand for high speed Field Programmable Gate Arrays (FPGAs) has been on a rise. These were never possible using CMOS as the basic device. People were able to achieve frequencies in the range of 70-250 MHz using CMOS. The availability of Silicon Germanium (SiGe) Heterojunction Bipolar Transistor (HBT) devices has opened the door for Gigahertz FPGAs. An FPGA with a speed of over 5 GHz was reported by B.S. Goda (2000) using SiGe 5HP technology. However in order to scale up FPGAs significantly, a serious power management scheme must be in place. Apart from this, architectural changes can be made to improve the speed and reduce the power. This paper elaborates on the architecture of the new SiGe FPGA and its advantages over the previous generation SiGe FPGAs. The entire Configuration Logic Block (CLB) has been implemented using seven Current Mode Logic (CML) trees. Apart from these, a novel power management scheme is implemented which allows the FPGA to operate at multiple modes: fast, non-critical, slow and off. The new FPGA can run in the fast mode when speed is critical or in the slow mode when power is the limiting issue. The CLB can run up to 5.96 GHz.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132598515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188706
J. Ko, K. Ng
Reconfigurable Computing (RC) is a technology that attempts to increase computational power by customizing the computational platform to the specific problem at hand. This approach is favorable for handling problems like radiosity distribution computation, which consist of a fine granularity of parallel floating point multiplications. We have performed a feasibility study on using reconfigurable hardware for interactive radiosity distribution computation. We have introduced and applied techniques to convert the conventional algorithms on Radiosity Redistribution into parallel execution structures, especially in reusing patches information. Parallel Progressive Radiosity Implementation (PPR), a new system architecture with swappable area is proposed to handle Form Factor Determination and Radiosity Redistribution dynamically in RC platforms, which reduces the unresolved conflicts between the resources starvation.
{"title":"Reconfigurable implementation of radiosity distribution computation","authors":"J. Ko, K. Ng","doi":"10.1109/FPT.2002.1188706","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188706","url":null,"abstract":"Reconfigurable Computing (RC) is a technology that attempts to increase computational power by customizing the computational platform to the specific problem at hand. This approach is favorable for handling problems like radiosity distribution computation, which consist of a fine granularity of parallel floating point multiplications. We have performed a feasibility study on using reconfigurable hardware for interactive radiosity distribution computation. We have introduced and applied techniques to convert the conventional algorithms on Radiosity Redistribution into parallel execution structures, especially in reusing patches information. Parallel Progressive Radiosity Implementation (PPR), a new system architecture with swappable area is proposed to handle Form Factor Determination and Radiosity Redistribution dynamically in RC platforms, which reduces the unresolved conflicts between the resources starvation.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126848595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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