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2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.最新文献

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FPGA implementation of MFNN for image registration MFNN图像配准的FPGA实现
D. Gharpure, M. Puranik
The multilayer feedforward neural network (MFNN) is modified to simplify hardware realization and at the same time retain the accuracy of detection. The results obtained have been found to be comparable to the software simulation algorithm which is used as a test base. The MFNN implementation involves low hardware complexity, good noise immunity and fast circuitry.
对多层前馈神经网络(MFNN)进行了改进,简化了硬件实现,同时保持了检测的准确性。所得结果与软件仿真算法相当,并作为测试基础。MFNN的实现具有硬件复杂度低、抗噪性好、电路速度快等特点。
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引用次数: 2
Pattern recognition in the HADES spectrometer: an application of FPGA technology in nuclear and particle physics HADES光谱仪中的模式识别:FPGA技术在核与粒子物理中的应用
I. Fröhlich, A. Gabriel, D. Kirschner, J. Lehnert, E. Lins, M. Petri, T. Perez, J. Ritman, D. Schäfer, A. Toia, M. Traxler, W. Kuehn
HADES is a second-generation dilepton spectrometer for hadron and heavy ion physics at the SIS Accelerator facility of GSI Darmstadt, Germany. The physics programme requires the detection of rare events in an environment of several GBytes/s of background data. This paper describes the dedicated trigger system which works together with a pipelined data acquisition system to suppress background events by 2 orders of magnitude. The trigger system is based on pattern recognition algorithms implemented in FPGAs and DSPs.
HADES是德国达姆施塔特GSI SIS加速器设施中用于强子和重离子物理的第二代双轻子光谱仪。物理程序要求在具有几gb /s背景数据的环境中检测罕见事件。本文介绍了一种专用触发系统,该系统与一个流水线数据采集系统一起工作,可将背景事件抑制2个数量级。触发系统基于在fpga和dsp上实现的模式识别算法。
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引用次数: 10
Implementing logic in FPGA memory arrays: heterogeneous memory architectures 在FPGA存储器阵列中实现逻辑:异构存储器架构
S. Wilton
It has become clear that large embedded configurable memory arrays will be essential in future FPGAs. Embedded arrays provide high-density high-speed implementations of the storage parts of circuits. Unfortunately, they require the FPGA vendor to partition the device into memory and logic resources at manufacture-time. This leads to a waste of chip area for customers that do not use all of the storage provided This chip area need not be wasted, and can in fact be used very efficiently, if the arrays are configured as large multi-output ROMs, and used to implement logic. In this paper we investigate how the architecture of the FPGA embedded arrays affects their ability to implement logic. Specifically, we focus on architectures which contain more than one size of memory array. We show that these heterogeneous architectures result in significantly denser implementations of logic than architectures with only one size of memory array. We also show that the best heterogeneous architecture contains both 2048 bit arrays and 128 bit arrays.
很明显,大型嵌入式可配置存储器阵列在未来的fpga中是必不可少的。嵌入式阵列提供了电路存储部分的高密度高速实现。不幸的是,它们要求FPGA供应商在制造时将器件划分为内存和逻辑资源。对于不使用所提供的所有存储的客户来说,这将导致芯片面积的浪费。如果将阵列配置为大型多输出rom,并用于实现逻辑,则无需浪费该芯片面积,实际上可以非常有效地使用该芯片面积。在本文中,我们研究了FPGA嵌入式阵列的架构如何影响其实现逻辑的能力。具体来说,我们关注的是包含不止一种大小的存储器阵列的体系结构。我们表明,这些异构架构导致逻辑的实现比只有一种大小的内存阵列的架构要密集得多。我们还证明了最好的异构架构包含2048位阵列和128位阵列。
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引用次数: 17
Evolutionary analog circuit design on a programmable analog multiplexer array 一种可编程模拟多路复用器阵列的进化模拟电路设计
C. C. Santini, Jose F. M. Amaral, M. Pacheco, M. Vellasco, M. H. Szwarcman
This work discusses an Evolvable Hardware (EHW) platform for the synthesis of analog electronic circuits. The EHW analog platform, named PAMA (Programmable Analog Multiplexer Array), is a reconfigurable platform that consists of integrated circuits whose internal connections can be programmed by Evolutionary Computation techniques, such as Genetic Algorithms, to synthesize circuits. The PAMA is classified as Field Programmable Analog Array (FPAA). FPAAs have just recently appeared, and most projects are being carried out in universities and research centers. They constitute the state of the art in the technology of reconfigurable platforms. These devices will become the building blocks of a forthcoming class of hardware, with the important features of self-adaptation and self-repairing, through automatic reconfiguration. The PAMA platform architectural details, concepts and characteristics are discussed. Three case studies, with promising results, are described: an operational amplifier, a logarithmic amplifier and a membership function circuit of a fuzzy logic controller.
本文讨论了一种用于模拟电路合成的可进化硬件(EHW)平台。EHW模拟平台名为PAMA(可编程模拟多路复用阵列),是一个可重构平台,由集成电路组成,其内部连接可以通过进化计算技术(如遗传算法)编程来合成电路。PAMA被归类为现场可编程模拟阵列(FPAA)。FPAAs是最近才出现的,大多数项目都是在大学和研究中心进行的。它们构成了可重构平台技术的最新状态。这些设备将成为即将到来的硬件的基石,通过自动重新配置,具有自适应和自我修复的重要特征。讨论了PAMA平台的体系结构细节、概念和特点。本文介绍了运算放大器、对数放大器和模糊逻辑控制器的隶属函数电路三个实例,并取得了良好的结果。
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引用次数: 8
PD-XML: extensible markup language for processor description PD-XML:用于处理器描述的可扩展标记语言
S. P. Seng, K. Palem, R. Rabbah, W. Wong, W. Luk, P. Cheung
This paper introduces PD-XML, a meta-language for describing instruction processors in general and with an emphasis on embedded processors, with the specific aim of enabling their rapid prototyping, evaluation and eventual design and implementation. PD-XML is not specific to any one architecture, compiler or simulation environment and hence provides greater flexibility than related machine description methodologies. We demonstrate how PD-XML can be interfaced to existing description methodologies and tool-flows. In particular we show how PD-XML specifications can be translated into appropriate machine descriptions for the parametric HPL-PD VLIW processor, and for the Flexible Instruction Processor (FIP) approach targeting reconfigurable implementations.
本文介绍了PD-XML,这是一种用于描述指令处理器的元语言,重点是嵌入式处理器,其具体目的是使它们能够快速原型、评估和最终设计和实现。PD-XML不特定于任何一种体系结构、编译器或模拟环境,因此比相关的机器描述方法提供了更大的灵活性。我们演示了如何将PD-XML与现有的描述方法和工具流连接起来。我们特别展示了如何将PD-XML规范转换为参数化HPL-PD VLIW处理器和针对可重构实现的灵活指令处理器(FIP)方法的适当机器描述。
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引用次数: 12
Design and implementation of a novel architecture for symmetric FIR filters with boundary handling on Xilinx Virtex FPGAs 基于Xilinx Virtex fpga的具有边界处理的对称FIR滤波器新架构的设计与实现
A. Benkrid, K. Benkrid, D. Crookes
Symmetric FIR filters, which provide linear phases, are frequently used in digital signal processing. This paper presents the design and implementation of a novel architecture for symmetric FIR filters on Xilinx Virtex FPGAs. The architecture is particularly useful for handling the problem of processing signal boundaries, which occurs in finite length signal processing (e.g. image processing). Based on bit parallel arithmetic, our architecture is fully scalable and parameterised. It takes into account the details of the symmetry and exploits the features of Xilinx Virtex FPGAs. The implementation leads to considerable area savings compared to conventional implementations (based on a hard router), at the expense of using a clock doubler, which reduces the overall processing speed. The latter is however still high enough to achieve real time performance. Moreover, our architecture can match the speed of a conventional implementation if the filter output is going to be decimated, as it is the case in multirate applications (e.g. wavelets).
对称FIR滤波器是数字信号处理中常用的一种提供线性相位的滤波器。本文介绍了一种基于Xilinx Virtex fpga的对称FIR滤波器的新架构的设计和实现。该架构对于处理信号边界的问题特别有用,这种问题发生在有限长度的信号处理中(例如图像处理)。基于位并行算法,我们的架构是完全可扩展和参数化的。它考虑了对称的细节,并利用了Xilinx Virtex fpga的特点。与传统实现(基于硬路由器)相比,该实现节省了相当大的面积,但代价是使用时钟加倍器,从而降低了整体处理速度。然而,后者仍然足够高,可以实现实时性能。此外,如果滤波器输出将被抽取,我们的架构可以匹配传统实现的速度,就像在多速率应用(例如小波)中的情况一样。
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引用次数: 8
Logic synthesis of multi-output functions for PAL-based CPLDs 基于pal的cpld多输出功能的逻辑综合
D. Kania
In this paper multi-level synthesis for PAL-based CPLDs is presented. The essence of the method is to search for multi-output implicants that can be shared by several functions. This approach presents a unique form for illustrating a minimized form of a multi-output Boolean function. The presented method, implemented within the PALDec system, is based on the analysis of graph nodes that represent states of a digital circuit outputs. The results of synthesis for benchmarks are compared to the classical technology mapping method.
本文介绍了基于pal的cpld的多级合成。该方法的实质是寻找可由多个函数共享的多输出隐含。这种方法为说明多输出布尔函数的最小化形式提供了一种独特的形式。所提出的方法在PALDec系统中实现,是基于对表示数字电路输出状态的图节点的分析。将基准综合的结果与经典的技术映射方法进行了比较。
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引用次数: 15
An optimal PCM codec soft IP generator and its application 一种最优PCM编解码软IP发生器及其应用
Gwo-Yang Wu, Liang-Bi Chen, Y. Jeang, G. Jong
In this paper, we propose a soft IP generator which can add or remove PCM codec modules arbitrarily. It can be applied to PCM codec IP designs that need to change their related modules, corresponding to different working environments. It also can help us to easily manage our soft IP modules, produce optimized modules, and remove unnecessary modules, in order to reduce the implementation cost. In addition, users can implement their own Verilog HDL code of PCM codec by following our predefined interface specification, and integrate it with our optimal PCM codec module to produce the users' own optimized system.
本文提出了一种可以任意增加或删除PCM编解码器模块的软IP发生器。适用于需要改变相关模块的PCM编解码器IP设计,以适应不同的工作环境。它还可以帮助我们轻松地管理我们的软IP模块,生成优化的模块,并删除不必要的模块,以降低实施成本。此外,用户可以按照我们预定义的接口规范实现自己的PCM编解码器的Verilog HDL代码,并将其与我们的最佳PCM编解码器模块集成,从而生成用户自己的优化系统。
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引用次数: 3
A methodology for design of run-time reconfigurable systems 运行时可重构系统的设计方法
Gareth Lee, G. Milne
Field-programmable logic (FPL) is rapidly becoming established in markets requiring high-performance, low lead time and the ability to perform soft-upgrades on site. However few current FPL systems utilise run-time reconfiguration (RTR) and those that do rely on infrequent and coarse-grained reconfiguration. This is partly due to poor support from current FPGAs; few devices allow random access to individual configurable logic blocks. But we believe it also partly reflects the fact that designers of reconfigurable computing systems lack methodologies and tools to guide the design process. In software engineering there are well established paradigms for the design of reconfigurable systems, such as object orientation (OO) and for the modelling and description of systems, such as UML. This paper describes our progress towards a component-based methodology for application to RTR. We have preserved useful OO properties which support a rigorous, modular design style.
现场可编程逻辑(FPL)在需要高性能、低交货周期和现场软升级能力的市场中迅速建立起来。然而,目前很少有FPL系统利用运行时重新配置(RTR),而那些依赖于不频繁和粗粒度的重新配置。这部分是由于当前fpga的支持不足;很少有设备允许随机访问单个可配置逻辑块。但我们认为,这也在一定程度上反映了一个事实,即可重构计算系统的设计者缺乏指导设计过程的方法和工具。在软件工程中,对于可重构系统的设计,例如面向对象(OO),以及对于系统的建模和描述,例如UML,都有很好的建立范例。本文描述了我们在基于组件的RTR应用方法方面的进展。我们保留了有用的OO属性,这些属性支持严格的模块化设计风格。
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引用次数: 5
Image fusion for uninhabited airborne vehicles 无人飞行器图像融合
M. Jasiunas, D. Kearney, John Hopf, G. Wigley
In image fusion, information from a set of images is extracted and then combined intelligently to form a new composite image with extended information content. The original data may come from different viewing conditions (bracketed focus or exposure) or various sensors (visible and infrared or a cat scan and magnetic resonance imagery). Uninhabited Airborne Vehicles (UAVs) often have visible, infrared and synthetic aperture radar imaging sensors, so image fusion is an appropriate onboard processing task for UAVs. Some forms of image fusion are computationally intensive tasks, but like many other image processing applications are naturally suited to acceleration in hardware. This potential for hardware acceleration, and the ability to reconfigure the UAV to implement new algorithms as it moves towards objects of interest make reconfigurable computing a natural route for a hardware implementation. In this paper we present what we believe is the first implementation of image fusion on a reconfigurable platform alone, and the first investigation of adaptive image fusion which makes use of dynamic reconfiguration to change the fusion algorithm as the UAV approaches an object of interest.
在图像融合中,从一组图像中提取信息,然后进行智能组合,形成新的具有扩展信息内容的复合图像。原始数据可能来自不同的观看条件(括号聚焦或曝光)或不同的传感器(可见光和红外或cat扫描和磁共振成像)。无人飞行器通常具有可见光、红外和合成孔径雷达成像传感器,因此图像融合是一项适合无人机的机载处理任务。某些形式的图像融合是计算密集型任务,但像许多其他图像处理应用程序一样,自然适合硬件加速。这种硬件加速的潜力,以及在无人机向感兴趣的目标移动时重新配置无人机以实现新算法的能力,使可重构计算成为硬件实现的自然途径。在本文中,我们提出了我们认为是第一次在可重构平台上实现图像融合,并且首次研究了自适应图像融合,该融合利用动态重构来改变融合算法,当无人机接近感兴趣的目标时。
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引用次数: 18
期刊
2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.
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