Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188712
D. Gharpure, M. Puranik
The multilayer feedforward neural network (MFNN) is modified to simplify hardware realization and at the same time retain the accuracy of detection. The results obtained have been found to be comparable to the software simulation algorithm which is used as a test base. The MFNN implementation involves low hardware complexity, good noise immunity and fast circuitry.
{"title":"FPGA implementation of MFNN for image registration","authors":"D. Gharpure, M. Puranik","doi":"10.1109/FPT.2002.1188712","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188712","url":null,"abstract":"The multilayer feedforward neural network (MFNN) is modified to simplify hardware realization and at the same time retain the accuracy of detection. The results obtained have been found to be comparable to the software simulation algorithm which is used as a test base. The MFNN implementation involves low hardware complexity, good noise immunity and fast circuitry.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128178629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188731
I. Fröhlich, A. Gabriel, D. Kirschner, J. Lehnert, E. Lins, M. Petri, T. Perez, J. Ritman, D. Schäfer, A. Toia, M. Traxler, W. Kuehn
HADES is a second-generation dilepton spectrometer for hadron and heavy ion physics at the SIS Accelerator facility of GSI Darmstadt, Germany. The physics programme requires the detection of rare events in an environment of several GBytes/s of background data. This paper describes the dedicated trigger system which works together with a pipelined data acquisition system to suppress background events by 2 orders of magnitude. The trigger system is based on pattern recognition algorithms implemented in FPGAs and DSPs.
{"title":"Pattern recognition in the HADES spectrometer: an application of FPGA technology in nuclear and particle physics","authors":"I. Fröhlich, A. Gabriel, D. Kirschner, J. Lehnert, E. Lins, M. Petri, T. Perez, J. Ritman, D. Schäfer, A. Toia, M. Traxler, W. Kuehn","doi":"10.1109/FPT.2002.1188731","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188731","url":null,"abstract":"HADES is a second-generation dilepton spectrometer for hadron and heavy ion physics at the SIS Accelerator facility of GSI Darmstadt, Germany. The physics programme requires the detection of rare events in an environment of several GBytes/s of background data. This paper describes the dedicated trigger system which works together with a pipelined data acquisition system to suppress background events by 2 orders of magnitude. The trigger system is based on pattern recognition algorithms implemented in FPGAs and DSPs.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130116702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188675
S. Wilton
It has become clear that large embedded configurable memory arrays will be essential in future FPGAs. Embedded arrays provide high-density high-speed implementations of the storage parts of circuits. Unfortunately, they require the FPGA vendor to partition the device into memory and logic resources at manufacture-time. This leads to a waste of chip area for customers that do not use all of the storage provided This chip area need not be wasted, and can in fact be used very efficiently, if the arrays are configured as large multi-output ROMs, and used to implement logic. In this paper we investigate how the architecture of the FPGA embedded arrays affects their ability to implement logic. Specifically, we focus on architectures which contain more than one size of memory array. We show that these heterogeneous architectures result in significantly denser implementations of logic than architectures with only one size of memory array. We also show that the best heterogeneous architecture contains both 2048 bit arrays and 128 bit arrays.
{"title":"Implementing logic in FPGA memory arrays: heterogeneous memory architectures","authors":"S. Wilton","doi":"10.1109/FPT.2002.1188675","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188675","url":null,"abstract":"It has become clear that large embedded configurable memory arrays will be essential in future FPGAs. Embedded arrays provide high-density high-speed implementations of the storage parts of circuits. Unfortunately, they require the FPGA vendor to partition the device into memory and logic resources at manufacture-time. This leads to a waste of chip area for customers that do not use all of the storage provided This chip area need not be wasted, and can in fact be used very efficiently, if the arrays are configured as large multi-output ROMs, and used to implement logic. In this paper we investigate how the architecture of the FPGA embedded arrays affects their ability to implement logic. Specifically, we focus on architectures which contain more than one size of memory array. We show that these heterogeneous architectures result in significantly denser implementations of logic than architectures with only one size of memory array. We also show that the best heterogeneous architecture contains both 2048 bit arrays and 128 bit arrays.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133430196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188681
C. C. Santini, Jose F. M. Amaral, M. Pacheco, M. Vellasco, M. H. Szwarcman
This work discusses an Evolvable Hardware (EHW) platform for the synthesis of analog electronic circuits. The EHW analog platform, named PAMA (Programmable Analog Multiplexer Array), is a reconfigurable platform that consists of integrated circuits whose internal connections can be programmed by Evolutionary Computation techniques, such as Genetic Algorithms, to synthesize circuits. The PAMA is classified as Field Programmable Analog Array (FPAA). FPAAs have just recently appeared, and most projects are being carried out in universities and research centers. They constitute the state of the art in the technology of reconfigurable platforms. These devices will become the building blocks of a forthcoming class of hardware, with the important features of self-adaptation and self-repairing, through automatic reconfiguration. The PAMA platform architectural details, concepts and characteristics are discussed. Three case studies, with promising results, are described: an operational amplifier, a logarithmic amplifier and a membership function circuit of a fuzzy logic controller.
{"title":"Evolutionary analog circuit design on a programmable analog multiplexer array","authors":"C. C. Santini, Jose F. M. Amaral, M. Pacheco, M. Vellasco, M. H. Szwarcman","doi":"10.1109/FPT.2002.1188681","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188681","url":null,"abstract":"This work discusses an Evolvable Hardware (EHW) platform for the synthesis of analog electronic circuits. The EHW analog platform, named PAMA (Programmable Analog Multiplexer Array), is a reconfigurable platform that consists of integrated circuits whose internal connections can be programmed by Evolutionary Computation techniques, such as Genetic Algorithms, to synthesize circuits. The PAMA is classified as Field Programmable Analog Array (FPAA). FPAAs have just recently appeared, and most projects are being carried out in universities and research centers. They constitute the state of the art in the technology of reconfigurable platforms. These devices will become the building blocks of a forthcoming class of hardware, with the important features of self-adaptation and self-repairing, through automatic reconfiguration. The PAMA platform architectural details, concepts and characteristics are discussed. Three case studies, with promising results, are described: an operational amplifier, a logarithmic amplifier and a membership function circuit of a fuzzy logic controller.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133745555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188729
S. P. Seng, K. Palem, R. Rabbah, W. Wong, W. Luk, P. Cheung
This paper introduces PD-XML, a meta-language for describing instruction processors in general and with an emphasis on embedded processors, with the specific aim of enabling their rapid prototyping, evaluation and eventual design and implementation. PD-XML is not specific to any one architecture, compiler or simulation environment and hence provides greater flexibility than related machine description methodologies. We demonstrate how PD-XML can be interfaced to existing description methodologies and tool-flows. In particular we show how PD-XML specifications can be translated into appropriate machine descriptions for the parametric HPL-PD VLIW processor, and for the Flexible Instruction Processor (FIP) approach targeting reconfigurable implementations.
{"title":"PD-XML: extensible markup language for processor description","authors":"S. P. Seng, K. Palem, R. Rabbah, W. Wong, W. Luk, P. Cheung","doi":"10.1109/FPT.2002.1188729","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188729","url":null,"abstract":"This paper introduces PD-XML, a meta-language for describing instruction processors in general and with an emphasis on embedded processors, with the specific aim of enabling their rapid prototyping, evaluation and eventual design and implementation. PD-XML is not specific to any one architecture, compiler or simulation environment and hence provides greater flexibility than related machine description methodologies. We demonstrate how PD-XML can be interfaced to existing description methodologies and tool-flows. In particular we show how PD-XML specifications can be translated into appropriate machine descriptions for the parametric HPL-PD VLIW processor, and for the Flexible Instruction Processor (FIP) approach targeting reconfigurable implementations.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117300971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188710
A. Benkrid, K. Benkrid, D. Crookes
Symmetric FIR filters, which provide linear phases, are frequently used in digital signal processing. This paper presents the design and implementation of a novel architecture for symmetric FIR filters on Xilinx Virtex FPGAs. The architecture is particularly useful for handling the problem of processing signal boundaries, which occurs in finite length signal processing (e.g. image processing). Based on bit parallel arithmetic, our architecture is fully scalable and parameterised. It takes into account the details of the symmetry and exploits the features of Xilinx Virtex FPGAs. The implementation leads to considerable area savings compared to conventional implementations (based on a hard router), at the expense of using a clock doubler, which reduces the overall processing speed. The latter is however still high enough to achieve real time performance. Moreover, our architecture can match the speed of a conventional implementation if the filter output is going to be decimated, as it is the case in multirate applications (e.g. wavelets).
{"title":"Design and implementation of a novel architecture for symmetric FIR filters with boundary handling on Xilinx Virtex FPGAs","authors":"A. Benkrid, K. Benkrid, D. Crookes","doi":"10.1109/FPT.2002.1188710","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188710","url":null,"abstract":"Symmetric FIR filters, which provide linear phases, are frequently used in digital signal processing. This paper presents the design and implementation of a novel architecture for symmetric FIR filters on Xilinx Virtex FPGAs. The architecture is particularly useful for handling the problem of processing signal boundaries, which occurs in finite length signal processing (e.g. image processing). Based on bit parallel arithmetic, our architecture is fully scalable and parameterised. It takes into account the details of the symmetry and exploits the features of Xilinx Virtex FPGAs. The implementation leads to considerable area savings compared to conventional implementations (based on a hard router), at the expense of using a clock doubler, which reduces the overall processing speed. The latter is however still high enough to achieve real time performance. Moreover, our architecture can match the speed of a conventional implementation if the filter output is going to be decimated, as it is the case in multirate applications (e.g. wavelets).","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114218636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188727
D. Kania
In this paper multi-level synthesis for PAL-based CPLDs is presented. The essence of the method is to search for multi-output implicants that can be shared by several functions. This approach presents a unique form for illustrating a minimized form of a multi-output Boolean function. The presented method, implemented within the PALDec system, is based on the analysis of graph nodes that represent states of a digital circuit outputs. The results of synthesis for benchmarks are compared to the classical technology mapping method.
{"title":"Logic synthesis of multi-output functions for PAL-based CPLDs","authors":"D. Kania","doi":"10.1109/FPT.2002.1188727","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188727","url":null,"abstract":"In this paper multi-level synthesis for PAL-based CPLDs is presented. The essence of the method is to search for multi-output implicants that can be shared by several functions. This approach presents a unique form for illustrating a minimized form of a multi-output Boolean function. The presented method, implemented within the PALDec system, is based on the analysis of graph nodes that represent states of a digital circuit outputs. The results of synthesis for benchmarks are compared to the classical technology mapping method.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"28 12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124100181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188700
Gwo-Yang Wu, Liang-Bi Chen, Y. Jeang, G. Jong
In this paper, we propose a soft IP generator which can add or remove PCM codec modules arbitrarily. It can be applied to PCM codec IP designs that need to change their related modules, corresponding to different working environments. It also can help us to easily manage our soft IP modules, produce optimized modules, and remove unnecessary modules, in order to reduce the implementation cost. In addition, users can implement their own Verilog HDL code of PCM codec by following our predefined interface specification, and integrate it with our optimal PCM codec module to produce the users' own optimized system.
{"title":"An optimal PCM codec soft IP generator and its application","authors":"Gwo-Yang Wu, Liang-Bi Chen, Y. Jeang, G. Jong","doi":"10.1109/FPT.2002.1188700","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188700","url":null,"abstract":"In this paper, we propose a soft IP generator which can add or remove PCM codec modules arbitrarily. It can be applied to PCM codec IP designs that need to change their related modules, corresponding to different working environments. It also can help us to easily manage our soft IP modules, produce optimized modules, and remove unnecessary modules, in order to reduce the implementation cost. In addition, users can implement their own Verilog HDL code of PCM codec by following our predefined interface specification, and integrate it with our optimal PCM codec module to produce the users' own optimized system.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124370803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188665
Gareth Lee, G. Milne
Field-programmable logic (FPL) is rapidly becoming established in markets requiring high-performance, low lead time and the ability to perform soft-upgrades on site. However few current FPL systems utilise run-time reconfiguration (RTR) and those that do rely on infrequent and coarse-grained reconfiguration. This is partly due to poor support from current FPGAs; few devices allow random access to individual configurable logic blocks. But we believe it also partly reflects the fact that designers of reconfigurable computing systems lack methodologies and tools to guide the design process. In software engineering there are well established paradigms for the design of reconfigurable systems, such as object orientation (OO) and for the modelling and description of systems, such as UML. This paper describes our progress towards a component-based methodology for application to RTR. We have preserved useful OO properties which support a rigorous, modular design style.
{"title":"A methodology for design of run-time reconfigurable systems","authors":"Gareth Lee, G. Milne","doi":"10.1109/FPT.2002.1188665","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188665","url":null,"abstract":"Field-programmable logic (FPL) is rapidly becoming established in markets requiring high-performance, low lead time and the ability to perform soft-upgrades on site. However few current FPL systems utilise run-time reconfiguration (RTR) and those that do rely on infrequent and coarse-grained reconfiguration. This is partly due to poor support from current FPGAs; few devices allow random access to individual configurable logic blocks. But we believe it also partly reflects the fact that designers of reconfigurable computing systems lack methodologies and tools to guide the design process. In software engineering there are well established paradigms for the design of reconfigurable systems, such as object orientation (OO) and for the modelling and description of systems, such as UML. This paper describes our progress towards a component-based methodology for application to RTR. We have preserved useful OO properties which support a rigorous, modular design style.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126396711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188708
M. Jasiunas, D. Kearney, John Hopf, G. Wigley
In image fusion, information from a set of images is extracted and then combined intelligently to form a new composite image with extended information content. The original data may come from different viewing conditions (bracketed focus or exposure) or various sensors (visible and infrared or a cat scan and magnetic resonance imagery). Uninhabited Airborne Vehicles (UAVs) often have visible, infrared and synthetic aperture radar imaging sensors, so image fusion is an appropriate onboard processing task for UAVs. Some forms of image fusion are computationally intensive tasks, but like many other image processing applications are naturally suited to acceleration in hardware. This potential for hardware acceleration, and the ability to reconfigure the UAV to implement new algorithms as it moves towards objects of interest make reconfigurable computing a natural route for a hardware implementation. In this paper we present what we believe is the first implementation of image fusion on a reconfigurable platform alone, and the first investigation of adaptive image fusion which makes use of dynamic reconfiguration to change the fusion algorithm as the UAV approaches an object of interest.
{"title":"Image fusion for uninhabited airborne vehicles","authors":"M. Jasiunas, D. Kearney, John Hopf, G. Wigley","doi":"10.1109/FPT.2002.1188708","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188708","url":null,"abstract":"In image fusion, information from a set of images is extracted and then combined intelligently to form a new composite image with extended information content. The original data may come from different viewing conditions (bracketed focus or exposure) or various sensors (visible and infrared or a cat scan and magnetic resonance imagery). Uninhabited Airborne Vehicles (UAVs) often have visible, infrared and synthetic aperture radar imaging sensors, so image fusion is an appropriate onboard processing task for UAVs. Some forms of image fusion are computationally intensive tasks, but like many other image processing applications are naturally suited to acceleration in hardware. This potential for hardware acceleration, and the ability to reconfigure the UAV to implement new algorithms as it moves towards objects of interest make reconfigurable computing a natural route for a hardware implementation. In this paper we present what we believe is the first implementation of image fusion on a reconfigurable platform alone, and the first investigation of adaptive image fusion which makes use of dynamic reconfiguration to change the fusion algorithm as the UAV approaches an object of interest.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124650270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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