Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188686
M. E. Dehkordi, S. Brown
Although delay driven clustering algorithms can optimize circuit delay, they usually result in huge area increase. We present a node duplication control strategy along with a simple packing algorithm that greatly reduce the area penalty with a very small degradation in performance. We use the Quartus Design System from Altera to test our algorithm for a set of MCNC benchmark circuits. The results show that while a 14.5% average delay decrease can be achieved with an average area increase of 240.8%, the algorithm reduces the average area penalty to 27.4% with an average delay decrease of 13.8%. Also the number of clusters and the fitting time reported by Quartus are reduced by more than 91% and 60%, respectively.
{"title":"The effect of cluster packing and node duplication control in delay driven clustering","authors":"M. E. Dehkordi, S. Brown","doi":"10.1109/FPT.2002.1188686","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188686","url":null,"abstract":"Although delay driven clustering algorithms can optimize circuit delay, they usually result in huge area increase. We present a node duplication control strategy along with a simple packing algorithm that greatly reduce the area penalty with a very small degradation in performance. We use the Quartus Design System from Altera to test our algorithm for a set of MCNC benchmark circuits. The results show that while a 14.5% average delay decrease can be achieved with an average area increase of 240.8%, the algorithm reduces the average area penalty to 27.4% with an average delay decrease of 13.8%. Also the number of clusters and the fitting time reported by Quartus are reduced by more than 91% and 60%, respectively.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128725887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188668
Y. Yi, Roger Francis Woods
A system level design framework for FPGA-based DSP design is presented. The design flow utilizes System Generator, a system level tool developed by Xilinx, and links it to an "in-house" architectural synthesis tool, IRIS. Whilst System Generator allows FPGA-based Intellectual Property (IP) cores to be incorporated into the design flow, it does not address the timing and latency problems introduced by the cores which can be considerable, particularly when the cores are pipelined. These problems are addressed by the IRIS synthesis tool. The paper describes the tools, their interaction and illustrates the flow using an 8-tap Transpose-Form Retimed Delayed LMS (TF-RDLMS) adaptive filter.
{"title":"FPGA-based system-level design framework based on the IRIS synthesis tool and System Generator","authors":"Y. Yi, Roger Francis Woods","doi":"10.1109/FPT.2002.1188668","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188668","url":null,"abstract":"A system level design framework for FPGA-based DSP design is presented. The design flow utilizes System Generator, a system level tool developed by Xilinx, and links it to an \"in-house\" architectural synthesis tool, IRIS. Whilst System Generator allows FPGA-based Intellectual Property (IP) cores to be incorporated into the design flow, it does not address the timing and latency problems introduced by the cores which can be considerable, particularly when the cores are pipelined. These problems are addressed by the IRIS synthesis tool. The paper describes the tools, their interaction and illustrates the flow using an 8-tap Transpose-Form Retimed Delayed LMS (TF-RDLMS) adaptive filter.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125915452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188672
Y. Hori, M. Sonoyama, T. Maruyama
After the success of DEEP BLUE in computer chess, shogi, or Japanese chess is a next challenging target in artificial intelligence for game playing. The complexity and huge search space of shogi have been motivating researchers to make shogi programs, but none of them is competent enough to play against human experts. To improve the competence of shogi programs, it is a promising approach to develop dedicated hardware systems. However inflexible architecture and lack of hardware resource have been the significant problems in hardware development. The flexibility and recent progress in the gate size of FPGAs are expected to give solutions to the problems. As a first step to shogi hardware, we implemented modules to generate check and defense moves in tsume-shogi, or mating problems in shogi. With the latest FPGA, we successfully implemented all modules on a single chip and eliminated the bottleneck of memory bandwidth. In this paper we describe a procedure for parallel move generation in tsume-shogi hardware and architecture of the modules implemented on an FPGA. A discussion about the performance of the hardware is also included in the paper. The hardware is roughly estimated to work 10-50 times faster than software.
{"title":"An FPGA-based processor for shogi mating problems","authors":"Y. Hori, M. Sonoyama, T. Maruyama","doi":"10.1109/FPT.2002.1188672","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188672","url":null,"abstract":"After the success of DEEP BLUE in computer chess, shogi, or Japanese chess is a next challenging target in artificial intelligence for game playing. The complexity and huge search space of shogi have been motivating researchers to make shogi programs, but none of them is competent enough to play against human experts. To improve the competence of shogi programs, it is a promising approach to develop dedicated hardware systems. However inflexible architecture and lack of hardware resource have been the significant problems in hardware development. The flexibility and recent progress in the gate size of FPGAs are expected to give solutions to the problems. As a first step to shogi hardware, we implemented modules to generate check and defense moves in tsume-shogi, or mating problems in shogi. With the latest FPGA, we successfully implemented all modules on a single chip and eliminated the bottleneck of memory bandwidth. In this paper we describe a procedure for parallel move generation in tsume-shogi hardware and architecture of the modules implemented on an FPGA. A discussion about the performance of the hardware is also included in the paper. The hardware is roughly estimated to work 10-50 times faster than software.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114788541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188661
T. Miyazaki, T. Murooka, N. Takahashi, M. Hashimoto
An active network node architecture, called Active Packet Editing (APE), is proposed. The main concept of APE is to accelerate functions essential to active network operation, such as packet classification and NAT (Network Address Translation). The twofold architecture of APE combines a software active packet processor with a high-speed hardware packet editor. Based on preset rules (pattern, action), the packet editor classifies and modifies packets passing through the node. Upon the receipt of active packets, the software active packet processor dynamically configures the packet editor. This paper focuses on introducing the high-speed packet editing mechanism which utilizes FPGAs (Field Programmable Gate Arrays) and CAMs (Content Addressable Memories). A prototype network node based on the architecture performs Gigabit-class throughput with packet editing.
{"title":"Real-time packet editing using reconfigurable hardware for active networking","authors":"T. Miyazaki, T. Murooka, N. Takahashi, M. Hashimoto","doi":"10.1109/FPT.2002.1188661","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188661","url":null,"abstract":"An active network node architecture, called Active Packet Editing (APE), is proposed. The main concept of APE is to accelerate functions essential to active network operation, such as packet classification and NAT (Network Address Translation). The twofold architecture of APE combines a software active packet processor with a high-speed hardware packet editor. Based on preset rules (pattern, action), the packet editor classifies and modifies packets passing through the node. Upon the receipt of active packets, the software active packet processor dynamically configures the packet editor. This paper focuses on introducing the high-speed packet editing mechanism which utilizes FPGAs (Field Programmable Gate Arrays) and CAMs (Content Addressable Memories). A prototype network node based on the architecture performs Gigabit-class throughput with packet editing.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131361066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188689
A. Fidjeland, W. Luk, S. Muggleton
Inductive logic programming systems are an emerging and powerful paradigm for machine learning which can make use of background knowledge to produce theories expressed in logic. They have been applied successfully to a wide range of problem domains, from protein structure prediction to satellite fault diagnosis. However, their execution can be computationally demanding. We introduce a scalable FPGA-based architecture for executing inductive logic programs, such that the execution speed largely increases linearly with respect to the number of processors. The architecture contains multiple processors derived from Warren's Abstract Machine, which has been optimised for hardware implementation using techniques such as instruction grouping and speculative assignment. The effectiveness of the architecture is demonstrated using the mutagenesis data set containing 12000 facts of chemical compounds.
{"title":"Scalable acceleration of inductive logic programs","authors":"A. Fidjeland, W. Luk, S. Muggleton","doi":"10.1109/FPT.2002.1188689","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188689","url":null,"abstract":"Inductive logic programming systems are an emerging and powerful paradigm for machine learning which can make use of background knowledge to produce theories expressed in logic. They have been applied successfully to a wide range of problem domains, from protein structure prediction to satellite fault diagnosis. However, their execution can be computationally demanding. We introduce a scalable FPGA-based architecture for executing inductive logic programs, such that the execution speed largely increases linearly with respect to the number of processors. The architecture contains multiple processors derived from Warren's Abstract Machine, which has been optimised for hardware implementation using techniques such as instruction grouping and speculative assignment. The effectiveness of the architecture is demonstrated using the mutagenesis data set containing 12000 facts of chemical compounds.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131615083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188669
Ju-wook Jang, S. Choi, V. Prasanna
We develop new algorithms and architectures for matrix multiplication on configurable hardware. These designs significantly reduce the latency as well as the area. Our designs improve the previous designs in terms of the area/speed metric where the speed denotes the maximum achievable running frequency. The area/speed metrics for the previous designs and our design are 14.45, 4.93, and 2.35, respectively, for 4 /spl times/ 4 matrix multiplication. The latency of one of the previous design is 0.57 /spl mu/s, while our design takes 0.15 /spl mu/s using 18% less area. The area of our designs is smaller by 11% - 46% compared with the best known systolic designs with the same latency for the matrices of sizes 3 /spl times/ 3 - 12 /spl times/ 12. The performance improvements tend to grow with the problem size.
{"title":"Area and time efficient implementations of matrix multiplication on FPGAs","authors":"Ju-wook Jang, S. Choi, V. Prasanna","doi":"10.1109/FPT.2002.1188669","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188669","url":null,"abstract":"We develop new algorithms and architectures for matrix multiplication on configurable hardware. These designs significantly reduce the latency as well as the area. Our designs improve the previous designs in terms of the area/speed metric where the speed denotes the maximum achievable running frequency. The area/speed metrics for the previous designs and our design are 14.45, 4.93, and 2.35, respectively, for 4 /spl times/ 4 matrix multiplication. The latency of one of the previous design is 0.57 /spl mu/s, while our design takes 0.15 /spl mu/s using 18% less area. The area of our designs is smaller by 11% - 46% compared with the best known systolic designs with the same latency for the matrices of sizes 3 /spl times/ 3 - 12 /spl times/ 12. The performance improvements tend to grow with the problem size.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125501851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188715
Teruyoshi Yamaguchi, T. Hashiyama, S. Okuma
This paper introduces a new encryption method for a block cipher. To keep the ciphertext safe, traditional methods usually use secret keys in simple fixed logic operations. To break the cipher, cryptanalysis has been developed. They use stochastic characteristics such as differential and linear relationships between the input and output data. Encryption algorithms must be secure against these analyses. The proposed method uses the secret key to modify substitution tables called S-Boxes in the encryption algorithm. They are reconfigured on demand using FPGA. Our method is hard enough to prevent the encrypted data from analyzing the secret key using statistical cryptanalysis.
{"title":"Dynamic reconfiguration for the common key encryption using FPGA","authors":"Teruyoshi Yamaguchi, T. Hashiyama, S. Okuma","doi":"10.1109/FPT.2002.1188715","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188715","url":null,"abstract":"This paper introduces a new encryption method for a block cipher. To keep the ciphertext safe, traditional methods usually use secret keys in simple fixed logic operations. To break the cipher, cryptanalysis has been developed. They use stochastic characteristics such as differential and linear relationships between the input and output data. Encryption algorithms must be secure against these analyses. The proposed method uses the secret key to modify substitution tables called S-Boxes in the encryption algorithm. They are reconfigured on demand using FPGA. Our method is hard enough to prevent the encrypted data from analyzing the secret key using statistical cryptanalysis.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"188 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117285442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188676
J. Coutinho, W. Luk
This paper presents a novel approach that focuses on rapid development and maintenance of optimised hardware designs using a high-level parallel language. We use an existing timing model that states, for instance, that every assignment executes in one clock cycle. This strict timing model gives users control over design scheduling, such as managing the number of cycles and cycle time. Our main contribution is the introduction of a flexible timing model that abstracts optimisation details by supporting high-level transformations and automatic scheduling. Furthermore, we provide techniques that unschedule parallel designs, so that they can be rescheduled to meet new performance and hardware constraints, making designs as implementation independent as possible. With both models, manual development and computerised optimisation can be interleaved to achieve the best effect. Our approach is illustrated by a case study where we port a pipelined convolver to another platform, and achieve either a 300% speedup or a 50% reduction in resource usage.
{"title":"Optimising and adapting high-level hardware designs","authors":"J. Coutinho, W. Luk","doi":"10.1109/FPT.2002.1188676","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188676","url":null,"abstract":"This paper presents a novel approach that focuses on rapid development and maintenance of optimised hardware designs using a high-level parallel language. We use an existing timing model that states, for instance, that every assignment executes in one clock cycle. This strict timing model gives users control over design scheduling, such as managing the number of cycles and cycle time. Our main contribution is the introduction of a flexible timing model that abstracts optimisation details by supporting high-level transformations and automatic scheduling. Furthermore, we provide techniques that unschedule parallel designs, so that they can be rescheduled to meet new performance and hardware constraints, making designs as implementation independent as possible. With both models, manual development and computerised optimisation can be interleaved to achieve the best effect. Our approach is illustrated by a case study where we port a pipelined convolver to another platform, and achieve either a 300% speedup or a 50% reduction in resource usage.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115063229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188679
S. Belkacemi, K. Benkrid, D. Crookes
This paper presents a high-level hardware description environment based on the logic programming language Prolog, called HIDE. The latter has been designed in an attempt to address the problem of abstract hardware design and hardware efficiency. HIDE provides more abstract hardware descriptions and compositions than are possible in traditional hardware description languages such as VHDL or Verilog. It enables highly scaleable and parameterised composition of blocks using a small set of constructors (e.g. horizontal, vertical composition), and generates pre-placed configurations in EDIF format for Xilinx Virtex FPGAs. The paper presents the syntax and semantics of HIDE and illustrates its use in the construction of a bit parallel multiplier core for Xilinx Virtex FPGAs.
{"title":"HIDE: a logic based hardware intelligent description environment","authors":"S. Belkacemi, K. Benkrid, D. Crookes","doi":"10.1109/FPT.2002.1188679","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188679","url":null,"abstract":"This paper presents a high-level hardware description environment based on the logic programming language Prolog, called HIDE. The latter has been designed in an attempt to address the problem of abstract hardware design and hardware efficiency. HIDE provides more abstract hardware descriptions and compositions than are possible in traditional hardware description languages such as VHDL or Verilog. It enables highly scaleable and parameterised composition of blocks using a small set of constructors (e.g. horizontal, vertical composition), and generates pre-placed configurations in EDIF format for Xilinx Virtex FPGAs. The paper presents the syntax and semantics of HIDE and illustrates its use in the construction of a bit parallel multiplier core for Xilinx Virtex FPGAs.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126365425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188662
O. Cheung, P. Leong
Virtual Private Networks (VPN) are becoming increasingly popular network architectures for corporate networks. As VPNs are built on the Internet infrastructure, the data exchange among different local area networks will be passed through the Internet and thus can be easily eavesdropped, masqueraded, etc. Therefore, certain security measures must be used to deal with these privacy issues. The Internet Protocol Security (IPSec) by the Internet Engineering Task Force (IETF) addresses the abovementioned security issues and the Free Secure Wide Area Network (FreeS/WAN) is an open source software implementation of IPSec for Linux which uses triple-DES as the default encryption mode. As shown in this paper, the performance of FreeS/WAN with IPSec is 50% of that without encryption. In order to improve its performance, a field programmable gate array (FPGA) based triple-DES accelerator was built on a reconfigurable computing development platform called Pilchard and achieved a throughput of more than 120 Mb/sec for triple-DES in cipher-block chaining mode, a speedup of 3 over a software implementation, Measurements show that an FPGA-accelerated FreeS/WAN offers a 30% speedup for the TCP protocol over the original software library.
{"title":"Implementation of an FPGA based accelerator for virtual private networks","authors":"O. Cheung, P. Leong","doi":"10.1109/FPT.2002.1188662","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188662","url":null,"abstract":"Virtual Private Networks (VPN) are becoming increasingly popular network architectures for corporate networks. As VPNs are built on the Internet infrastructure, the data exchange among different local area networks will be passed through the Internet and thus can be easily eavesdropped, masqueraded, etc. Therefore, certain security measures must be used to deal with these privacy issues. The Internet Protocol Security (IPSec) by the Internet Engineering Task Force (IETF) addresses the abovementioned security issues and the Free Secure Wide Area Network (FreeS/WAN) is an open source software implementation of IPSec for Linux which uses triple-DES as the default encryption mode. As shown in this paper, the performance of FreeS/WAN with IPSec is 50% of that without encryption. In order to improve its performance, a field programmable gate array (FPGA) based triple-DES accelerator was built on a reconfigurable computing development platform called Pilchard and achieved a throughput of more than 120 Mb/sec for triple-DES in cipher-block chaining mode, a speedup of 3 over a software implementation, Measurements show that an FPGA-accelerated FreeS/WAN offers a 30% speedup for the TCP protocol over the original software library.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127899517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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