Pub Date : 2002-12-16DOI: 10.1109/FPT.2002.1188720
S. Melnikoff, S. Quigley, M. Russell
Speech recognition is a computationally demanding task, particularly the stages which use Viterbi decoding for converting pre-processed speech data into words or subword unit, and the associated observation probability calculations, which employ multivariate Gaussian distributions; so any device that can reduce the load on, for example, a PC's processor, is advantageous. Hence we present two implementations of a speech recognition system incorporating an FPGA, employing continuous hidden Markov models (HMMs), and capable of processing three speech files simultaneously. The first uses monophones, and can perform recognition 250 times real time (in terms of average time per observation), as well as outperforming its software equivalent. The second uses biphones and triphones, reducing the speedup to 13 times real time.
{"title":"Performing speech recognition on multiple parallel files using continuous hidden Markov models on an FPGA","authors":"S. Melnikoff, S. Quigley, M. Russell","doi":"10.1109/FPT.2002.1188720","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188720","url":null,"abstract":"Speech recognition is a computationally demanding task, particularly the stages which use Viterbi decoding for converting pre-processed speech data into words or subword unit, and the associated observation probability calculations, which employ multivariate Gaussian distributions; so any device that can reduce the load on, for example, a PC's processor, is advantageous. Hence we present two implementations of a speech recognition system incorporating an FPGA, employing continuous hidden Markov models (HMMs), and capable of processing three speech files simultaneously. The first uses monophones, and can perform recognition 250 times real time (in terms of average time per observation), as well as outperforming its software equivalent. The second uses biphones and triphones, reducing the speedup to 13 times real time.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126079626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/FPT.2002.1188702
S. J. Visser, Anwar S. Dawood, John A. Williams
Satellites and other space-based signal processing systems face a challenging operating environment. In addition to radiation related effects, the satellites themselves are often electrically noisy, resulting in high levels of noise and interference in data signals. Digital signal processing systems such as adaptive filters are vital components for the next generation of satellites. Most current satellite systems have limited computing resources for on-board digital signal processing and lack flexibility to adapt to changing operation requirements. The deployment of reconfigurable field programmable gate array (FPGA) technology on-board satellites is a very promising solution for digital signal processing in space, as they offer flexibility, scalability and high performance. The high performance computing (HPC-I) payload integrated into the Australian scientific mission satellite FedSat is designed to evaluate the deployment of FPGA technology for a variety of space applications. This paper elaborates on implementing rule-based adaptive filtering techniques on FPGAs for space applications, presenting the design and implementation of an adaptive finite impulse response (FIR) filter on HPC-I. A fuzzy adaptive image filtering algorithm for remote sensing applications is also considered.
{"title":"FPGA based real-time adaptive filtering for space applications","authors":"S. J. Visser, Anwar S. Dawood, John A. Williams","doi":"10.1109/FPT.2002.1188702","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188702","url":null,"abstract":"Satellites and other space-based signal processing systems face a challenging operating environment. In addition to radiation related effects, the satellites themselves are often electrically noisy, resulting in high levels of noise and interference in data signals. Digital signal processing systems such as adaptive filters are vital components for the next generation of satellites. Most current satellite systems have limited computing resources for on-board digital signal processing and lack flexibility to adapt to changing operation requirements. The deployment of reconfigurable field programmable gate array (FPGA) technology on-board satellites is a very promising solution for digital signal processing in space, as they offer flexibility, scalability and high performance. The high performance computing (HPC-I) payload integrated into the Australian scientific mission satellite FedSat is designed to evaluate the deployment of FPGA technology for a variety of space applications. This paper elaborates on implementing rule-based adaptive filtering techniques on FPGAs for space applications, presenting the design and implementation of an adaptive finite impulse response (FIR) filter on HPC-I. A fuzzy adaptive image filtering algorithm for remote sensing applications is also considered.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126709773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/FPT.2002.1188698
Anwar S. Dawood, John A. Williams, S. J. Visser
Remote sensing satellites operate almost exclusively in a store-and-forward mode, with acquired imagery stored on board until being downlinked when ground stations come within view. Space-borne imaging sensors generate tremendous volumes of data at very high rates, however storage capacity and communication bandwidth are expensive satellite resources. By compressing the images as they are acquired, better use is made of available storage and bandwidth capacity. Reconfigurable computing technology, which combines the flexibility of traditional microprocessors with the performance of ASIC devices, is very promising for space applications. The High Performance Computing (HPC-I) payload, based on a radiation hardened reconfigurable FPGA has been developed and integrated into the Australian scientific mission satellite FedSat. HPC-I is a testbed in space to validate reconfigurable logic for a variety of satellite applications. The design and implementation on HPC-I of the On-Board Image Compression System (OBICS) is presented, and its compression performance evaluated using JPEG standard as a benchmark. The results indicate that FPGAs and HPC-I are suitable platforms for such systems, and that satisfactory compression can only be achieved with moderately complex logic designs.
{"title":"On-board satellite image compression using reconfigurable FPGAs","authors":"Anwar S. Dawood, John A. Williams, S. J. Visser","doi":"10.1109/FPT.2002.1188698","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188698","url":null,"abstract":"Remote sensing satellites operate almost exclusively in a store-and-forward mode, with acquired imagery stored on board until being downlinked when ground stations come within view. Space-borne imaging sensors generate tremendous volumes of data at very high rates, however storage capacity and communication bandwidth are expensive satellite resources. By compressing the images as they are acquired, better use is made of available storage and bandwidth capacity. Reconfigurable computing technology, which combines the flexibility of traditional microprocessors with the performance of ASIC devices, is very promising for space applications. The High Performance Computing (HPC-I) payload, based on a radiation hardened reconfigurable FPGA has been developed and integrated into the Australian scientific mission satellite FedSat. HPC-I is a testbed in space to validate reconfigurable logic for a variety of satellite applications. The design and implementation on HPC-I of the On-Board Image Compression System (OBICS) is presented, and its compression performance evaluated using JPEG standard as a benchmark. The results indicate that FPGAs and HPC-I are suitable platforms for such systems, and that satisfactory compression can only be achieved with moderately complex logic designs.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116616818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/FPT.2002.1188711
N. Bergmann
Reconfigurable computing technology (RCT) has provided an alternative to conventional von-Neumann computing which is academically intriguing but of marginal commercial interest to mainstream desktop and supercomputer communities. This paper describes a number of key enabling technologies in the form of an overall design methodology which need to be developed in order to make embedded RCT an effective implementation technology. The paper also describes some first steps that our research group is making in developing these technologies.
{"title":"Enabling technologies for reconfigurable system-on-chip","authors":"N. Bergmann","doi":"10.1109/FPT.2002.1188711","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188711","url":null,"abstract":"Reconfigurable computing technology (RCT) has provided an alternative to conventional von-Neumann computing which is academically intriguing but of marginal commercial interest to mainstream desktop and supercomputer communities. This paper describes a number of key enabling technologies in the form of an overall design methodology which need to be developed in order to make embedded RCT an effective implementation technology. The paper also describes some first steps that our research group is making in developing these technologies.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132040224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/FPT.2002.1188678
B. Mei, S. Vernalde, D. Verkest, H. Man, R. Lauwereins
Coarse-grained reconfigurable architectures have become increasingly important in recent years. Automatic design or compiling tools are essential to their success. In this paper, we present a retargetable compiler for a family of coarse-grained reconfigurable architectures. Several key issues are addressed. Program analysis and transformation prepare dataflow for scheduling. Architecture abstraction generates an internal graph representation from a concrete architecture description. A modulo scheduling algorithm is key to exploit parallelism and achieve high performance. The experimental results show up to 28.7 instructions per cycle (IPC) over tested kernels.
{"title":"DRESC: a retargetable compiler for coarse-grained reconfigurable architectures","authors":"B. Mei, S. Vernalde, D. Verkest, H. Man, R. Lauwereins","doi":"10.1109/FPT.2002.1188678","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188678","url":null,"abstract":"Coarse-grained reconfigurable architectures have become increasingly important in recent years. Automatic design or compiling tools are essential to their success. In this paper, we present a retargetable compiler for a family of coarse-grained reconfigurable architectures. Several key issues are addressed. Program analysis and transformation prepare dataflow for scheduling. Architecture abstraction generates an internal graph representation from a concrete architecture description. A modulo scheduling algorithm is key to exploit parallelism and achieve high performance. The experimental results show up to 28.7 instructions per cycle (IPC) over tested kernels.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123288194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/FPT.2002.1188732
Yu-Tsang Chang, Yu-Te Chou, W. Tsai, J. Wang, Chen-Yi Lee
The role of Chip Implementation Center (CIC), founded in 1992 under the National Science Council (NSC) of Taiwan R.O.C., is to provide the services for the fabrication of multi-project chip (MPC), the procurement/integration of software CAD tools, and the promotion of IC and FPGA design/testing/CAD software technology for academia in Taiwan. To date, CIC assisted 86 universities and polytechnics to install over 6000 academic licenses of FPGA design and verification tools. Moreover, CIC promotes various training courses intensively and periodically for the FPGA design flow. In year 2002, 8 kinds of courses with over 25 classes are provided to meet the demands from academia sites. More than 1000 students are trained in these classes. The FPGA design flow, provided by CIC, is used in many of researches for implementation, verification, and prototypes. Based on the demands of academics, CIC will build a laboratory for rapid prototyping system-level design. In this laboratory, SoC (System on a Chip) and IP (Intellectual Property) designs can be downloaded into FPGA to work with a processor to verification on an SOPC (System on Programmable Chip) environment.
{"title":"FPGA education and research activities in Taiwan","authors":"Yu-Tsang Chang, Yu-Te Chou, W. Tsai, J. Wang, Chen-Yi Lee","doi":"10.1109/FPT.2002.1188732","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188732","url":null,"abstract":"The role of Chip Implementation Center (CIC), founded in 1992 under the National Science Council (NSC) of Taiwan R.O.C., is to provide the services for the fabrication of multi-project chip (MPC), the procurement/integration of software CAD tools, and the promotion of IC and FPGA design/testing/CAD software technology for academia in Taiwan. To date, CIC assisted 86 universities and polytechnics to install over 6000 academic licenses of FPGA design and verification tools. Moreover, CIC promotes various training courses intensively and periodically for the FPGA design flow. In year 2002, 8 kinds of courses with over 25 classes are provided to meet the demands from academia sites. More than 1000 students are trained in these classes. The FPGA design flow, provided by CIC, is used in many of researches for implementation, verification, and prototypes. Based on the demands of academics, CIC will build a laboratory for rapid prototyping system-level design. In this laboratory, SoC (System on a Chip) and IP (Intellectual Property) designs can be downloaded into FPGA to work with a processor to verification on an SOPC (System on Programmable Chip) environment.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128590058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/FPT.2002.1188734
H. Ip, James D. Low, P. Cheung, G. Constantinides, W. Luk, S. P. Seng, P. Metzgen
Strassen's algorithm is an efficient method for multiplying large matrices. We explore various ways of mapping Strassen's algorithm into reconfigurable hardware that contains one or more customisable instruction processors. Our approach has been implemented using Nios processors with custom instructions and with custom-designed coprocessors, taking advantage of the additional logic and memory blocks available on a reconfigurable platform.
{"title":"Strassen's matrix multiplication for customisable processors","authors":"H. Ip, James D. Low, P. Cheung, G. Constantinides, W. Luk, S. P. Seng, P. Metzgen","doi":"10.1109/FPT.2002.1188734","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188734","url":null,"abstract":"Strassen's algorithm is an efficient method for multiplying large matrices. We explore various ways of mapping Strassen's algorithm into reconfigurable hardware that contains one or more customisable instruction processors. Our approach has been implemented using Nios processors with custom instructions and with custom-designed coprocessors, taking advantage of the additional logic and memory blocks available on a reconfigurable platform.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125963004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/FPT.2002.1188671
John A. Williams, Anwar S. Dawood, S. J. Visser
Reconfigurable computing is an enabling technology for real-time image processing onboard remote sensing satellites. This can potentially reduce the delay between image capture, analysis and action, and also reduce onboard storage and downlink capacity requirements. This paper discusses the design and implementation of a real-time cloud detection system intended for use within an onboard remote sensing platform. The High Performance Computing (HPC-1) payload, designed and developed for the Australian scientific satellite FedSat, is briefly introduced as a demonstration of onboard processing in space using reconfigurable logic. A high level conceptual design of the proposed remote sensing system is provided, before details of the cloud detection design and implementation are presented. Results from simulation and testing demonstrate very promising performance in terms of data throughput and detection capabilities.
{"title":"FPGA-based cloud detection for real-time onboard remote sensing","authors":"John A. Williams, Anwar S. Dawood, S. J. Visser","doi":"10.1109/FPT.2002.1188671","DOIUrl":"https://doi.org/10.1109/FPT.2002.1188671","url":null,"abstract":"Reconfigurable computing is an enabling technology for real-time image processing onboard remote sensing satellites. This can potentially reduce the delay between image capture, analysis and action, and also reduce onboard storage and downlink capacity requirements. This paper discusses the design and implementation of a real-time cloud detection system intended for use within an onboard remote sensing platform. The High Performance Computing (HPC-1) payload, designed and developed for the Australian scientific satellite FedSat, is briefly introduced as a demonstration of onboard processing in space using reconfigurable logic. A high level conceptual design of the proposed remote sensing system is provided, before details of the cloud detection design and implementation are presented. Results from simulation and testing demonstrate very promising performance in terms of data throughput and detection capabilities.","PeriodicalId":355740,"journal":{"name":"2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.","volume":"20 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129332004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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