Pub Date : 2003-08-25DOI: 10.1109/LPE.2003.1231956
F. Koushanfar, A. Davare, D. Nguyen, M. Potkonjak, A. Sangiovanni-Vincentelli
Distributed wireless ad-hoc networks (DWANs) pose numerous technical challenges. Among them, two are widely considered as crucial: autonomous localized operation and minimization of energy consumption. We address the fundamental problem of how to maximize the life-time of the network by using only local information while preserving network connectivity. We start by introducing the care-free sleep (CS) theorem that provides provably optimal necessary and sufficient conditions for a node to turn off its radio while ensuring that global connectivity is not affected. The CS theorem is the basis for an efficient localized algorithm that decides which node will turn its radio off, and for how long. The effectiveness of the approach is demonstrated using numerous simulations of the performance of the algorithm over a wide range of network parameters.
{"title":"Low power coordination in wireless ad-hoc networks","authors":"F. Koushanfar, A. Davare, D. Nguyen, M. Potkonjak, A. Sangiovanni-Vincentelli","doi":"10.1109/LPE.2003.1231956","DOIUrl":"https://doi.org/10.1109/LPE.2003.1231956","url":null,"abstract":"Distributed wireless ad-hoc networks (DWANs) pose numerous technical challenges. Among them, two are widely considered as crucial: autonomous localized operation and minimization of energy consumption. We address the fundamental problem of how to maximize the life-time of the network by using only local information while preserving network connectivity. We start by introducing the care-free sleep (CS) theorem that provides provably optimal necessary and sufficient conditions for a node to turn off its radio while ensuring that global connectivity is not affected. The CS theorem is the basis for an efficient localized algorithm that decides which node will turn its radio off, and for how long. The effectiveness of the approach is demonstrated using numerous simulations of the performance of the algorithm over a wide range of network parameters.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"59 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130357193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A high performance and low power clock delayed sleep mode (CDSM) domino logic is proposed for wide fan-in domino logic. The CDSM-domino logic not only improves the robustness but also reduces the active and stand-by power. The proposed scheme reduces delay by 21%, dynamic power by 16%, and leakage power by 91% respectively compared to the typical wide fan-in domino logic in 0.18 /spl mu/m CMOS technology. In addition, the sleep mode entrance power is reduced to 10/sup -5/ of the HS-domino logic.
{"title":"A clock delayed sleep mode domino logic for wide dynamic OR gate","authors":"Kwang-Il Oh, L. Kim","doi":"10.1145/871506.871550","DOIUrl":"https://doi.org/10.1145/871506.871550","url":null,"abstract":"A high performance and low power clock delayed sleep mode (CDSM) domino logic is proposed for wide fan-in domino logic. The CDSM-domino logic not only improves the robustness but also reduces the active and stand-by power. The proposed scheme reduces delay by 21%, dynamic power by 16%, and leakage power by 91% respectively compared to the typical wide fan-in domino logic in 0.18 /spl mu/m CMOS technology. In addition, the sleep mode entrance power is reduced to 10/sup -5/ of the HS-domino logic.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120957751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Inseok Choi, Hyung Soo Kim, Heonshik Shin, N. Chang
The Java platform provides a fully fledged programming environment for graphics applications using the Abstract Window Toolkit (AWT). We present a power-aware basis profile of the Java 2 Micro Edition (J2ME) for embedded applications. The low-power basis profile (LPBP) is responsive to backlight luminance scaling in such a way that dynamic adjustment of the backlight luminance is accompanied by adaptive image compensation. The proposed scheme performs aggressive backlight dimming while maintaining the readability of screen contents based on image compensation techniques such as brightness compensation, image enhancement and context processing. Experiments show that on average the LPBP can easily achieve approximately 30% backlight system power reduction.
{"title":"LPBP: low-power basis profile of the Java 2 Micro Edition","authors":"Inseok Choi, Hyung Soo Kim, Heonshik Shin, N. Chang","doi":"10.1145/871506.871519","DOIUrl":"https://doi.org/10.1145/871506.871519","url":null,"abstract":"The Java platform provides a fully fledged programming environment for graphics applications using the Abstract Window Toolkit (AWT). We present a power-aware basis profile of the Java 2 Micro Edition (J2ME) for embedded applications. The low-power basis profile (LPBP) is responsive to backlight luminance scaling in such a way that dynamic adjustment of the backlight luminance is accompanied by adaptive image compensation. The proposed scheme performs aggressive backlight dimming while maintaining the readability of screen contents based on image compensation techniques such as brightness compensation, image enhancement and context processing. Experiments show that on average the LPBP can easily achieve approximately 30% backlight system power reduction.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126542625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Won, Kyorai Kim, Kwang-Ok Jeong, Ki-Tae Park, Kyu-Myung Choi, J. Kong
The multi-threshold CMOS (MTCMOS) technology provides a solution to the high performance and low power design requirements of modern designs. While the low V/sub th/ transistors are used to implement the desired function, the high V/sub th/ transistors are used to cut off the leakage current. In this paper, we (i) examine the effectiveness of the MTCMOS technology for Samsung's 0.18 /spl mu/m process, (ii) propose a new special flip-flop which keeps valid data during the sleep mode, and (iii) develop a methodology which takes into account the new design issues related to the MTCMOS technology. Towards validating the proposed technique, a personal digital assistant (PDA) processor has been implemented using the MTCMOS design methodology, and the 0.18 /spl mu/m process. The fabricated PDA processor operates at 333 MHz, and consumes about 2 /spl mu/W of leakage power. Whereas the performance of the MTCMOS implementation is the same as that of the generic CMOS implementation, three orders of reduction in the leakage power has been achieved.
{"title":"An MTCMOS design methodology and its application to mobile computing","authors":"H. Won, Kyorai Kim, Kwang-Ok Jeong, Ki-Tae Park, Kyu-Myung Choi, J. Kong","doi":"10.1145/871506.871536","DOIUrl":"https://doi.org/10.1145/871506.871536","url":null,"abstract":"The multi-threshold CMOS (MTCMOS) technology provides a solution to the high performance and low power design requirements of modern designs. While the low V/sub th/ transistors are used to implement the desired function, the high V/sub th/ transistors are used to cut off the leakage current. In this paper, we (i) examine the effectiveness of the MTCMOS technology for Samsung's 0.18 /spl mu/m process, (ii) propose a new special flip-flop which keeps valid data during the sleep mode, and (iii) develop a methodology which takes into account the new design issues related to the MTCMOS technology. Towards validating the proposed technique, a personal digital assistant (PDA) processor has been implemented using the MTCMOS design methodology, and the 0.18 /spl mu/m process. The fabricated PDA processor operates at 333 MHz, and consumes about 2 /spl mu/W of leakage power. Whereas the performance of the MTCMOS implementation is the same as that of the generic CMOS implementation, three orders of reduction in the leakage power has been achieved.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125665768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Lowering active power dissipation is increasingly important for battery powered embedded microprocessors. Here, power reduction techniques applicable to fully associative translation lookaside buffers, as well as other associative structures and dynamic register files, are described. Powermill simulations of implementation in a microprocessor on 0.18 /spl mu/m process technology demonstrate 42% power savings. Circuit implementations, as well as. architectural simulations demonstrating applicability to typical instruction mixes are shown.
{"title":"Reducing translation lookaside buffer active power","authors":"L. Clark, Byungwoo Choi, M. Wilkerson","doi":"10.1145/871506.871512","DOIUrl":"https://doi.org/10.1145/871506.871512","url":null,"abstract":"Lowering active power dissipation is increasingly important for battery powered embedded microprocessors. Here, power reduction techniques applicable to fully associative translation lookaside buffers, as well as other associative structures and dynamic register files, are described. Powermill simulations of implementation in a microprocessor on 0.18 /spl mu/m process technology demonstrate 42% power savings. Circuit implementations, as well as. architectural simulations demonstrating applicability to typical instruction mixes are shown.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121733445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-08-25DOI: 10.1109/LPE.2003.1231954
Sung I. Park, V. Raghunathan, M. Srivastava
This paper presents techniques for optimizing the energy efficiency of multi-resource, multi-tasking embedded systems. Low power design of individual system resources, such as embedded processors, has been extensively studied in the past. However, system-level techniques, such as those presented in this paper, which exploit the synergy between various system resources, achieve levels of energy efficiency that cannot be obtained by considering individual resources independently. We demonstrate that, in multi-resource embedded systems that concurrently execute multiple applications, there exists a tradeoff between resource management efficiency and resource allocation fairness. By solving the multi-resource energy optimization problem in the context of an embedded sensor system, we show that our techniques enable the system designer to traverse this efficiency-fairness tradeoff space.
{"title":"Energy efficiency and fairness tradeoffs in multi-resource, multi-tasking embedded systems","authors":"Sung I. Park, V. Raghunathan, M. Srivastava","doi":"10.1109/LPE.2003.1231954","DOIUrl":"https://doi.org/10.1109/LPE.2003.1231954","url":null,"abstract":"This paper presents techniques for optimizing the energy efficiency of multi-resource, multi-tasking embedded systems. Low power design of individual system resources, such as embedded processors, has been extensively studied in the past. However, system-level techniques, such as those presented in this paper, which exploit the synergy between various system resources, achieve levels of energy efficiency that cannot be obtained by considering individual resources independently. We demonstrate that, in multi-resource embedded systems that concurrently execute multiple applications, there exists a tradeoff between resource management efficiency and resource allocation fairness. By solving the multi-resource energy optimization problem in the context of an embedded sensor system, we show that our techniques enable the system designer to traverse this efficiency-fairness tradeoff space.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"25 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132033289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Tag comparison elimination (TCE) is an effective approach to reduce I-cache energy. Current research focuses on finding good tradeoffs between hardware cost and percentage of comparisons that can be removed. For this purpose, two low cost innovations are proposed in this paper. We design a small dedicated TCE table whose size is flexible both horizontally (entry size) and vertically (number of entries). The design also minimizes interactions with the I-cache. For a 64-way 16K cache, the new design reduces the tag comparisons to 4.0% with a fraction only 20% of the hardware cost of the way memoization technique. The result is 40% better compared to a recent proposed low cost design of comparable hardware cost.
{"title":"Low cost instruction cache designs for tag comparison elimination","authors":"Youtao Zhang, Jun Yang","doi":"10.1145/871506.871572","DOIUrl":"https://doi.org/10.1145/871506.871572","url":null,"abstract":"Tag comparison elimination (TCE) is an effective approach to reduce I-cache energy. Current research focuses on finding good tradeoffs between hardware cost and percentage of comparisons that can be removed. For this purpose, two low cost innovations are proposed in this paper. We design a small dedicated TCE table whose size is flexible both horizontally (entry size) and vertically (number of entries). The design also minimizes interactions with the I-cache. For a 64-way 16K cache, the new design reduces the tag comparisons to 4.0% with a fraction only 20% of the hardware cost of the way memoization technique. The result is 40% better compared to a recent proposed low cost design of comparable hardware cost.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133959064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Carlos Molina, Carles Aliagas, Montse Garcia, Antonio González, Jordi Tubella
Current microprocessors spend a huge percentage of the die area to implement the memory hierarchy. Moreover, cache memory is responsible for a significant percentage of the total energy consumption. This paper presents a novel data cache design to reduce its die area, power dissipation and latency. The new scheme, called Non Redundant Cache (NRC), exploits the immense amount of value replication observed in traditional data caches. The NRC cache significantly reduces the storage requirements by avoiding the replication of values. Results show that the NRC cache reduces the die area in a 32%, the power dissipation by 14% and the latency by 25%, while maintaining the miss ratio of a conventional cache.
{"title":"Non redundant data cache","authors":"Carlos Molina, Carles Aliagas, Montse Garcia, Antonio González, Jordi Tubella","doi":"10.1145/871506.871574","DOIUrl":"https://doi.org/10.1145/871506.871574","url":null,"abstract":"Current microprocessors spend a huge percentage of the die area to implement the memory hierarchy. Moreover, cache memory is responsible for a significant percentage of the total energy consumption. This paper presents a novel data cache design to reduce its die area, power dissipation and latency. The new scheme, called Non Redundant Cache (NRC), exploits the immense amount of value replication observed in traditional data caches. The NRC cache significantly reduces the storage requirements by avoiding the replication of values. Results show that the NRC cache reduces the die area in a 32%, the power dissipation by 14% and the latency by 25%, while maintaining the miss ratio of a conventional cache.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128891261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Power will be the key limiter to system scalability as interconnection networks take up an increasingly significant portion of system power. In this paper, we propose an architectural leakage power modeling methodology that achieves 95-98% accuracy against HSPICE estimates. When applied to interconnection networks, combined with previous proposed dynamic power models, we gain valuable insights on total network power consumption. Our modeling shows router buffers to be a prime candidate for leakage power optimization. We thus investigate the design space of power-aware buffer policies, propose a suite of policies, and explore the impact of various circuits mechanisms on these policies. Simulations show power-aware buffers saving up to 96.6% of total buffer leakage power.
{"title":"Leakage power modeling and optimization in interconnection networks","authors":"Xuning Chen, L. Peh","doi":"10.1145/871506.871531","DOIUrl":"https://doi.org/10.1145/871506.871531","url":null,"abstract":"Power will be the key limiter to system scalability as interconnection networks take up an increasingly significant portion of system power. In this paper, we propose an architectural leakage power modeling methodology that achieves 95-98% accuracy against HSPICE estimates. When applied to interconnection networks, combined with previous proposed dynamic power models, we gain valuable insights on total network power consumption. Our modeling shows router buffers to be a prime candidate for leakage power optimization. We thus investigate the design space of power-aware buffer policies, propose a suite of policies, and explore the impact of various circuits mechanisms on these policies. Simulations show power-aware buffers saving up to 96.6% of total buffer leakage power.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133794775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Energy constrained systems such as sensor networks can increase their usable lifetimes by extracting energy from their environment. However, environmental energy will typically not be spread homogeneously over the spread of the network. We argue that significant improvements in usable system lifetime can be achieved if the task allocation is aligned with the spatio-temporal characteristics of energy availability. To the best of our knowledge, this problem has not been addressed before. We present a distributed framework for the sensor network to adaptively learn its energy environment and give localized algorithms to use this information for task sharing among nodes. Our framework allows the system to exploit its energy resources more efficiently, thus increasing its lifetime. These gains are in addition to those from utilizing sleep modes and residual energy based scheduling mechanisms. Performance studies for an experimental energy environment show up to 200% improvement in lifetime.
{"title":"An environmental energy harvesting framework for sensor networks","authors":"A. Kansal, M. Srivastava","doi":"10.1145/871506.871624","DOIUrl":"https://doi.org/10.1145/871506.871624","url":null,"abstract":"Energy constrained systems such as sensor networks can increase their usable lifetimes by extracting energy from their environment. However, environmental energy will typically not be spread homogeneously over the spread of the network. We argue that significant improvements in usable system lifetime can be achieved if the task allocation is aligned with the spatio-temporal characteristics of energy availability. To the best of our knowledge, this problem has not been addressed before. We present a distributed framework for the sensor network to adaptively learn its energy environment and give localized algorithms to use this information for task sharing among nodes. Our framework allows the system to exploit its energy resources more efficiently, thus increasing its lifetime. These gains are in addition to those from utilizing sleep modes and residual energy based scheduling mechanisms. Performance studies for an experimental energy environment show up to 200% improvement in lifetime.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124103856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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