J. Plouchart, Jonghae Kim, H. Recoules, N. Zamdmer, Yue Tan, M. Sherony, A. Ray, L. Wagner
A static frequency divider by 8 was fabricated in a 120 nm SOI technology. The highest operation frequency achieved is 8.25 GHz at 1.5 V power supply. The lowest core power consumption achieved is 0.016 mW at 4 GHz when the lowest operating voltage supply of 0.75 V is used.
{"title":"A 0.123 mW 7.25 GHz static frequency divider by 8 in a 120-nm SOI technology","authors":"J. Plouchart, Jonghae Kim, H. Recoules, N. Zamdmer, Yue Tan, M. Sherony, A. Ray, L. Wagner","doi":"10.1145/871506.871615","DOIUrl":"https://doi.org/10.1145/871506.871615","url":null,"abstract":"A static frequency divider by 8 was fabricated in a 120 nm SOI technology. The highest operation frequency achieved is 8.25 GHz at 1.5 V power supply. The lowest core power consumption achieved is 0.016 mW at 4 GHz when the lowest operating voltage supply of 0.75 V is used.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130335845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
David Nguyen, A. Davare, M. Orshansky, D. Chinnery, B. Thompson, K. Keutzer
We describe an optimization strategy for minimizing total power consumption using dual threshold voltage (Vth) technology. Significant power savings are possible by simultaneous assignment of Vth with gate sizing. We propose an efficient algorithm based on linear programming that jointly performs Vth assignment and gate sizing to minimize total power under delay constraints. First, linear programming assigns the optimal amounts of slack to gates based on power-delay sensitivity. Then, an optimal gate configuration, in terms of Vth and transistor sizes, is selected by an exhaustive local search. Benchmark results for the algorithm show 32% reduction in power consumption on average, compared to sizing only power minimization. There is up to a 57% reduction for some circuits. The flow can be extended to dual supply voltage libraries to yield further power savings.
{"title":"Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization [logic IC design]","authors":"David Nguyen, A. Davare, M. Orshansky, D. Chinnery, B. Thompson, K. Keutzer","doi":"10.1145/871506.871545","DOIUrl":"https://doi.org/10.1145/871506.871545","url":null,"abstract":"We describe an optimization strategy for minimizing total power consumption using dual threshold voltage (Vth) technology. Significant power savings are possible by simultaneous assignment of Vth with gate sizing. We propose an efficient algorithm based on linear programming that jointly performs Vth assignment and gate sizing to minimize total power under delay constraints. First, linear programming assigns the optimal amounts of slack to gates based on power-delay sensitivity. Then, an optimal gate configuration, in terms of Vth and transistor sizes, is selected by an exhaustive local search. Benchmark results for the algorithm show 32% reduction in power consumption on average, compared to sizing only power minimization. There is up to a 57% reduction for some circuits. The flow can be extended to dual supply voltage libraries to yield further power savings.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127174341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Rapid advancement of semiconductor, personal computing, and mobile communications technology during the last few decades has been transforming lifestyle into "digital lifestyle", in which one can create, share, and enjoy multimedia information in a personalized virtual space in a mobile environment. There are, in general, three key enabling factors to realize the future digital lifestyle: easily accessible multimedia contents for diversified user applications, communication and information infrastructure to support such access from the user, and intelligent user devices to deliver such digital contents in a user friendly manner. In this talk, future prospects of user devices in consumer electronics space and associated technological challenges, especially low power aspects, are discussed. A brief overview of the current status of low power technology employed by many portable devices and wireless data collection systems is followed by the suggestion of future research areas for low power user devices in the areas of portable power sources, components, software architecture, and SOC (system-on-chip) technology. Finally, Samsung's R&D strategy in low power technology is discussed.
{"title":"Low power requirements for future digital life style","authors":"Ki Won Lee","doi":"10.1145/871506.871508","DOIUrl":"https://doi.org/10.1145/871506.871508","url":null,"abstract":"Rapid advancement of semiconductor, personal computing, and mobile communications technology during the last few decades has been transforming lifestyle into \"digital lifestyle\", in which one can create, share, and enjoy multimedia information in a personalized virtual space in a mobile environment. There are, in general, three key enabling factors to realize the future digital lifestyle: easily accessible multimedia contents for diversified user applications, communication and information infrastructure to support such access from the user, and intelligent user devices to deliver such digital contents in a user friendly manner. In this talk, future prospects of user devices in consumer electronics space and associated technological challenges, especially low power aspects, are discussed. A brief overview of the current status of low power technology employed by many portable devices and wireless data collection systems is followed by the suggestion of future research areas for low power user devices in the areas of portable power sources, components, software architecture, and SOC (system-on-chip) technology. Finally, Samsung's R&D strategy in low power technology is discussed.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"88 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128302583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A new architectural technique to reduce power dissipation in data caches is proposed. In multimedia applications, a major portion of data cache accesses hit in the same cache set continuously before going to a different set. This feature allows us to remove unnecessary driving power in data arrays as long as the same cache set is accessed incessantly. Power saving is achieved through buffering and accessing the cache set instead of the main data array. The proposed technique does not incur performance degradation and accomplishes up to 57% of power reduction for data caches.
{"title":"Lightweight set buffer: low power data cache for multimedia application","authors":"Jun Yang, Youtao Zhang","doi":"10.1145/871506.871573","DOIUrl":"https://doi.org/10.1145/871506.871573","url":null,"abstract":"A new architectural technique to reduce power dissipation in data caches is proposed. In multimedia applications, a major portion of data cache accesses hit in the same cache set continuously before going to a different set. This feature allows us to remove unnecessary driving power in data arrays as long as the same cache set is accessed incessantly. Power saving is achieved through buffering and accessing the cache set instead of the main data array. The proposed technique does not incur performance degradation and accomplishes up to 57% of power reduction for data caches.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123498947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We introduce an architectural-level power, area, and latency estimator for multi-ported, pipelined register files. Strengths of the proposed approach include the handling of pipelined operation and clock power, the simulation-based device size estimation, and the ability to handle user-specified timing constraints. The model proposed can be used as a standalone estimation and design exploration tool for register files and register-file type structures, or it can be incorporated into a high-level performance simulator to add power estimation capabilities.
{"title":"ESTIMA: an architectural-level power estimator for multi-ported pipelined register files","authors":"Kavel M. Büyüksahin, Priyadarsan Patra, F. Najm","doi":"10.1145/871506.871579","DOIUrl":"https://doi.org/10.1145/871506.871579","url":null,"abstract":"We introduce an architectural-level power, area, and latency estimator for multi-ported, pipelined register files. Strengths of the proposed approach include the handling of pipelined operation and clock power, the simulation-based device size estimation, and the ability to handle user-specified timing constraints. The model proposed can be used as a standalone estimation and design exploration tool for register files and register-file type structures, or it can be incorporated into a high-level performance simulator to add power estimation capabilities.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126875862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Low power technology is impacting our society by creating the newly emerging digital consumer market, which leads to a nomadic lifestyle. In this paper, a historical review of the technologies is provided with some examples. It is suggested that robotics will provide the major challenge for low power electronics in the coming decades.
{"title":"Evolution of low power electronics and its future applications","authors":"T. Makimoto, Y. Sakai","doi":"10.1145/871506.871509","DOIUrl":"https://doi.org/10.1145/871506.871509","url":null,"abstract":"Low power technology is impacting our society by creating the newly emerging digital consumer market, which leads to a nomadic lifestyle. In this paper, a historical review of the technologies is provided with some examples. It is suggested that robotics will provide the major challenge for low power electronics in the coming decades.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125493456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, the many issues around the system and circuit design of advanced RF front ends for wireless RF applications will be discussed. After a short discussion on technology related issues, design choices linked to the different circuit/system solutions will be discussed.
{"title":"Low power RF IC design for wireless communication","authors":"D. Leenaerts","doi":"10.1145/871506.871612","DOIUrl":"https://doi.org/10.1145/871506.871612","url":null,"abstract":"In this paper, the many issues around the system and circuit design of advanced RF front ends for wireless RF applications will be discussed. After a short discussion on technology related issues, design choices linked to the different circuit/system solutions will be discussed.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116278339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Security is critical to a wide range of wireless data applications and services. While several security mechanisms and protocols have been developed in the context of the wired Internet, many new challenges arise due to the unique characteristics of battery powered embedded systems. In this work, we focus on an important constraint of such devices - battery life - and examine how it is impacted by the use of security protocols. We present a comprehensive analysis of the energy requirements of a wide range of cryptographic algorithms that are used as building blocks in security protocols. Furthermore, we study the energy consumption requirements of the most popular transport-layer security protocol SSL (Secure Sockets Layer). To our knowledge, this is the first comprehensive analysis of the energy requirements of SSL. For our studies, we have developed a measurement-based experimental testbed that consists of an iPAQ PDA connected to a wireless LAN and running Linux, a PC-based data acquisition system for real-time current measurement, the OpenSSL implementation of the SSL protocol, and parametrizable SSL client and server test programs. We investigate the impact of various parameters at protocol level (such as cipher suites, authentication mechanisms, transaction sizes, etc.) and cryptographic algorithm level (cipher modes, strength) on overall energy consumption for secure data transactions. Based on our results, we discuss various opportunities for realizing energy-efficient implementations of security protocols. We believe such investigations to be an important first step towards addressing the challenges of energy efficient security for battery-constrained systems.
{"title":"Analyzing the energy consumption of security protocols","authors":"N. R. Potlapally, S. Ravi, A. Raghunathan, N. Jha","doi":"10.1145/871506.871518","DOIUrl":"https://doi.org/10.1145/871506.871518","url":null,"abstract":"Security is critical to a wide range of wireless data applications and services. While several security mechanisms and protocols have been developed in the context of the wired Internet, many new challenges arise due to the unique characteristics of battery powered embedded systems. In this work, we focus on an important constraint of such devices - battery life - and examine how it is impacted by the use of security protocols. We present a comprehensive analysis of the energy requirements of a wide range of cryptographic algorithms that are used as building blocks in security protocols. Furthermore, we study the energy consumption requirements of the most popular transport-layer security protocol SSL (Secure Sockets Layer). To our knowledge, this is the first comprehensive analysis of the energy requirements of SSL. For our studies, we have developed a measurement-based experimental testbed that consists of an iPAQ PDA connected to a wireless LAN and running Linux, a PC-based data acquisition system for real-time current measurement, the OpenSSL implementation of the SSL protocol, and parametrizable SSL client and server test programs. We investigate the impact of various parameters at protocol level (such as cipher suites, authentication mechanisms, transaction sizes, etc.) and cryptographic algorithm level (cipher modes, strength) on overall energy consumption for secure data transactions. Based on our results, we discuss various opportunities for realizing energy-efficient implementations of security protocols. We believe such investigations to be an important first step towards addressing the challenges of energy efficient security for battery-constrained systems.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116931432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-08-25DOI: 10.1109/LPE.2003.1231859
Q. Khan, S. Wadhwa, K. Misri
A class of new startup circuits for voltage and current reference circuits is proposed. Unlike conventional startup circuits, the proposed circuits completely turn off once the reference circuit is started and consume no current during normal operation of the reference circuits. The circuits employ feedback from the reference circuit to ensure that the latter has reached its desired operating state prior to shutting themselves off. The proposed circuits are useful in low power integrated circuit design. Very low startup time can be achieved. The circuits are generic in nature and can be used with any reference circuit such as bandgap voltage references and /spl Delta/Vgs/R circuits.
{"title":"Low power startup circuits for voltage and current reference with zero steady state current","authors":"Q. Khan, S. Wadhwa, K. Misri","doi":"10.1109/LPE.2003.1231859","DOIUrl":"https://doi.org/10.1109/LPE.2003.1231859","url":null,"abstract":"A class of new startup circuits for voltage and current reference circuits is proposed. Unlike conventional startup circuits, the proposed circuits completely turn off once the reference circuit is started and consume no current during normal operation of the reference circuits. The circuits employ feedback from the reference circuit to ensure that the latter has reached its desired operating state prior to shutting themselves off. The proposed circuits are useful in low power integrated circuit design. Very low startup time can be achieved. The circuits are generic in nature and can be used with any reference circuit such as bandgap voltage references and /spl Delta/Vgs/R circuits.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"92 39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128901738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we present power models with clock and temperature scaling, and develop a first-of-its-type coupled thermal and power simulation with a temperature-dependent leakage power model at the microarchitecture level. We show that leakage energy and total energy can be different by up to 2.5/spl times/ and 2/spl times/ for temperatures between 90/spl deg/C and 130/spl deg/C, respectively. Given such big energy variations, no power model at the microarchitecture level is accurate without considering temperature dependent leakage models.
{"title":"Microarchitecture level power and thermal simulation considering temperature dependent leakage model","authors":"W. Liao, Fei Li, Lei He","doi":"10.1145/871506.871560","DOIUrl":"https://doi.org/10.1145/871506.871560","url":null,"abstract":"In this paper, we present power models with clock and temperature scaling, and develop a first-of-its-type coupled thermal and power simulation with a temperature-dependent leakage power model at the microarchitecture level. We show that leakage energy and total energy can be different by up to 2.5/spl times/ and 2/spl times/ for temperatures between 90/spl deg/C and 130/spl deg/C, respectively. Given such big energy variations, no power model at the microarchitecture level is accurate without considering temperature dependent leakage models.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127751677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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