Pub Date : 2003-08-25DOI: 10.1109/LPE.2003.1231890
R. Lotfi, M. Taherzadeh‐Sani, M. Azizi, O. Shoaei
In this paper a general method to design a pipelined ADC with minimum power consumption is presented. By expressing the total static power consumption and the total input-referred noise of the converter as functions of the capacitor values and the resolutions of the converter stages, a simple optimization algorithm is employed to calculate the optimum values of these parameters, which lead to minimum power consumption while a. specified noise requirement is satisfied. To determine the bias current values of operational amplifiers, a novel optimal choice for settling and slewing time parameters is proposed applicable to both single-stage and two-stage Miller-compensated opamp, structures. Using the proposed methodology, the optimum values for capacitors, the resolutions and the opamp device sizes of all stages are determined in order to minimize the total power consumption. Design examples are presented and compared with conventional approaches to show the effectiveness of the proposed methodology.
{"title":"A low-power design methodology for high-resolution pipelined analog-to-digital converters","authors":"R. Lotfi, M. Taherzadeh‐Sani, M. Azizi, O. Shoaei","doi":"10.1109/LPE.2003.1231890","DOIUrl":"https://doi.org/10.1109/LPE.2003.1231890","url":null,"abstract":"In this paper a general method to design a pipelined ADC with minimum power consumption is presented. By expressing the total static power consumption and the total input-referred noise of the converter as functions of the capacitor values and the resolutions of the converter stages, a simple optimization algorithm is employed to calculate the optimum values of these parameters, which lead to minimum power consumption while a. specified noise requirement is satisfied. To determine the bias current values of operational amplifiers, a novel optimal choice for settling and slewing time parameters is proposed applicable to both single-stage and two-stage Miller-compensated opamp, structures. Using the proposed methodology, the optimum values for capacitors, the resolutions and the opamp device sizes of all stages are determined in order to minimize the total power consumption. Design examples are presented and compared with conventional approaches to show the effectiveness of the proposed methodology.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126179993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
While circuit and package designers have addressed microprocessor inductive noise issues in the past, multi-gigahertz clock frequencies and billion-transistor-level integration are exacerbating the problem, necessitating microarchitectural solutions. The large net on-die decoupling capacitance used to address this noise throughout the chip consumes substantial area and can cause a large leakage current. This paper proposes microarchitectural techniques to reduce high-frequency current variability, reducing the need for decoupling capacitors. We observe that we can control inductive noise by reducing current variability either in space (i.e., variability in usage of circuit blocks) or in time (i.e., variability within a circuit block across clock cycles). We propose pipeline muffling, a novel technique to reduce changes in the number of resources being utilized by controlling instruction issue, trading off some energy and performance to control di/dt in space. We also extend a previous technique, which incurs performance and energy degradation, and propose a priori current ramping to allow the current of a resource to ramp up ahead of usage, with virtually no performance loss, and ramp down immediately after usage, with little energy loss. Our techniques guarantee a worst-case bound on the di/dt, which is required to reduce the demand for decoupling capacitors, saving area and reducing leakage.
{"title":"Pipeline muffling and a priori current ramping: architectural techniques to reduce high-frequency inductive noise","authors":"Michael D. Powell, T. N. Vijaykumar","doi":"10.1145/871506.871562","DOIUrl":"https://doi.org/10.1145/871506.871562","url":null,"abstract":"While circuit and package designers have addressed microprocessor inductive noise issues in the past, multi-gigahertz clock frequencies and billion-transistor-level integration are exacerbating the problem, necessitating microarchitectural solutions. The large net on-die decoupling capacitance used to address this noise throughout the chip consumes substantial area and can cause a large leakage current. This paper proposes microarchitectural techniques to reduce high-frequency current variability, reducing the need for decoupling capacitors. We observe that we can control inductive noise by reducing current variability either in space (i.e., variability in usage of circuit blocks) or in time (i.e., variability within a circuit block across clock cycles). We propose pipeline muffling, a novel technique to reduce changes in the number of resources being utilized by controlling instruction issue, trading off some energy and performance to control di/dt in space. We also extend a previous technique, which incurs performance and energy degradation, and propose a priori current ramping to allow the current of a resource to ramp up ahead of usage, with virtually no performance loss, and ramp down immediately after usage, with little energy loss. Our techniques guarantee a worst-case bound on the di/dt, which is required to reduce the demand for decoupling capacitors, saving area and reducing leakage.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128190835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We propose an integrated architectural/physical planning approach to reduce the power supply noise due to current surge in high performance, general-purpose, clock-gated microprocessors. The proposed approach combines dynamic selection of functional units on-the-fly, dynamic issue width scaling and physical planning with soft module, to balance the current demand across layout. Experimental results show that the proposed approach could reduce the peak noise by 6.54% and consequently, the decoupling capacitance requirement by 21.8%. The degradation in IPC (instruction Per Cycle) due to the selection logic and issue width scaling is only 1.86e-7 (without increasing clock cycle period) in 0.18 /spl mu/m technology.
{"title":"Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors","authors":"Yiran Chen, K. Roy, Cheng-Kok Koh","doi":"10.1145/871506.871563","DOIUrl":"https://doi.org/10.1145/871506.871563","url":null,"abstract":"We propose an integrated architectural/physical planning approach to reduce the power supply noise due to current surge in high performance, general-purpose, clock-gated microprocessors. The proposed approach combines dynamic selection of functional units on-the-fly, dynamic issue width scaling and physical planning with soft module, to balance the current demand across layout. Experimental results show that the proposed approach could reduce the peak noise by 6.54% and consequently, the decoupling capacitance requirement by 21.8%. The degradation in IPC (instruction Per Cycle) due to the selection logic and issue width scaling is only 1.86e-7 (without increasing clock cycle period) in 0.18 /spl mu/m technology.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127286879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Min, K. Kanda, H. Kawaguchi, K. Inagaki, F. R. Saliba, Hoon-Dae Choi, Hyunjun Choi, D. Kim, D. M. Kim, T. Sakurai
A new row-by-row dynamic source-line voltage control (RRDSV) scheme is proposed to reduce the active leakage as well as the stand-by leakage in SRAM. By dynamically controlling the source-line voltage of cells row by row, the cell leakage through inactive cells can be reduced by two orders of magnitude. Moreover, the bit-line leakage through pass transistors can be completely cut off. This leakage reduction is caused from the cooperation of reverse body-to-source biasing and drain induced barrier lowering (DIBL) effects. A test chip has been fabricated using 0.18-/spl mu/m triple-well CMOS technology to verify the data retention capability of this RRDSV scheme. The minimum retention voltage in the RRDSV is measured to be reduced by more than 60 mV, when shielding metal is inserted to protect the memory cell nodes from bit-line coupling noise. It can reduce the leakage by another 50% in addition to the reduction by two orders of magnitude.
{"title":"Row-by-row dynamic source-line voltage control (RRDSV) scheme for two orders of magnitude leakage current reduction of sub-1-V-V/sub DD/ SRAM's","authors":"K. Min, K. Kanda, H. Kawaguchi, K. Inagaki, F. R. Saliba, Hoon-Dae Choi, Hyunjun Choi, D. Kim, D. M. Kim, T. Sakurai","doi":"10.1145/871506.871526","DOIUrl":"https://doi.org/10.1145/871506.871526","url":null,"abstract":"A new row-by-row dynamic source-line voltage control (RRDSV) scheme is proposed to reduce the active leakage as well as the stand-by leakage in SRAM. By dynamically controlling the source-line voltage of cells row by row, the cell leakage through inactive cells can be reduced by two orders of magnitude. Moreover, the bit-line leakage through pass transistors can be completely cut off. This leakage reduction is caused from the cooperation of reverse body-to-source biasing and drain induced barrier lowering (DIBL) effects. A test chip has been fabricated using 0.18-/spl mu/m triple-well CMOS technology to verify the data retention capability of this RRDSV scheme. The minimum retention voltage in the RRDSV is measured to be reduced by more than 60 mV, when shielding metal is inserted to protect the memory cell nodes from bit-line coupling noise. It can reduce the leakage by another 50% in addition to the reduction by two orders of magnitude.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130535438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-08-25DOI: 10.1109/LPE.2003.1231855
K. Das, R. Joshi, C. Chuang, P. Cook, Richard B. Brown
This paper proposes new SOI circuit strategies for simultaneous reduction of standby gate and sub-threshold leakages. Various enhanced MTCMOS design alternatives are analyzed. A new method for assigning the V/sub TH/ and sizes of header and footer transistors is proposed, and stacking of headers/footers is analyzed. The optimum stacking height and tapering/sizing ratio under various design constraints are determined. Our strategies reduce MTCMOS standby leakage further by as much as 20/spl times/ and reduce virtual supply noise by 15%.
{"title":"New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology","authors":"K. Das, R. Joshi, C. Chuang, P. Cook, Richard B. Brown","doi":"10.1109/LPE.2003.1231855","DOIUrl":"https://doi.org/10.1109/LPE.2003.1231855","url":null,"abstract":"This paper proposes new SOI circuit strategies for simultaneous reduction of standby gate and sub-threshold leakages. Various enhanced MTCMOS design alternatives are analyzed. A new method for assigning the V/sub TH/ and sizes of header and footer transistors is proposed, and stacking of headers/footers is analyzed. The optimum stacking height and tapering/sizing ratio under various design constraints are determined. Our strategies reduce MTCMOS standby leakage further by as much as 20/spl times/ and reduce virtual supply noise by 15%.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122763065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
High-performance processors use a large set-associative L1 data cache with multiple ports. As clock speeds and size increase such a cache consumes a significant percentage of the total processor energy. This paper proposes a method of saving energy by reducing the number of data cache accesses. It does so by modifying the load/store queue design to allow "caching" of previously accessed data values on both loads and stores after the corresponding memory access instruction has been committed. It is shown that a 32 entry modified LSQ design allows an average of 38.5% of the loads in the SpecINT95 benchmarks and 18.9% in the SpecFP95 benchmarks to get their data from the LSQ. The reduction in the number of Ll cache accesses results in up to a 40% reduction in the L1 data cache energy consumption and in an up to a 16% improvement in the energy-delay product while requiring almost no additional hardware or complex control logic.
{"title":"Reducing data cache energy consumption via cached load/store queue","authors":"D. Nicolaescu, A. Veidenbaum, A. Nicolau","doi":"10.1145/871506.871569","DOIUrl":"https://doi.org/10.1145/871506.871569","url":null,"abstract":"High-performance processors use a large set-associative L1 data cache with multiple ports. As clock speeds and size increase such a cache consumes a significant percentage of the total processor energy. This paper proposes a method of saving energy by reducing the number of data cache accesses. It does so by modifying the load/store queue design to allow \"caching\" of previously accessed data values on both loads and stores after the corresponding memory access instruction has been committed. It is shown that a 32 entry modified LSQ design allows an average of 38.5% of the loads in the SpecINT95 benchmarks and 18.9% in the SpecFP95 benchmarks to get their data from the LSQ. The reduction in the number of Ll cache accesses results in up to a 40% reduction in the L1 data cache energy consumption and in an up to a 16% improvement in the energy-delay product while requiring almost no additional hardware or complex control logic.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123087265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-08-25DOI: 10.1109/LPE.2003.1231912
Quoc-Hoang Duong, Trung‐Kien Nguyen, Sang-Gug Lee
A CMOS voltage-to-current converter with exponential characteristic is presented in this paper. The concept of Taylor series expansion is used for realizing the exponential characteristic. The proposed exponential V-I converter is composed of a current-to-current squarer and a linear V-I converter with the use of linearization technique. Based on a 0.25 /spl mu/m CMOS process, simulations show a 23 dB of linear-output current range and the linearity within 20 dB with error less than /spl plusmn/0.5dB is achieved. The total power consumption is below 0.2 mW with 1.25 V supply voltage. The proposed circuit can be used for the design of an extremely low-voltage low-power variable gain amplifier (VGA).
{"title":"Low-voltage low-power high dB-Linear CMOS exponential function generator using highly-linear V-I converter","authors":"Quoc-Hoang Duong, Trung‐Kien Nguyen, Sang-Gug Lee","doi":"10.1109/LPE.2003.1231912","DOIUrl":"https://doi.org/10.1109/LPE.2003.1231912","url":null,"abstract":"A CMOS voltage-to-current converter with exponential characteristic is presented in this paper. The concept of Taylor series expansion is used for realizing the exponential characteristic. The proposed exponential V-I converter is composed of a current-to-current squarer and a linear V-I converter with the use of linearization technique. Based on a 0.25 /spl mu/m CMOS process, simulations show a 23 dB of linear-output current range and the linearity within 20 dB with error less than /spl plusmn/0.5dB is achieved. The total power consumption is below 0.2 mW with 1.25 V supply voltage. The proposed circuit can be used for the design of an extremely low-voltage low-power variable gain amplifier (VGA).","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116062546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Soontae Kim, N. Vijaykrishnan, M. J. Irwin, L. John
Many of the recently proposed techniques to reduce power consumption in caches introduce an additional level of nondeterminism in cache access latency. Due to this additional latency, instructions speculatively issued and dependent on a non-deterministic load must be re-executed. Our experiments show that there is a large performance degradation and associated energy wastage due to these effects of instruction re-execution. To address this problem, we propose an early cache set resolution scheme. It is based on the observation that the displacement values used for address generation are generally small. Our experimental evaluation shows that this technique is quite effective in mitigating this problem.
{"title":"On load latency in low-power caches","authors":"Soontae Kim, N. Vijaykrishnan, M. J. Irwin, L. John","doi":"10.1145/871506.871570","DOIUrl":"https://doi.org/10.1145/871506.871570","url":null,"abstract":"Many of the recently proposed techniques to reduce power consumption in caches introduce an additional level of nondeterminism in cache access latency. Due to this additional latency, instructions speculatively issued and dependent on a non-deterministic load must be re-executed. Our experiments show that there is a large performance degradation and associated energy wastage due to these effects of instruction re-execution. To address this problem, we propose an early cache set resolution scheme. It is based on the observation that the displacement values used for address generation are generally small. Our experimental evaluation shows that this technique is quite effective in mitigating this problem.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"358 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122814072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estimator closely reflects both dynamic and static power contributed by various FPGA components in 0.1 /spl mu/m technology. The power estimation error is 16.2% on average. Second, we present a low power high level synthesis system, named LOPASS, for FPGA designs. It includes two algorithms for power consumption reduction: (i) a simulated annealing engine that carries out resource selection function unit binding, scheduling, register binding, and data pat. generation simultaneously to effectively reduce power; (ii) an enhanced weighted bipartite matching algorithm that is able to reduce the total amount of MUX ports by 22.7%. Experimental results show that LOPASS is able to reduce-power consumption by 35.8% compared to the results-of -Synopsys' Behavioral Compiler.
{"title":"Low-power high-level synthesis for FPGA architectures","authors":"Deming Chen, J. Cong, Yiping Fan","doi":"10.1145/871506.871541","DOIUrl":"https://doi.org/10.1145/871506.871541","url":null,"abstract":"This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estimator closely reflects both dynamic and static power contributed by various FPGA components in 0.1 /spl mu/m technology. The power estimation error is 16.2% on average. Second, we present a low power high level synthesis system, named LOPASS, for FPGA designs. It includes two algorithms for power consumption reduction: (i) a simulated annealing engine that carries out resource selection function unit binding, scheduling, register binding, and data pat. generation simultaneously to effectively reduce power; (ii) an enhanced weighted bipartite matching algorithm that is able to reduce the total amount of MUX ports by 22.7%. Experimental results show that LOPASS is able to reduce-power consumption by 35.8% compared to the results-of -Synopsys' Behavioral Compiler.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131176349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Several techniques have been proposed to enhance the energy-efficiency of ASIPs (Application-Specific Instruction set Processors). While those techniques can reduce the energy consumption with a minimal change in the instruction set (IS), they fail to exploit the opportunity of designing the entire IS from the energy-efficiency perspective. In this paper, we present an energy-efficient IS synthesis technique that can comprehensively reduce the energy-delay product (EDP) of ASIPs through optimal instruction encoding, considering both the instruction bitwidth and the dynamic instruction count. Experimental results with a typical embedded RISC processor show that our technique can generate application-specific IS's that are up to 40% more energy-efficient over the native IS for several application benchmarks.
已经提出了几种技术来提高专用指令集处理器(Application-Specific Instruction set processor, asip)的能效。虽然这些技术可以通过对指令集(IS)进行最小的更改来降低能耗，但它们无法利用从能效角度设计整个IS的机会。在本文中，我们提出了一种节能的IS合成技术，该技术可以在考虑指令位宽和动态指令数的情况下，通过优化指令编码，全面降低asip的能量延迟积(EDP)。在典型嵌入式RISC处理器上的实验结果表明，我们的技术可以生成特定应用的IS，在几个应用基准测试中，比本地IS节能高达40%。
{"title":"Energy-efficient instruction set synthesis for application-specific processors","authors":"Jongeun Lee, Kiyoung Choi, N. Dutt","doi":"10.1145/871506.871588","DOIUrl":"https://doi.org/10.1145/871506.871588","url":null,"abstract":"Several techniques have been proposed to enhance the energy-efficiency of ASIPs (Application-Specific Instruction set Processors). While those techniques can reduce the energy consumption with a minimal change in the instruction set (IS), they fail to exploit the opportunity of designing the entire IS from the energy-efficiency perspective. In this paper, we present an energy-efficient IS synthesis technique that can comprehensively reduce the energy-delay product (EDP) of ASIPs through optimal instruction encoding, considering both the instruction bitwidth and the dynamic instruction count. Experimental results with a typical embedded RISC processor show that our technique can generate application-specific IS's that are up to 40% more energy-efficient over the native IS for several application benchmarks.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115332409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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