Pub Date : 2003-08-25DOI: 10.1109/LPE.2003.1231833
Ravishankar Rao, S. Vrudhula, Daler N. Rakhmatov
We consider the problem of scheduling multiple identical batteries for discharge in portable electronic systems. Unlike previous work reporting some experimental data to suggest which scheduling schemes are better than others, we arrive at our general conclusions formally, based on the analysis of an accurate high-level model of battery behavior. Our analytical results show that: (1) the lifetime of a parallel discharge schedule is equal to that of an equivalent monolithic battery, (2) the lifetime of a parallel discharge-schedule is no less than that of a sequential discharge schedule, and (3) the lifetime of a switched discharge schedule approaches that of an equivalent monolithic battery as the switching frequency increases. We also derive bounds on the lifetime of a single battery under a constant-rate load, and then extend them to multiple battery systems. Using a low-level battery simulator, we verify our analytical findings with numerical data. For the simulated cases, the parallel discharge schedule resulted in up to 72% higher lifetimes than the sequential discharge schedule but fell short of the lifetime tipper bound by up to 29%.
{"title":"Analysis of discharge techniques for multiple battery systems","authors":"Ravishankar Rao, S. Vrudhula, Daler N. Rakhmatov","doi":"10.1109/LPE.2003.1231833","DOIUrl":"https://doi.org/10.1109/LPE.2003.1231833","url":null,"abstract":"We consider the problem of scheduling multiple identical batteries for discharge in portable electronic systems. Unlike previous work reporting some experimental data to suggest which scheduling schemes are better than others, we arrive at our general conclusions formally, based on the analysis of an accurate high-level model of battery behavior. Our analytical results show that: (1) the lifetime of a parallel discharge schedule is equal to that of an equivalent monolithic battery, (2) the lifetime of a parallel discharge-schedule is no less than that of a sequential discharge schedule, and (3) the lifetime of a switched discharge schedule approaches that of an equivalent monolithic battery as the switching frequency increases. We also derive bounds on the lifetime of a single battery under a constant-rate load, and then extend them to multiple battery systems. Using a low-level battery simulator, we verify our analytical findings with numerical data. For the simulated cases, the parallel discharge schedule resulted in up to 72% higher lifetimes than the sequential discharge schedule but fell short of the lifetime tipper bound by up to 29%.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114372252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Recent mobile processors are required to exhibit both low-energy consumption and high performance. To satisfy these requirements, dynamic voltage scaling (DVS) is currently employed. However, its effectiveness will be limited in the future because of shrinking the variable supply voltage range. As an alternative, we previously proposed pipeline stage unification (PSU), which unifies multiple pipeline stages without reducing the supply voltage at a power-saving mode. This paper compares effectiveness of PSU to DVS in current and future process generations. Our evaluation results show PSU will reduce energy consumption by 27-34% more than DVS after about 10 years.
{"title":"Pipeline stage unification: a low-energy consumption technique for future mobile processors","authors":"Hajime Shimada, H. Ando, T. Shimada","doi":"10.1145/871506.871587","DOIUrl":"https://doi.org/10.1145/871506.871587","url":null,"abstract":"Recent mobile processors are required to exhibit both low-energy consumption and high performance. To satisfy these requirements, dynamic voltage scaling (DVS) is currently employed. However, its effectiveness will be limited in the future because of shrinking the variable supply voltage range. As an alternative, we previously proposed pipeline stage unification (PSU), which unifies multiple pipeline stages without reducing the supply voltage at a power-saving mode. This paper compares effectiveness of PSU to DVS in current and future process generations. Our evaluation results show PSU will reduce energy consumption by 27-34% more than DVS after about 10 years.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128642331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Memory systems consume a significant portion of power in hand-held embedded systems. So far, low-power memory techniques have addressed the power consumption when the system is turned on. In this paper, we consider data retention energy during the power-off period. For this purpose, we first characterize the data retention energy and cycle-accurate active mode energy. of the non-volatile memory systems. Next, we present energy-aware memory allocation for a given task set taking into account arrival rate, execution time, code size, user data size and the number of memory transactions by the use of trace-driven simulation. Experiments demonstrate that our optimal configuration can save up to 26% of the memory system energy compared traditional allocation schemes.
{"title":"Energy-aware memory allocation in heterogeneous non-volatile memory systems","authors":"H. Lee, N. Chang","doi":"10.1145/871506.871609","DOIUrl":"https://doi.org/10.1145/871506.871609","url":null,"abstract":"Memory systems consume a significant portion of power in hand-held embedded systems. So far, low-power memory techniques have addressed the power consumption when the system is turned on. In this paper, we consider data retention energy during the power-off period. For this purpose, we first characterize the data retention energy and cycle-accurate active mode energy. of the non-volatile memory systems. Next, we present energy-aware memory allocation for a given task set taking into account arrival rate, execution time, code size, user data size and the number of memory transactions by the use of trace-driven simulation. Experiments demonstrate that our optimal configuration can save up to 26% of the memory system energy compared traditional allocation schemes.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128921663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Gate leakage current is expected to be the dominant leakage component in future technology generations. In this paper, we propose methods for steady-state gate leakage estimation based on state characterization. An efficient technique for pattern-dependent gate leakage estimation is presented. Furthermore, we propose the use of this technique for estimating the average gate leakage of a circuit using pattern-independent probabilistic analysis. Results on a large set of benchmark ISCAS circuits show an accuracy within 5% of SPICE results with 500/spl times/ to 50000/spl times/ speed improvement.
{"title":"Efficient techniques for gate leakage estimation","authors":"R. Rao, J. Burns, A. Devgan, Richard B. Brown","doi":"10.1145/871506.871533","DOIUrl":"https://doi.org/10.1145/871506.871533","url":null,"abstract":"Gate leakage current is expected to be the dominant leakage component in future technology generations. In this paper, we propose methods for steady-state gate leakage estimation based on state characterization. An efficient technique for pattern-dependent gate leakage estimation is presented. Furthermore, we propose the use of this technique for estimating the average gate leakage of a circuit using pattern-independent probabilistic analysis. Results on a large set of benchmark ISCAS circuits show an accuracy within 5% of SPICE results with 500/spl times/ to 50000/spl times/ speed improvement.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"29 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127474192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-08-25DOI: 10.1109/LPE.2003.1231931
N. Kim, T. Mudge
The access time, energy and area of the register file are often critical to overall performance in wide-issue microprocessors, because these terms grow superlinearly with the number of read and write ports that are required to support wide-issue. This paper presents two techniques to reduce the number of ports of a register file intended for a wide-issue microprocessor with hardly any impact on IPC. Our results show that it is possible to replace a register file with 16 read and 8 write ports, intended for an eight-issue processor, with a register file with just 8 read and 8 write ports so that the impact on IPC is a few percent. This is accomplished with the addition of several small auxiliary memory structures, a 'delayed write-back queue' and an 'operand prefetch buffer.' We examine several configurations employing these structures separately and in combination. In the case of just the delayed write-back queue, we show an energy per access savings of about 40% and an area savings of 40% . This incurs a performance loss of just 4%. The area savings in turn has the potential for further savings by shortening global interconnect in the layout. We also show that the performance loss can be almost eliminated if both techniques are used in combination, although some area and power savings is lost.
{"title":"The microarchitecture of a low power register file","authors":"N. Kim, T. Mudge","doi":"10.1109/LPE.2003.1231931","DOIUrl":"https://doi.org/10.1109/LPE.2003.1231931","url":null,"abstract":"The access time, energy and area of the register file are often critical to overall performance in wide-issue microprocessors, because these terms grow superlinearly with the number of read and write ports that are required to support wide-issue. This paper presents two techniques to reduce the number of ports of a register file intended for a wide-issue microprocessor with hardly any impact on IPC. Our results show that it is possible to replace a register file with 16 read and 8 write ports, intended for an eight-issue processor, with a register file with just 8 read and 8 write ports so that the impact on IPC is a few percent. This is accomplished with the addition of several small auxiliary memory structures, a 'delayed write-back queue' and an 'operand prefetch buffer.' We examine several configurations employing these structures separately and in combination. In the case of just the delayed write-back queue, we show an energy per access savings of about 40% and an area savings of 40% . This incurs a performance loss of just 4%. The area savings in turn has the potential for further savings by shortening global interconnect in the layout. We also show that the performance loss can be almost eliminated if both techniques are used in combination, although some area and power savings is lost.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116790503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Scaling devices while maintaining reasonable short channel immunity requires gate oxide thickness of less than 20 /spl Aring/ for CMOS devices beyond the 70 nm technology node. Low oxide thickness gives rise to considerable direct tunneling current (gate leakage). Power dissipation in large caches is dominated by the gate and sub-threshold leakage current. This paper proposes a novel cache that has high noise immunity with improved leakage power. For every bank of SRAM cells, this technique requires an extra diode in parallel with a gated-ground transistor connected between the source of NMOS transistors and ground in SRAM cells. The row decoder itself can be used to control the extra gated-ground transistor. Our simulation results on a 70 nm process (Berkeley Predictive Technology Model augmented with our gate leakage model) show 39.2% reduction in consumed energy (leakage plus dynamic) in L1 cache and 59.4% reduction in L2 cache energy with less than 2.5% impact on execution time. The technique is applicable to data and instruction caches as well as different levels of cache hierarchy such as the L1, L2, or L3 caches.
{"title":"A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime","authors":"A. Agarwal, K. Roy","doi":"10.1145/871506.871514","DOIUrl":"https://doi.org/10.1145/871506.871514","url":null,"abstract":"Scaling devices while maintaining reasonable short channel immunity requires gate oxide thickness of less than 20 /spl Aring/ for CMOS devices beyond the 70 nm technology node. Low oxide thickness gives rise to considerable direct tunneling current (gate leakage). Power dissipation in large caches is dominated by the gate and sub-threshold leakage current. This paper proposes a novel cache that has high noise immunity with improved leakage power. For every bank of SRAM cells, this technique requires an extra diode in parallel with a gated-ground transistor connected between the source of NMOS transistors and ground in SRAM cells. The row decoder itself can be used to control the extra gated-ground transistor. Our simulation results on a 70 nm process (Berkeley Predictive Technology Model augmented with our gate leakage model) show 39.2% reduction in consumed energy (leakage plus dynamic) in L1 cache and 59.4% reduction in L2 cache energy with less than 2.5% impact on execution time. The technique is applicable to data and instruction caches as well as different levels of cache hierarchy such as the L1, L2, or L3 caches.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131423761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present a DC-DC converter design for on-chip integration with a WCDMA power amplifier to provide supply voltage modulation and efficiency enhancement. It operates from a 3.3 V supply using 0.35 /spl mu/m 'high-breakdown' CMOS transistors available in IBM's SiGe BiCMOS 6H:P process. Five selectable output voltage levels are available ranging from 1.3 V to 3.3 V. The converter is optimized for operation at 88.7 MHz. Simulation results show an average efficiency of 78.8% over the power amplifier operating conditions and a peak enabled efficiency of 86%. CCM-DCM mode switching and transistor width switching are used to minimize losses at the different output voltage and current load levels.
{"title":"Integrated DC-DC converter design for improved WCDMA power amplifier efficiency in SiGe BiCMOS technology","authors":"D. Guckenberger, K. Kornegay","doi":"10.1145/871506.871617","DOIUrl":"https://doi.org/10.1145/871506.871617","url":null,"abstract":"We present a DC-DC converter design for on-chip integration with a WCDMA power amplifier to provide supply voltage modulation and efficiency enhancement. It operates from a 3.3 V supply using 0.35 /spl mu/m 'high-breakdown' CMOS transistors available in IBM's SiGe BiCMOS 6H:P process. Five selectable output voltage levels are available ranging from 1.3 V to 3.3 V. The converter is optimized for operation at 88.7 MHz. Simulation results show an average efficiency of 78.8% over the power amplifier operating conditions and a peak enabled efficiency of 86%. CCM-DCM mode switching and transistor width switching are used to minimize losses at the different output voltage and current load levels.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131701920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-08-25DOI: 10.1109/LPE.2003.1231862
Stephen Tang, S. Narendra, V. De
Measurements on a prototype chip, implemented in a 150 nm logic process technology, validate the theories for two sub-1V MOS reference current generator circuits and show that /spl sim/2/spl times/ reduction in current variation is achievable across extremes of both process and temperature.
在采用 150 纳米逻辑工艺技术实现的原型芯片上进行的测量验证了两个 1V 以下 MOS 基准电流发生器电路的理论，并表明在极端工艺和温度条件下，电流变化可减少 /spl sim/2/spl times/。
{"title":"Temperature and process invariant MOS-based reference current generation circuits for sub-1V operation","authors":"Stephen Tang, S. Narendra, V. De","doi":"10.1109/LPE.2003.1231862","DOIUrl":"https://doi.org/10.1109/LPE.2003.1231862","url":null,"abstract":"Measurements on a prototype chip, implemented in a 150 nm logic process technology, validate the theories for two sub-1V MOS reference current generator circuits and show that /spl sim/2/spl times/ reduction in current variation is achievable across extremes of both process and temperature.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133827001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. Acar, A. Devgan, R. Rao, Y. Liu, Haihua Su, S. Nassif, J. Burns
Leakage power is emerging as a new critical challenge in the design of high performance integrated circuits. Leakage is increasing dramatically with each technology generation and is expected to dominate system power. This paper describes a static (i.e input independent) technique for efficient and accurate leakage estimation. A probabilistic technique is presented to compute the average leakage of combinational circuits. The proposed technique gives accurate results with an average error of only 2% for the ISCAS benchmarks and accurately predict both subthreshold and gate leakage as well as the leakage sensitivities to process and environmental parameters.
{"title":"Leakage and leakage sensitivity computation for combinational circuits","authors":"E. Acar, A. Devgan, R. Rao, Y. Liu, Haihua Su, S. Nassif, J. Burns","doi":"10.1145/871506.871532","DOIUrl":"https://doi.org/10.1145/871506.871532","url":null,"abstract":"Leakage power is emerging as a new critical challenge in the design of high performance integrated circuits. Leakage is increasing dramatically with each technology generation and is expected to dominate system power. This paper describes a static (i.e input independent) technique for efficient and accurate leakage estimation. A probabilistic technique is presented to compute the average leakage of combinational circuits. The proposed technique gives accurate results with an average error of only 2% for the ISCAS benchmarks and accurately predict both subthreshold and gate leakage as well as the leakage sensitivities to process and environmental parameters.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128426024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-08-25DOI: 10.1109/LPE.2003.1231835
M. Cooke, H. Mahmoodi, K. Roy
A significant fraction of the total power in highly synchronous systems is dissipated over clock networks. Hence, low-power clocking schemes would be promising approaches for future designs. We propose four novel energy recovery flip-flops that enable energy recovery from the clock network, resulting in significant energy savings. The proposed flip-flops operate with a single-phase sinusoidal clock, which can be generated with high efficiency. Based on the simulation results using TSMC 0.25 /spl mu/m CMOS process technology, at a frequency of 200 MHz, the proposed flip-flops exhibit more than 80% delay reduction, power reduction of up to 46%, and area reduction of up to 77%, as compared to the conventional energy recovery flip-flop. We implemented 1024 proposed energy recovery flip-flops through an H-tree clock network driven by a resonant clock-generator that generates a sinusoidal clock. Results show a power reduction of 90% on the clock-tree and total power savings of up to 83% as compared to the same implementation using the conventional square-wave clocking scheme and flip-flops.
在高度同步的系统中，总功率的很大一部分是在时钟网络上耗散的。因此，低功耗时钟方案将是未来设计的有希望的方法。我们提出了四种新颖的能量恢复触发器，可以从时钟网络中恢复能量，从而显著节省能源。所提出的触发器采用单相正弦时钟工作，产生效率高。基于采用台积电0.25 /spl μ m CMOS工艺技术的仿真结果，在200 MHz频率下，与传统的能量回收触发器相比，所提出的触发器延迟降低80%以上，功耗降低46%，面积减少77%。我们通过一个h树时钟网络实现了1024个提议的能量恢复触发器，该网络由一个产生正弦时钟的谐振时钟发生器驱动。结果表明，与使用传统方波时钟方案和触发器的相同实现相比，时钟树的功耗降低了90%，总功耗节省高达83%。
{"title":"Energy recovery clocking scheme and flip-flops for ultra low-energy applications","authors":"M. Cooke, H. Mahmoodi, K. Roy","doi":"10.1109/LPE.2003.1231835","DOIUrl":"https://doi.org/10.1109/LPE.2003.1231835","url":null,"abstract":"A significant fraction of the total power in highly synchronous systems is dissipated over clock networks. Hence, low-power clocking schemes would be promising approaches for future designs. We propose four novel energy recovery flip-flops that enable energy recovery from the clock network, resulting in significant energy savings. The proposed flip-flops operate with a single-phase sinusoidal clock, which can be generated with high efficiency. Based on the simulation results using TSMC 0.25 /spl mu/m CMOS process technology, at a frequency of 200 MHz, the proposed flip-flops exhibit more than 80% delay reduction, power reduction of up to 46%, and area reduction of up to 77%, as compared to the conventional energy recovery flip-flop. We implemented 1024 proposed energy recovery flip-flops through an H-tree clock network driven by a resonant clock-generator that generates a sinusoidal clock. Results show a power reduction of 90% on the clock-tree and total power savings of up to 83% as compared to the same implementation using the conventional square-wave clocking scheme and flip-flops.","PeriodicalId":355883,"journal":{"name":"Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115483904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：