Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188663
S. Thirumaran, S. K. N. Devi, P. Deepika, A. Vasanthi
Chromatic Dispersion is one of the major (Linear) effect in Optic transmission System. Dispersion causes broadening of transmitted pulses that leads to Inter Symbol Interference (ISI). Dispersion effect can be compensated by using Phase Conjugation technique. Phase conjugators were used in mid-way of the system in the late 90's to demonstrate for the compensation of dispersion. In this paper analysis of phase conjugation in compensating dispersion in an optical transmission system with bitrate of 10gb/s and for a distance of 30,000kms. The required number and fashion of OPC to be used for effective dispersion compensation were analysed. Simulation results were obtained using OPTSIM software from Rsoft.
{"title":"Optical phase conjugation in long haul optical transmission","authors":"S. Thirumaran, S. K. N. Devi, P. Deepika, A. Vasanthi","doi":"10.1109/ICDCSYST.2012.6188663","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188663","url":null,"abstract":"Chromatic Dispersion is one of the major (Linear) effect in Optic transmission System. Dispersion causes broadening of transmitted pulses that leads to Inter Symbol Interference (ISI). Dispersion effect can be compensated by using Phase Conjugation technique. Phase conjugators were used in mid-way of the system in the late 90's to demonstrate for the compensation of dispersion. In this paper analysis of phase conjugation in compensating dispersion in an optical transmission system with bitrate of 10gb/s and for a distance of 30,000kms. The required number and fashion of OPC to be used for effective dispersion compensation were analysed. Simulation results were obtained using OPTSIM software from Rsoft.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"2014 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133803916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188696
Vivitha Vijay, I. Jacob
The availability of large quantities of user contributed images with labels has provided opportunities to develop automatic tools to tag images to facilitate image search and retrieval. This paper discusses about an approach for automatic annotation in digital images. Some of the previous models for automatic image annotations are translation model (TM), continuous-space relevance model (CRM) and multiple Bernoulli relevance model (MBRM).These models have some semantic gap problems. To avoid these problems here developed a hybrid probabilistic model (HPM) which is used to combine both low-level image features and user provided tags to automatically tag images. For images without any tags, HPM predicts new tags based on the low-level image features. Low-level features are color, texture and shape. For images with user provided tags, HPM use both the image features and the tags to recommend additional tags to label the images. Here a Colored Pattern Appearance Model (CPAM) is used to capture both color and texture information. An L1 norm kernel method is used to estimate the correlations between image features and semantic concepts. The kernel density estimation is accelerated by an Improved Fast Gauss transform(IFGT).When the number of images becomes larger then Tag-Image Association Matrix (TIAM) used in the HPM framework become very sparse, thus it is very difficult to estimate tag-to-tag co-occurrence probabilities. So a collaborative filtering method based on nonnegative matrix factorization (NMF) is used for tackling this data sparsity issue. Here a CF algorithm is used to find the correlation between the words. Building such a HPM will make image labelling more efficient and less labour intensive.
{"title":"Combined approach of user specified tags and content-based image annotation","authors":"Vivitha Vijay, I. Jacob","doi":"10.1109/ICDCSYST.2012.6188696","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188696","url":null,"abstract":"The availability of large quantities of user contributed images with labels has provided opportunities to develop automatic tools to tag images to facilitate image search and retrieval. This paper discusses about an approach for automatic annotation in digital images. Some of the previous models for automatic image annotations are translation model (TM), continuous-space relevance model (CRM) and multiple Bernoulli relevance model (MBRM).These models have some semantic gap problems. To avoid these problems here developed a hybrid probabilistic model (HPM) which is used to combine both low-level image features and user provided tags to automatically tag images. For images without any tags, HPM predicts new tags based on the low-level image features. Low-level features are color, texture and shape. For images with user provided tags, HPM use both the image features and the tags to recommend additional tags to label the images. Here a Colored Pattern Appearance Model (CPAM) is used to capture both color and texture information. An L1 norm kernel method is used to estimate the correlations between image features and semantic concepts. The kernel density estimation is accelerated by an Improved Fast Gauss transform(IFGT).When the number of images becomes larger then Tag-Image Association Matrix (TIAM) used in the HPM framework become very sparse, thus it is very difficult to estimate tag-to-tag co-occurrence probabilities. So a collaborative filtering method based on nonnegative matrix factorization (NMF) is used for tackling this data sparsity issue. Here a CF algorithm is used to find the correlation between the words. Building such a HPM will make image labelling more efficient and less labour intensive.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114767591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188767
R. Gokulakrishnan, V. Bhaskar
In a high-capacity mobile radio system, reduction of Adjacent Chennel Interference (ACI) can be the most important advantage. Very recent researches showed that ACI can seriously degrade the overall capacity. Here, we consider a Nakagami fading channel and the impact of ACI on Spectral Efficiency. The Probability Density Function (PDF) of Singal-to-Interference Ratio (SIR) for Single Input Single Output (SISO) model are derived. It is then applied to different adaptation policies like Optimal Power and Rate Adaptation (OPRA), Optimal Rate Adaptation (ORA) policies and spectral efficiency (capacity per unit bandwidth) will be derived for each of them. These results are then compared and the impact of ACI on the system is studied.
{"title":"Spectrum efficiency of Nakagami-m fading channels for SISO system in the presence of Adjacent Channel Interference for various adaptation policies","authors":"R. Gokulakrishnan, V. Bhaskar","doi":"10.1109/ICDCSYST.2012.6188767","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188767","url":null,"abstract":"In a high-capacity mobile radio system, reduction of Adjacent Chennel Interference (ACI) can be the most important advantage. Very recent researches showed that ACI can seriously degrade the overall capacity. Here, we consider a Nakagami fading channel and the impact of ACI on Spectral Efficiency. The Probability Density Function (PDF) of Singal-to-Interference Ratio (SIR) for Single Input Single Output (SISO) model are derived. It is then applied to different adaptation policies like Optimal Power and Rate Adaptation (OPRA), Optimal Rate Adaptation (ORA) policies and spectral efficiency (capacity per unit bandwidth) will be derived for each of them. These results are then compared and the impact of ACI on the system is studied.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115098618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188640
A. Acharyya, J. Banerjee
In this paper the authors have proposed a lateral double drift region (DDR) IMPATT structure which can be fabricated in standard complementary metal semiconductor oxide (CMOS) technology. Possible fabrication steps of p+pnn+ structured lateral IMPATT designed to operate at 94 GHz window frequency are described in standard 0.18 μm CMOS technology. A double-iterative computer method based on drift-diffusion model is used to study the high frequency properties of the designed lateral IMPATT device. The proposed structure provides better feasibility of optical control of RF performance of the device.
{"title":"A proposed lateral DDR IMPATT structure for better millimeter-wave optical interaction","authors":"A. Acharyya, J. Banerjee","doi":"10.1109/ICDCSYST.2012.6188640","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188640","url":null,"abstract":"In this paper the authors have proposed a lateral double drift region (DDR) IMPATT structure which can be fabricated in standard complementary metal semiconductor oxide (CMOS) technology. Possible fabrication steps of p+pnn+ structured lateral IMPATT designed to operate at 94 GHz window frequency are described in standard 0.18 μm CMOS technology. A double-iterative computer method based on drift-diffusion model is used to study the high frequency properties of the designed lateral IMPATT device. The proposed structure provides better feasibility of optical control of RF performance of the device.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116923405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188712
Nithya Thilak, R. Braun
Next generation wireless communication system may be near filed magnetic induction Communication (NFMIC) which has major application in Body Area Network (BAN). Communication takes place in and around the body is called BAN. This Paper describes the working principle, power equation, its significance and application in NFMIC. It is compared with the other short range wireless technology such as Bluetooth, WLAN, UWB, ZigBee and RFID inside a BAN. This provides information how NFMIC is going to be next generation wireless communication.
{"title":"Near field magnetic induction Communication in Body Area Network","authors":"Nithya Thilak, R. Braun","doi":"10.1109/ICDCSYST.2012.6188712","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188712","url":null,"abstract":"Next generation wireless communication system may be near filed magnetic induction Communication (NFMIC) which has major application in Body Area Network (BAN). Communication takes place in and around the body is called BAN. This Paper describes the working principle, power equation, its significance and application in NFMIC. It is compared with the other short range wireless technology such as Bluetooth, WLAN, UWB, ZigBee and RFID inside a BAN. This provides information how NFMIC is going to be next generation wireless communication.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117295205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188710
T. Ahmed, M. A. Khan, M. S. Islam
A two-dimensional (2D) analytical model is derived in this paper to predict the channel potential of MESFET. The model is based on two-dimensional analytical solution of Poisson's equation with suitable boundary conditions. The analytical result is obtained and verified for GaN MESFET. The result of analytical model is almost similar to the simulation result obtained by Comsol Multiphysics. The variation of channel potential with respect to gate to source voltage, drain to source voltage and channel length is also shown. This model can be used for further device characterization and optimization.
{"title":"Two-dimensional analytical potential distribution model for GaN MESFET","authors":"T. Ahmed, M. A. Khan, M. S. Islam","doi":"10.1109/ICDCSYST.2012.6188710","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188710","url":null,"abstract":"A two-dimensional (2D) analytical model is derived in this paper to predict the channel potential of MESFET. The model is based on two-dimensional analytical solution of Poisson's equation with suitable boundary conditions. The analytical result is obtained and verified for GaN MESFET. The result of analytical model is almost similar to the simulation result obtained by Comsol Multiphysics. The variation of channel potential with respect to gate to source voltage, drain to source voltage and channel length is also shown. This model can be used for further device characterization and optimization.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116268915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188744
A. Jain, B. Dash, A. K. Panda, M. Suresh
An architecture for a fast 32-bit floating point multiplier compliant with the single precision IEEE 754-2008 standard has been proposed in this paper. This design intends to make the multiplier faster by reducing the delay caused by the propagation of the carry by implementing adders having the least power delay constant. The implementation of the multiplier module has been done in a top down approach. The sub-modules have been written in Verilog HDL and then synthesized and simulated using the Xilinx ISE 12.1 targeted on the Spartan 3E FPGA.
本文提出了一种符合单精度IEEE 754-2008标准的32位快速浮点乘法器结构。本设计旨在通过实现具有最小功率延迟常数的加法器来减少由进位传播引起的延迟，从而使乘法器更快。乘数模块的实现采用了自顶向下的方法。子模块用Verilog HDL编写，然后使用针对Spartan 3E FPGA的Xilinx ISE 12.1进行合成和仿真。
{"title":"FPGA design of a fast 32-bit floating point multiplier unit","authors":"A. Jain, B. Dash, A. K. Panda, M. Suresh","doi":"10.1109/ICDCSYST.2012.6188744","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188744","url":null,"abstract":"An architecture for a fast 32-bit floating point multiplier compliant with the single precision IEEE 754-2008 standard has been proposed in this paper. This design intends to make the multiplier faster by reducing the delay caused by the propagation of the carry by implementing adders having the least power delay constant. The implementation of the multiplier module has been done in a top down approach. The sub-modules have been written in Verilog HDL and then synthesized and simulated using the Xilinx ISE 12.1 targeted on the Spartan 3E FPGA.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117233282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188660
J. C. Dutta, M. Hazarika
We develop a physico-chemical model of Enzyme Field effect transistor (ENFET) biosensor for glucose detection by considering some important criteria like biocatalytic reaction, diffusion phenomena and the surface charging of ion sensitive field effect transistor (ISFET). In general, in ENFET creation, though the enzyme is immobilized on the surface of the insulator of the FET device, here we have assumed that the immobilized enzyme molecules have formed an enzymatic layer that behaves as a membrane situated just near the outer Helmholtz plane (OHP). It is essential because the proton generated through enzyme catalyzed reaction must interact with the insulating surface in accordance with the site binding theory which is generally used for ISFET modeling. The concentration of glucose has been characterized by considering two kinds of binding sites in the sensing insulator layer, mainly silanol and basic primary amine sites and the pH dependent electrolyte-insulator potential according to Boltzmann distribution along with the diffusion phenomena of electrolyte substrate. The charges and potentials at the different interfaces are related in accordance with Gouy-Chapman-Stern theory.
{"title":"Modeling of Enzyme biosensor based on pH-sensitive field effect transistor for detection of glucose","authors":"J. C. Dutta, M. Hazarika","doi":"10.1109/ICDCSYST.2012.6188660","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188660","url":null,"abstract":"We develop a physico-chemical model of Enzyme Field effect transistor (ENFET) biosensor for glucose detection by considering some important criteria like biocatalytic reaction, diffusion phenomena and the surface charging of ion sensitive field effect transistor (ISFET). In general, in ENFET creation, though the enzyme is immobilized on the surface of the insulator of the FET device, here we have assumed that the immobilized enzyme molecules have formed an enzymatic layer that behaves as a membrane situated just near the outer Helmholtz plane (OHP). It is essential because the proton generated through enzyme catalyzed reaction must interact with the insulating surface in accordance with the site binding theory which is generally used for ISFET modeling. The concentration of glucose has been characterized by considering two kinds of binding sites in the sensing insulator layer, mainly silanol and basic primary amine sites and the pH dependent electrolyte-insulator potential according to Boltzmann distribution along with the diffusion phenomena of electrolyte substrate. The charges and potentials at the different interfaces are related in accordance with Gouy-Chapman-Stern theory.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128707059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188708
S. Remmanapudi, B. Bandaru
This paper presents implementation of Low Density Parity-Check (LDPC) Codes on FPGA Platform. LDPC codes has been implemented by writing Hardware Description Language (Verilog) code and targeted to a Xilinx Spartan-3E XC3S500E FPGA chip. Repeat-Accumulation LDPC codes are also constructed. Codewords have been constructed & simulated for different rates such as 1/2 rate, 1/3 rate, 1/4 rate. The iterative decoding algorithms such as Belief Propagation (BP) and Bit-Flipping has been implemented and desired simulation results were obtained using three different coding (C, Verilog-HDL, MATlab (Simulink)) styles. Synthesis has been done for LDPC codes Construction & Bit-flipping decoding using Leonardo-Spectrum and Xilinx-ISE Project Navigator. This code is useful for large and small length of block codes. So this is flexible to use for any length of code word (or) data word and also for any rate of code word. So the usage of this code leads to high performance. The above decoding algorithms can recover the original codeword in the face of large amounts of noise.
{"title":"An fpga implementation of Low Density Parity-Check CodeS construction & decoding","authors":"S. Remmanapudi, B. Bandaru","doi":"10.1109/ICDCSYST.2012.6188708","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188708","url":null,"abstract":"This paper presents implementation of Low Density Parity-Check (LDPC) Codes on FPGA Platform. LDPC codes has been implemented by writing Hardware Description Language (Verilog) code and targeted to a Xilinx Spartan-3E XC3S500E FPGA chip. Repeat-Accumulation LDPC codes are also constructed. Codewords have been constructed & simulated for different rates such as 1/2 rate, 1/3 rate, 1/4 rate. The iterative decoding algorithms such as Belief Propagation (BP) and Bit-Flipping has been implemented and desired simulation results were obtained using three different coding (C, Verilog-HDL, MATlab (Simulink)) styles. Synthesis has been done for LDPC codes Construction & Bit-flipping decoding using Leonardo-Spectrum and Xilinx-ISE Project Navigator. This code is useful for large and small length of block codes. So this is flexible to use for any length of code word (or) data word and also for any rate of code word. So the usage of this code leads to high performance. The above decoding algorithms can recover the original codeword in the face of large amounts of noise.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132146574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188641
J. Sathiyanarayanan, A. S. Kumar
Many wearable and portable devices, like personal communicators, cellular phones, laptops, are equipped with two or more battery packs to increase user flexibility in selecting the optimal form-factor/weight versus required lifetime trade off. For instance, the Compaq IPAQ PDA is equipped with an add-on module that contains PCMCIA expansion and an auxiliary battery pack. Portable and wearable computers can be powered by different combinations of two or more battery packs to give the user the possibility of choosing an optimal compromise between lifetime and weight/size. Recent work on battery-driven power management has demonstrated that sequential discharge is suboptimal in multibattery systems and lifetime can be maximized by distributing (steering) the current load on the available batteries, thereby discharging them in a partially concurrent fashion. Based on these observations, we formulate multibattery lifetime maximization as a continuous, constrained optimization problem, which can be efficiently solved by nonlinear optimizers. We show that significant lifetime extensions can be obtained with respect to standard sequential discharge (up to 160 percent), as well to previously proposed battery scheduling algorithms (up to 12 percent). From the manufacturing standpoint, numerous issues must be faced when multiple batteries have to be accommodated into the case of a portable electronic appliance. They range from the selection of battery capacities and shapes to the design of the power supply circuitry (including the switching regulator that interfaces the various batteries to the current load). One degree of freedom that, so far, has not been fully exploited, is the policy to be used for discharging the available batteries. The main contribution of this paper is the development of a new class battery lifetime maximization policies and an approach for optimally tuning the policies for a given battery system.
{"title":"Maximization battery lifetime and improving efficiency","authors":"J. Sathiyanarayanan, A. S. Kumar","doi":"10.1109/ICDCSYST.2012.6188641","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188641","url":null,"abstract":"Many wearable and portable devices, like personal communicators, cellular phones, laptops, are equipped with two or more battery packs to increase user flexibility in selecting the optimal form-factor/weight versus required lifetime trade off. For instance, the Compaq IPAQ PDA is equipped with an add-on module that contains PCMCIA expansion and an auxiliary battery pack. Portable and wearable computers can be powered by different combinations of two or more battery packs to give the user the possibility of choosing an optimal compromise between lifetime and weight/size. Recent work on battery-driven power management has demonstrated that sequential discharge is suboptimal in multibattery systems and lifetime can be maximized by distributing (steering) the current load on the available batteries, thereby discharging them in a partially concurrent fashion. Based on these observations, we formulate multibattery lifetime maximization as a continuous, constrained optimization problem, which can be efficiently solved by nonlinear optimizers. We show that significant lifetime extensions can be obtained with respect to standard sequential discharge (up to 160 percent), as well to previously proposed battery scheduling algorithms (up to 12 percent). From the manufacturing standpoint, numerous issues must be faced when multiple batteries have to be accommodated into the case of a portable electronic appliance. They range from the selection of battery capacities and shapes to the design of the power supply circuitry (including the switching regulator that interfaces the various batteries to the current load). One degree of freedom that, so far, has not been fully exploited, is the policy to be used for discharging the available batteries. The main contribution of this paper is the development of a new class battery lifetime maximization policies and an approach for optimally tuning the policies for a given battery system.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"159 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131010234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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