Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188654
R. Jayagowri, K. Gurumurthy
Power consumption of a circuit is more in test mode than normal mode. The increased heat due to excess power dissipation can open up reliability issue due to electro-migration. In extreme conditions excess power consumption might even result in chip burn outs also. In this paper, we propose a scan flip-flop which helps to reduce the power consumption during test mode without affecting the functional mode requirements. The proposed scan flip-flop use the single latch double edge triggered flip-flop to perform the scanning during test by halving of number of cycles in the clock frequency. The proposed design of clock driving circuit for the scan flip-flop helps to use the same flip-flop during the normal mode for the specified clock frequency. This avoids the redesign of the circuit for normal mode while using the high speed proposed scan flip-flop. The usage of the proposed scan flip-flop reduces the silicon area by 30% - 45% and the power dissipation by 25% - 35%.
{"title":"A technique for low power testing of VLSI chips","authors":"R. Jayagowri, K. Gurumurthy","doi":"10.1109/ICDCSYST.2012.6188654","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188654","url":null,"abstract":"Power consumption of a circuit is more in test mode than normal mode. The increased heat due to excess power dissipation can open up reliability issue due to electro-migration. In extreme conditions excess power consumption might even result in chip burn outs also. In this paper, we propose a scan flip-flop which helps to reduce the power consumption during test mode without affecting the functional mode requirements. The proposed scan flip-flop use the single latch double edge triggered flip-flop to perform the scanning during test by halving of number of cycles in the clock frequency. The proposed design of clock driving circuit for the scan flip-flop helps to use the same flip-flop during the normal mode for the specified clock frequency. This avoids the redesign of the circuit for normal mode while using the high speed proposed scan flip-flop. The usage of the proposed scan flip-flop reduces the silicon area by 30% - 45% and the power dissipation by 25% - 35%.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125516929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188732
S. A. Abbas, K. S. Geethu, S. Thiruvengadam
LTE is accepted worldwide as the Long Term Evolution Perspective for today's 3G and 4G networks. The downlink physical channels of LTE include 3 data channels (PDSCH, PMCH and PBCH) and 3 control channels (PDCCH, PCFICH and PHICH). Control channels are inevitable for the transmission of both downlink and uplink data channels. Control information for one or multiple user equipments are contained in Downlink Control Information (DCI) and transmitted through PDCCH. This paper deals with transmitter architecture for PDCCH comprising of Scrambling, Modulation, Layermapping, Precoding and Resource element mapping and receiver architecture comprising of Demapping from resource elements, Removal of parity bits, Decoding, Delayermapping, Demodulation and Descrambling as described in LTE specifications. Modelsim 6.4a is used for simulation and implementation done in Xilinx Spartan 3E kit.
{"title":"Implementation of physical downlink control channel (PDCCH) FOR LTE using FPGA","authors":"S. A. Abbas, K. S. Geethu, S. Thiruvengadam","doi":"10.1109/ICDCSYST.2012.6188732","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188732","url":null,"abstract":"LTE is accepted worldwide as the Long Term Evolution Perspective for today's 3G and 4G networks. The downlink physical channels of LTE include 3 data channels (PDSCH, PMCH and PBCH) and 3 control channels (PDCCH, PCFICH and PHICH). Control channels are inevitable for the transmission of both downlink and uplink data channels. Control information for one or multiple user equipments are contained in Downlink Control Information (DCI) and transmitted through PDCCH. This paper deals with transmitter architecture for PDCCH comprising of Scrambling, Modulation, Layermapping, Precoding and Resource element mapping and receiver architecture comprising of Demapping from resource elements, Removal of parity bits, Decoding, Delayermapping, Demodulation and Descrambling as described in LTE specifications. Modelsim 6.4a is used for simulation and implementation done in Xilinx Spartan 3E kit.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122173473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188788
S. Chiwande, P. Dakhole
This paper presents various designs of reversible logic gates used for reversible operation & one of the applications as Carry Skip Adder Block. When we say reversible computing, we mean performing computation in such a way that any previous state of the computation can always be reconstructed given a description of the current state. In recent years, reversible logic has emerged as a promising computing paradigm having application in low power CMOS, quantum computing, nanotechnology, and optical computing. The classical set of gates such as AND, OR, and EXOR are not reversible. This paper also includes simulation result of forward & backward computation of 4*4 reversible TSG & Fredkin gate. This gate is then used to design four bit Carry Skip Adder block. Methodology used for designing reversible gate is Tanner Tool Version-13 & technology file 0.35 micron. It is shown that the adder architecture designed using TSG & Fredkin gate are much better & optimized as compared to existing four bit Carry Skip Adder in terms of low power dissipation.
{"title":"VLSI design of power efficient Carry Skip Adder using TSG & Fredkin reversible gate","authors":"S. Chiwande, P. Dakhole","doi":"10.1109/ICDCSYST.2012.6188788","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188788","url":null,"abstract":"This paper presents various designs of reversible logic gates used for reversible operation & one of the applications as Carry Skip Adder Block. When we say reversible computing, we mean performing computation in such a way that any previous state of the computation can always be reconstructed given a description of the current state. In recent years, reversible logic has emerged as a promising computing paradigm having application in low power CMOS, quantum computing, nanotechnology, and optical computing. The classical set of gates such as AND, OR, and EXOR are not reversible. This paper also includes simulation result of forward & backward computation of 4*4 reversible TSG & Fredkin gate. This gate is then used to design four bit Carry Skip Adder block. Methodology used for designing reversible gate is Tanner Tool Version-13 & technology file 0.35 micron. It is shown that the adder architecture designed using TSG & Fredkin gate are much better & optimized as compared to existing four bit Carry Skip Adder in terms of low power dissipation.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121068453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188673
R. John, V. Bhaskar
This paper deals with the design of a new system where Rayleigh fading channel is subjected to a more generalized scenario by considering L-Independent block fading, where L= 2, 3, ... Each block undergoes different fading characteristics for a particular time interval such that the channel coefficient is fixed during a fading block, and statistically independent from one block to another. The main focus of this work is to derive performance measures, such as outage probability and average signal power. Once mathematical expressions are derived, attention is given to obtain numerical results by plotting analytical graphs for the obtained expressions, and is observed with the proposed system parameters like Signal to Noise Ratio (SNR), average channel power and data transmission rate. Hence, the proposed system can be evaluated and the amount of degradation can be measured.
{"title":"Performance measures of L-independent block fading rayleigh channel with perfect channel estimation for a SISO system","authors":"R. John, V. Bhaskar","doi":"10.1109/ICDCSYST.2012.6188673","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188673","url":null,"abstract":"This paper deals with the design of a new system where Rayleigh fading channel is subjected to a more generalized scenario by considering L-Independent block fading, where L= 2, 3, ... Each block undergoes different fading characteristics for a particular time interval such that the channel coefficient is fixed during a fading block, and statistically independent from one block to another. The main focus of this work is to derive performance measures, such as outage probability and average signal power. Once mathematical expressions are derived, attention is given to obtain numerical results by plotting analytical graphs for the obtained expressions, and is observed with the proposed system parameters like Signal to Noise Ratio (SNR), average channel power and data transmission rate. Hence, the proposed system can be evaluated and the amount of degradation can be measured.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"253 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121070230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188691
D. J. Judy, V. S. K. Bhaaskaran
Energy recovery is a technique developed for low power digital circuits. Energy recovery clocking is an effective method for reducing the clock power in which the conventional square wave clock signal is replaced by a trapezoidal clock. This modification in the clock signal prevents the application of existing clock gating solutions. In this paper, a clock gating solution for energy recovery clocking is proposed by gating the flip-flops. Further, all the existing energy recovery clocked flip-flops are positive edge triggered. But in a synchronous system, it is advantageous to have both positive and negative edge triggered flip-flops in the same system. There has not been a negative edge triggered energy recovery flip-flop in the literature so far. In this paper, we propose a design of negative edge triggered flip-flop with the clock gating feature. The proposed design is simulated using the industrial standard Austria micro systems 350nm process technology Tanner spice(T-spice) tool. The simulation results show that the design is as power efficient as the existing positive edge triggered energy recovery flip-flops and is well suited for low power applications.
{"title":"Energy recovery clock gating scheme and negative edge triggering flip-flop for low power applications","authors":"D. J. Judy, V. S. K. Bhaaskaran","doi":"10.1109/ICDCSYST.2012.6188691","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188691","url":null,"abstract":"Energy recovery is a technique developed for low power digital circuits. Energy recovery clocking is an effective method for reducing the clock power in which the conventional square wave clock signal is replaced by a trapezoidal clock. This modification in the clock signal prevents the application of existing clock gating solutions. In this paper, a clock gating solution for energy recovery clocking is proposed by gating the flip-flops. Further, all the existing energy recovery clocked flip-flops are positive edge triggered. But in a synchronous system, it is advantageous to have both positive and negative edge triggered flip-flops in the same system. There has not been a negative edge triggered energy recovery flip-flop in the literature so far. In this paper, we propose a design of negative edge triggered flip-flop with the clock gating feature. The proposed design is simulated using the industrial standard Austria micro systems 350nm process technology Tanner spice(T-spice) tool. The simulation results show that the design is as power efficient as the existing positive edge triggered energy recovery flip-flops and is well suited for low power applications.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131376420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188799
R. Shende, P. Zode
In this paper, a binary to residue number system architecture based on the 2k-1 modulo set. For the integer modulo operation (X mod m), (p, 2) compressors are used, where m is restricted to the values 2k-1, for any value of k >; 1 and X is a 16 bit number. The novel 3-2, 4-2 and 5-2 compressors are illustrated for efficient design, which are used as the basic building blocks for the proposed binary to residue converter designs. The 3-2, 4-2 and 5-2 compressors are used in place of half adder and full adder to reduce the delay, power consumption as well as the area of the circuit. The 4-2 and 5-2 compressors cell can operate reliably in any tree structured parallel multiplier at very low supply voltages. The proposed converter can be implemented by fast and simple architecture and also required less hardware.
{"title":"Efficient design 2k−1 binary to residue converter","authors":"R. Shende, P. Zode","doi":"10.1109/ICDCSYST.2012.6188799","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188799","url":null,"abstract":"In this paper, a binary to residue number system architecture based on the 2k-1 modulo set. For the integer modulo operation (X mod m), (p, 2) compressors are used, where m is restricted to the values 2k-1, for any value of k >; 1 and X is a 16 bit number. The novel 3-2, 4-2 and 5-2 compressors are illustrated for efficient design, which are used as the basic building blocks for the proposed binary to residue converter designs. The 3-2, 4-2 and 5-2 compressors are used in place of half adder and full adder to reduce the delay, power consumption as well as the area of the circuit. The 4-2 and 5-2 compressors cell can operate reliably in any tree structured parallel multiplier at very low supply voltages. The proposed converter can be implemented by fast and simple architecture and also required less hardware.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121836135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188698
A. Bhagat, M. Atique
The Digital Imaging and Communications in Medicine (DICOM) standard was created to aid the distribution and viewing of medical images, such as CT scans, MRIs, and ultrasound by the National Electrical Manufacturers Association (NEMA). This paper includes description of various image formats and image compression algorithms which will be helpful for researcher in the field of medical image processing. The comparison of described formats and compression techniques is also provided in this paper. DICOM is the most common standard for receiving scans from a hospital. The DICOM standard is an evolving standard and it is maintained in accordance with the procedures of the DICOM standards committee. The features, which are extracted from DICOM images, are included in this paper.
{"title":"Medical images: Formats, compression techniques and DICOM image retrieval a survey","authors":"A. Bhagat, M. Atique","doi":"10.1109/ICDCSYST.2012.6188698","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188698","url":null,"abstract":"The Digital Imaging and Communications in Medicine (DICOM) standard was created to aid the distribution and viewing of medical images, such as CT scans, MRIs, and ultrasound by the National Electrical Manufacturers Association (NEMA). This paper includes description of various image formats and image compression algorithms which will be helpful for researcher in the field of medical image processing. The comparison of described formats and compression techniques is also provided in this paper. DICOM is the most common standard for receiving scans from a hospital. The DICOM standard is an evolving standard and it is maintained in accordance with the procedures of the DICOM standards committee. The features, which are extracted from DICOM images, are included in this paper.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133917258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188733
S. Arivazhagan, R. Ahila Priyadharshini, S. Seedhanadevi
The proposed method is to recognize objects from different categories of images using Gabor features. In the domain of object recognition, it is often to classify objects from images that make only limited part of the image. Hence to identify local features and certain region of images, salient point detection and patch extraction are used. Gabor wavelet features such as Gabor mean and variance using 2 scales and 2 orientations and 2 scales and 4 orientations are computed for every patch that extracted over the salient points taken from the original image. These features provide adequate resolution in both spatial and spectral domains. Thus extracted features are trained in order to get a learning model, tested and classified using SVM. Finally, the results obtained using Gabor wavelet features using 2 scales and 2 orientations and 2 scales and 4 orientations are compared and thus observed that the latter performs better than the former with less error rate. The experimental evaluation of proposed method is done using the Caltech database.
{"title":"Object recognition based on gabor wavelet features","authors":"S. Arivazhagan, R. Ahila Priyadharshini, S. Seedhanadevi","doi":"10.1109/ICDCSYST.2012.6188733","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188733","url":null,"abstract":"The proposed method is to recognize objects from different categories of images using Gabor features. In the domain of object recognition, it is often to classify objects from images that make only limited part of the image. Hence to identify local features and certain region of images, salient point detection and patch extraction are used. Gabor wavelet features such as Gabor mean and variance using 2 scales and 2 orientations and 2 scales and 4 orientations are computed for every patch that extracted over the salient points taken from the original image. These features provide adequate resolution in both spatial and spectral domains. Thus extracted features are trained in order to get a learning model, tested and classified using SVM. Finally, the results obtained using Gabor wavelet features using 2 scales and 2 orientations and 2 scales and 4 orientations are compared and thus observed that the latter performs better than the former with less error rate. The experimental evaluation of proposed method is done using the Caltech database.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131904286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188715
D. Moni, P. Jisha
This paper presents the comparison between the CMOS dynamic latch comparators. High speed and low power comparators are essential building blocks of high speed analog to digital converters (ADCs). The comparator circuit take for study are dynamic latch comparator using preamplifier and dynamic latch with inverter buffer. Preamplifier dynamic latch circuit that consists of a preamplifier followed by a double regenerative dynamic latch, this preamplifier uses fully differential circuit which decreases the effects of offset voltage error due to device mismatch. Buffered dynamic latch circuit includes a basic dynamic latch comparator followed by an inverter buffer stage. The inverter buffers are added to isolate the comparator output and large node capacitance also used to minimize the offset errors. The circuit using SPICE tool with 0.18um technology and the supply voltage used 1.8V.
{"title":"High-speed and low-power dynamic latch comparator","authors":"D. Moni, P. Jisha","doi":"10.1109/ICDCSYST.2012.6188715","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188715","url":null,"abstract":"This paper presents the comparison between the CMOS dynamic latch comparators. High speed and low power comparators are essential building blocks of high speed analog to digital converters (ADCs). The comparator circuit take for study are dynamic latch comparator using preamplifier and dynamic latch with inverter buffer. Preamplifier dynamic latch circuit that consists of a preamplifier followed by a double regenerative dynamic latch, this preamplifier uses fully differential circuit which decreases the effects of offset voltage error due to device mismatch. Buffered dynamic latch circuit includes a basic dynamic latch comparator followed by an inverter buffer stage. The inverter buffers are added to isolate the comparator output and large node capacitance also used to minimize the offset errors. The circuit using SPICE tool with 0.18um technology and the supply voltage used 1.8V.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"342 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132339637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188758
G. Ignatius, K. Murali, N. Krishna, P. V. Sachin, P. Sudheesh
This paper presents an algorithm for performing effective channel estimation for multiple input multiple output (MIMO) orthogonal frequency division multiplexing (OFDM) systems when they encounter a fast fading environment. The algorithm models the parameters to be estimated using an auto-regressive model which is implemented using Burg Method. The channel estimation is performed using an Extended Kalman Filter (EKF). The effect of intercarrier interference (ICI) is removed by QR decomposing the channel matrix, which effectively leads to estimation of the data symbol. The channel is modeled as L-path parametric Rayleigh flat fading. The Rayleigh complex amplitudes (CA) and carrier frequency offset are jointly estimated for this channel.
{"title":"Extended Kalman Filter based estimation for fast fading MIMO channels","authors":"G. Ignatius, K. Murali, N. Krishna, P. V. Sachin, P. Sudheesh","doi":"10.1109/ICDCSYST.2012.6188758","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188758","url":null,"abstract":"This paper presents an algorithm for performing effective channel estimation for multiple input multiple output (MIMO) orthogonal frequency division multiplexing (OFDM) systems when they encounter a fast fading environment. The algorithm models the parameters to be estimated using an auto-regressive model which is implemented using Burg Method. The channel estimation is performed using an Extended Kalman Filter (EKF). The effect of intercarrier interference (ICI) is removed by QR decomposing the channel matrix, which effectively leads to estimation of the data symbol. The channel is modeled as L-path parametric Rayleigh flat fading. The Rayleigh complex amplitudes (CA) and carrier frequency offset are jointly estimated for this channel.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114744122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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