Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380945
F. Gianesello, S. Montusclat, B. Martineau, D. Gloria, C. Raynaud, S. Boret, G. Dambrine, S. Lépilliet, R. Pilard
Today, measurement of 65 nm CMOS and 130 nm-based SiGe HBTs technologies demonstrate both Ftau (current gain cut-off frequency) and Fmax (maximum oscillation frequency) higher than 200 GHz, which are clearly comparable to advanced commercially available 100 nm III-V HEMT. Consequently, the integration of full transceiver at 60 GHz has been achieved both in SiGe bipolar and CMOS technology. In the same time passive circuits working at 220 GHz have been achieved and characterized on high resistivity SOI demonstrating state-of-the-art performances and good agreement with electrical simulations using developed models. Moreover, HR SOI has also demonstrated some advantages concerning the performances of integrated antennas and a first fully integrated prototype with amplifier, filter and antenna has already been achieved using STMicroelectronics 130 nm CMOS HR SOI technology. This paper will review the MMW performances of STMicrolectronics 65 nm CMOS HR SOI technology from device up to circuit level and discuss the opportunities of MMW SoC integrated on CMOS HR SOI technology.
{"title":"65 nm HR SOI CMOS Technology: emergence of Millimeter-Wave SoC","authors":"F. Gianesello, S. Montusclat, B. Martineau, D. Gloria, C. Raynaud, S. Boret, G. Dambrine, S. Lépilliet, R. Pilard","doi":"10.1109/RFIC.2007.380945","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380945","url":null,"abstract":"Today, measurement of 65 nm CMOS and 130 nm-based SiGe HBTs technologies demonstrate both Ftau (current gain cut-off frequency) and Fmax (maximum oscillation frequency) higher than 200 GHz, which are clearly comparable to advanced commercially available 100 nm III-V HEMT. Consequently, the integration of full transceiver at 60 GHz has been achieved both in SiGe bipolar and CMOS technology. In the same time passive circuits working at 220 GHz have been achieved and characterized on high resistivity SOI demonstrating state-of-the-art performances and good agreement with electrical simulations using developed models. Moreover, HR SOI has also demonstrated some advantages concerning the performances of integrated antennas and a first fully integrated prototype with amplifier, filter and antenna has already been achieved using STMicroelectronics 130 nm CMOS HR SOI technology. This paper will review the MMW performances of STMicrolectronics 65 nm CMOS HR SOI technology from device up to circuit level and discuss the opportunities of MMW SoC integrated on CMOS HR SOI technology.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"416 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123002423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380955
B. Shrestha, Nam-Young Kim
The proposed double cross-coupled differential Colpitts voltage controlled oscillator (VCO) is designed using InGaP/GaAs HBT technology for an adaptive feedback interference cancellation system (AF-ICS). In this paper, two switching transistors were used to steer the bias current and voltage in the VCO core, thereby saving power. The VCO achieves excellent phase noise characteristics of -135 dBc/Hz at 1 MHz offset from carrier frequency (1.630 GHz) when supplied with a control voltage of 0 V Also, its tuning range is around 218 MHz with an output power of -3.91 dBm (including cable loss). It shows the figure of merit (FoM) of -180.5 dBc/Hz. Two pairs of base-collector (BC) diodes are integrated in the tank circuit to increase the VCO tuning range. The optimized chip size is 0.9 mm x 0.9 mm.
{"title":"Double Cross Coupled Colpitts VCO with Low Phase Noise using InGaP/GaAs HBT Technology","authors":"B. Shrestha, Nam-Young Kim","doi":"10.1109/RFIC.2007.380955","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380955","url":null,"abstract":"The proposed double cross-coupled differential Colpitts voltage controlled oscillator (VCO) is designed using InGaP/GaAs HBT technology for an adaptive feedback interference cancellation system (AF-ICS). In this paper, two switching transistors were used to steer the bias current and voltage in the VCO core, thereby saving power. The VCO achieves excellent phase noise characteristics of -135 dBc/Hz at 1 MHz offset from carrier frequency (1.630 GHz) when supplied with a control voltage of 0 V Also, its tuning range is around 218 MHz with an output power of -3.91 dBm (including cable loss). It shows the figure of merit (FoM) of -180.5 dBc/Hz. Two pairs of base-collector (BC) diodes are integrated in the tank circuit to increase the VCO tuning range. The optimized chip size is 0.9 mm x 0.9 mm.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"479 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123032153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380835
V. Dao, Q. Bui, C. Park
A multi-band 900 MHz/1.8 GHz/5.2 GHz low noise amplifier (LNA) which can operate at mobile band of 900 MHz and 1.8 G and WLAN band of 5.2 GHz frequency is proposed. Input matching, noise matching and narrow gain are achieved at three frequency bands by adopting a switched output load and a resistive shunt-feedback circuit. The proposed LNA is designed in TSMC 0.18 um CMOS technology with a supply voltage of 1.8 V. The LNA has gains of 14 dB, 13 dB and 16 dB and noise figures of 2.3 dB, 2.9 dB and 2.7 dB at 900 MHz, 1.8 GHz and 5.2 GHz frequency bands, respectively, while dissipating power of 7.5 mW at all frequency bands.
{"title":"A Multi-band 900MHz/1.8GHz/5.2GHz LNA for Reconfigurable Radio","authors":"V. Dao, Q. Bui, C. Park","doi":"10.1109/RFIC.2007.380835","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380835","url":null,"abstract":"A multi-band 900 MHz/1.8 GHz/5.2 GHz low noise amplifier (LNA) which can operate at mobile band of 900 MHz and 1.8 G and WLAN band of 5.2 GHz frequency is proposed. Input matching, noise matching and narrow gain are achieved at three frequency bands by adopting a switched output load and a resistive shunt-feedback circuit. The proposed LNA is designed in TSMC 0.18 um CMOS technology with a supply voltage of 1.8 V. The LNA has gains of 14 dB, 13 dB and 16 dB and noise figures of 2.3 dB, 2.9 dB and 2.7 dB at 900 MHz, 1.8 GHz and 5.2 GHz frequency bands, respectively, while dissipating power of 7.5 mW at all frequency bands.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126825178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380949
Andre van Bezooijen1, Maurice de Jongh1, Christophe Chanlo1, Henk Lennart Ruijs1, Jan ten Dolle1, Pieter Lok1, Freek van Straten1, Jack Sneep2, Reza Mahmoudi3, Arthur H.M. van Roermund3
To preserve the link quality, in fluctuating operating environments, an adaptive antenna matching module is presented that consists of a 5-bit RF-MEMS switched capacitor array, a bipolar 60/30 V MEMS-biasing voltage generator for improved reliability, and an impedance phase detector that provides information on mismatch. It uses an iterative up-down counting algorithm for robust control. Measurements show proper correction of the antenna reactance, even for a VSWR of 10. The switched capacitor array exhibits a large tuning range from 1 to 15 pF and an insertion loss of 0.4 dB. The detector dynamic range equals 35 dB with an accuracy of 8 degrees from 0.8 to 2 GHz. Adaptive matching will make isolators redundant.
为了在波动的工作环境中保持链路质量，提出了一种自适应天线匹配模块，该模块由一个5位RF-MEMS开关电容阵列、一个双极60/30 V mems偏置电压发生器(用于提高可靠性)和一个阻抗相位检测器(提供失配信息)组成。采用迭代上下计数算法进行鲁棒控制。测量结果表明，即使在10的驻波比下，天线电抗也有适当的校正。该开关电容阵列具有1至15pf的大调谐范围和0.4 dB的插入损耗。该探测器动态范围为35 dB，精度为8度，范围为0.8至2 GHz。自适应匹配将使隔离器冗余。
{"title":"RF-MEMS based adaptive antenna matching module","authors":"Andre van Bezooijen1, Maurice de Jongh1, Christophe Chanlo1, Henk Lennart Ruijs1, Jan ten Dolle1, Pieter Lok1, Freek van Straten1, Jack Sneep2, Reza Mahmoudi3, Arthur H.M. van Roermund3","doi":"10.1109/RFIC.2007.380949","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380949","url":null,"abstract":"To preserve the link quality, in fluctuating operating environments, an adaptive antenna matching module is presented that consists of a 5-bit RF-MEMS switched capacitor array, a bipolar 60/30 V MEMS-biasing voltage generator for improved reliability, and an impedance phase detector that provides information on mismatch. It uses an iterative up-down counting algorithm for robust control. Measurements show proper correction of the antenna reactance, even for a VSWR of 10. The switched capacitor array exhibits a large tuning range from 1 to 15 pF and an insertion loss of 0.4 dB. The detector dynamic range equals 35 dB with an accuracy of 8 degrees from 0.8 to 2 GHz. Adaptive matching will make isolators redundant.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126200137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380844
N. Stanic, A. Balankutty, P. Kinget, Y. Tsividis
We report an ultra-low voltage RF receiver for applications in the 2.4 GHz band, designed in a 90 nm CMOS technology. The sliding-IF receiver prototype includes an LNA, an image-reject LC filter with single-ended to differential conversion, an RF mixer, an LC IF filter, a quadrature IF mixer, RF and IF LO buffers, and an I/Q baseband section with a VGA and a low-pass channel-select filter in each path, all integrated on-chip. It has a programmable overall gain of 30 dB, noise figure of 18 dB, out-of-channel IIP3 of -22 dBm, and 26 dB of on-chip image rejection. The 3.4 mm2 chip consumes 8.5 mW from a 0.5 V supply.
{"title":"A 0.5 V Receiver in 90 nm CMOS for 2.4 GHz Applications","authors":"N. Stanic, A. Balankutty, P. Kinget, Y. Tsividis","doi":"10.1109/RFIC.2007.380844","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380844","url":null,"abstract":"We report an ultra-low voltage RF receiver for applications in the 2.4 GHz band, designed in a 90 nm CMOS technology. The sliding-IF receiver prototype includes an LNA, an image-reject LC filter with single-ended to differential conversion, an RF mixer, an LC IF filter, a quadrature IF mixer, RF and IF LO buffers, and an I/Q baseband section with a VGA and a low-pass channel-select filter in each path, all integrated on-chip. It has a programmable overall gain of 30 dB, noise figure of 18 dB, out-of-channel IIP3 of -22 dBm, and 26 dB of on-chip image rejection. The 3.4 mm2 chip consumes 8.5 mW from a 0.5 V supply.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126021649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380938
D. Lim, Jonghae Kim, J. Plouchart, Daeik D. Kim, Choongyeun Cho, D. Boning
A combination of LC-VCO and 2:1 CML static frequency divider has been fabricated in 65 nm SOI CMOS technology and operates at 70 GHz. A cascoded buffer amplifier is used in VCO-to-divider connection to compensate for the power losses caused by interconnect parasitics, and inductive peaking is employed for bandwidth enhancement. The bias condition of the frequency divider has been tuned to find an optimal bias point in existence of VCO and frequency divider operating range variation. The inter-die variation of VCO and divider performance variations over a wafer and their correlation have been estimated.
LC-VCO和2:1 CML静态分频器的组合采用65 nm SOI CMOS技术制造，工作频率为70 GHz。在vco -分压器连接中使用级联编码缓冲放大器来补偿互连寄生造成的功率损失，并使用感应峰值来增强带宽。对分频器的偏置条件进行了调整，在存在压控振荡器和分频器工作范围变化的情况下，找到了最优偏置点。在晶圆上估计了压控振荡器的芯片间变化和分频器性能的变化及其相关性。
{"title":"Performance and Yield Optimization of mm-Wave PLL Front-End in 65nm SOI CMOS","authors":"D. Lim, Jonghae Kim, J. Plouchart, Daeik D. Kim, Choongyeun Cho, D. Boning","doi":"10.1109/RFIC.2007.380938","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380938","url":null,"abstract":"A combination of LC-VCO and 2:1 CML static frequency divider has been fabricated in 65 nm SOI CMOS technology and operates at 70 GHz. A cascoded buffer amplifier is used in VCO-to-divider connection to compensate for the power losses caused by interconnect parasitics, and inductive peaking is employed for bandwidth enhancement. The bias condition of the frequency divider has been tuned to find an optimal bias point in existence of VCO and frequency divider operating range variation. The inter-die variation of VCO and divider performance variations over a wafer and their correlation have been estimated.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125856808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380834
C. Fu, Chun-Lin Ko, C. Kuo
A CMOS reconfigurable LNA is reported. By combination of switched inductors and varactors it performs continuous frequency tuning from 2.4 to 5.4 GHz with 500 MHz 3 dB-bandwidth. Switching transistor is used to provide variable gain control over a 12 dB-range. The LNA supports standards including Bluetooth, WiMAX, UWB mode-1, 802.11 b/g and part of 802.11a. Fabricated in 0.13 um CMOS process the LNA achieves up to 25 dB power gain, 2.2 dB noise figure, -1 dBm IIP3 while consuming less than 5 mW from 1-V power supply.
{"title":"A 2.4 to 5.4 GHz Low Power CMOS Reconfigurable LNA for Multistandard Wireless Receiver","authors":"C. Fu, Chun-Lin Ko, C. Kuo","doi":"10.1109/RFIC.2007.380834","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380834","url":null,"abstract":"A CMOS reconfigurable LNA is reported. By combination of switched inductors and varactors it performs continuous frequency tuning from 2.4 to 5.4 GHz with 500 MHz 3 dB-bandwidth. Switching transistor is used to provide variable gain control over a 12 dB-range. The LNA supports standards including Bluetooth, WiMAX, UWB mode-1, 802.11 b/g and part of 802.11a. Fabricated in 0.13 um CMOS process the LNA achieves up to 25 dB power gain, 2.2 dB noise figure, -1 dBm IIP3 while consuming less than 5 mW from 1-V power supply.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125460432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380922
J. Qureshi, S. Kim, K. Buisman, C. Huang, M. Pelk, A. Akhnoukh, L. Larson, L. Nanver, L. D. de Vreede
Design trade-offs are presented for varactor-based variable phase-shifters in terms of size, tuning range, bandwidth/phase linearity and large-signal performance. Based on this study, a compact, low-loss (0.6dB/90deg @ 1.0 GHz), wideband and extremely linear varactor-based phase shifter is presented.
{"title":"A Low-Loss Compact Linear Varactor Based Phase-Shifter","authors":"J. Qureshi, S. Kim, K. Buisman, C. Huang, M. Pelk, A. Akhnoukh, L. Larson, L. Nanver, L. D. de Vreede","doi":"10.1109/RFIC.2007.380922","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380922","url":null,"abstract":"Design trade-offs are presented for varactor-based variable phase-shifters in terms of size, tuning range, bandwidth/phase linearity and large-signal performance. Based on this study, a compact, low-loss (0.6dB/90deg @ 1.0 GHz), wideband and extremely linear varactor-based phase shifter is presented.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130423964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380988
Younsuk Kim, B. Ku, Changkun Park, Dong Ho Lee, Songcheol Hong
A fully integrated CMOS RF power amplifier for a 1.8 GHz band EDGE polar transmitter is presented. It is implemented with 0.18-mum CMOS process. The output power is 33.4 ~ 33.5 dBm and the power added efficiency is 39 ~ 41 percent when the frequency varies from 1.71 to 1.91 GHz. The dynamic range is increased by 12 dB with the use of the proposed switchable transformer, which meets the EDGE dynamic range requirement of 37 dB when the supply voltage changes from 0.8 to 3.3 V.
{"title":"A High Dynamic Range CMOS RF Power Amplifier with a Switchable Transformer for Polar Transmitters","authors":"Younsuk Kim, B. Ku, Changkun Park, Dong Ho Lee, Songcheol Hong","doi":"10.1109/RFIC.2007.380988","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380988","url":null,"abstract":"A fully integrated CMOS RF power amplifier for a 1.8 GHz band EDGE polar transmitter is presented. It is implemented with 0.18-mum CMOS process. The output power is 33.4 ~ 33.5 dBm and the power added efficiency is 39 ~ 41 percent when the frequency varies from 1.71 to 1.91 GHz. The dynamic range is increased by 12 dB with the use of the proposed switchable transformer, which meets the EDGE dynamic range requirement of 37 dB when the supply voltage changes from 0.8 to 3.3 V.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125126280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380948
Byung-Wook Min, Gabriel M. Rebeiz
This paper presents 35 GHz single-pole-single-throw (SPST) and single-pole-double-throw (SPDT) CMOS switches using a 0.13 mum BiCMOS process (IBM 8 HP). The CMOS transistors are designed to have a high substrate resistance to minimize the insertion loss and improve power handling capability. The SPST/SPDT switches have a insertion loss of 1.8 dB/2.2 dB, respectively, and an input 1-dB compression point (P1 dB) greater than 22 dBm. The isolation is greater than 30 dB at 35-40 GHz and is achieved using two parallel resonant networks. To our knowledge, this is the first demonstration of low-loss, high-isolation CMOS switches at Ka-band frequencies.
{"title":"Ka-Band Low-Loss and High-Isolation 0.13 /spl mu/m CMOS SPST/SPDT Switches Using High Substrate Resistance","authors":"Byung-Wook Min, Gabriel M. Rebeiz","doi":"10.1109/RFIC.2007.380948","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380948","url":null,"abstract":"This paper presents 35 GHz single-pole-single-throw (SPST) and single-pole-double-throw (SPDT) CMOS switches using a 0.13 mum BiCMOS process (IBM 8 HP). The CMOS transistors are designed to have a high substrate resistance to minimize the insertion loss and improve power handling capability. The SPST/SPDT switches have a insertion loss of 1.8 dB/2.2 dB, respectively, and an input 1-dB compression point (P1 dB) greater than 22 dBm. The isolation is greater than 30 dB at 35-40 GHz and is achieved using two parallel resonant networks. To our knowledge, this is the first demonstration of low-loss, high-isolation CMOS switches at Ka-band frequencies.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133730967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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