Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380863
J. Koskinen, P. Eloranta, P. Seppinen, P. Kosonen, A. Parssinen
The implemented ASICs, intended for mobile terminal usage, comprise a wideband high capacity OFDM direct conversion transceiver front-end for beyond 3G cellular systems. The transceiver operates with 83.2 MHz signal bandwidth and is designed for the operational frequency range of 5.15-5.725 GHz. The receiver and transmitter chips were fabricated with 0.13mum BiCMOS technology.
所实现的asic用于移动终端使用，包括用于3G以上蜂窝系统的宽带高容量OFDM直接转换收发器前端。收发器的信号带宽为83.2 MHz，工作频率范围为5.15-5.725 GHz。接收机和发射机芯片采用0.13 μ m BiCMOS工艺制作。
{"title":"A wideband OFDM transceiver implementation for beyond 3G radio systems","authors":"J. Koskinen, P. Eloranta, P. Seppinen, P. Kosonen, A. Parssinen","doi":"10.1109/RFIC.2007.380863","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380863","url":null,"abstract":"The implemented ASICs, intended for mobile terminal usage, comprise a wideband high capacity OFDM direct conversion transceiver front-end for beyond 3G cellular systems. The transceiver operates with 83.2 MHz signal bandwidth and is designed for the operational frequency range of 5.15-5.725 GHz. The receiver and transmitter chips were fabricated with 0.13mum BiCMOS technology.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129377379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380886
A. Siligaris, C. Mounet, B. Reig, P. Vincent
This paper presents a new modeling method for integrated coplanar wave guides (CPW) and CPW discontinuities implemented in silicon on insulator (SOI) CMOS technology. Empirical equations, which are fitted to 3D EM simulations, are used to describe the electrical behavior of CPW as a function of the line's geometrical parameters. The models are validated through measurements up to 110 GHz. Thanks to accurate full wave simulations, discontinuities such as underpasses, 90deg bends, and tee and cross junctions are improved, and electrical models are developed. All models are easily implemented in commercial CAD tools. Finally, a 60 GHz band-pass filter is designed applying the described models and the simulations are compared to measurements.
{"title":"CPW and discontinuities modeling for circuit design up to 110 GHz in SOI CMOS technology","authors":"A. Siligaris, C. Mounet, B. Reig, P. Vincent","doi":"10.1109/RFIC.2007.380886","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380886","url":null,"abstract":"This paper presents a new modeling method for integrated coplanar wave guides (CPW) and CPW discontinuities implemented in silicon on insulator (SOI) CMOS technology. Empirical equations, which are fitted to 3D EM simulations, are used to describe the electrical behavior of CPW as a function of the line's geometrical parameters. The models are validated through measurements up to 110 GHz. Thanks to accurate full wave simulations, discontinuities such as underpasses, 90deg bends, and tee and cross junctions are improved, and electrical models are developed. All models are easily implemented in commercial CAD tools. Finally, a 60 GHz band-pass filter is designed applying the described models and the simulations are compared to measurements.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126459237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380962
T. Thrivikraman, W. Kuo, J. Comeau, A. Sutton, J. Cressler, P. Marshall, M. Mitchell
This paper presents a low-power X-band low-noise amplifier (LNA) implemented in silicon-germanium (SiGe) technology targeting high-altitude or space-based low-power density phased-array radar systems. To our knowledge, this X-band LNA is the first in a Si-based technology to achieve less than 2 dB mean noise figure while dissipating only 2 mW from a 1.5 V power supply. The gain of the circuit is 10 dB at 10 GHz with an IIP 3 of 0 dBm. In addition to standard amplifier characterization, the LNA's total dose radiation response has been evaluated.
{"title":"A 2 mW, Sub-2 dB Noise Figure, SiGe Low-Noise Amplifier For X-band High-Altitude or Space-based Radar Applications","authors":"T. Thrivikraman, W. Kuo, J. Comeau, A. Sutton, J. Cressler, P. Marshall, M. Mitchell","doi":"10.1109/RFIC.2007.380962","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380962","url":null,"abstract":"This paper presents a low-power X-band low-noise amplifier (LNA) implemented in silicon-germanium (SiGe) technology targeting high-altitude or space-based low-power density phased-array radar systems. To our knowledge, this X-band LNA is the first in a Si-based technology to achieve less than 2 dB mean noise figure while dissipating only 2 mW from a 1.5 V power supply. The gain of the circuit is 10 dB at 10 GHz with an IIP 3 of 0 dBm. In addition to standard amplifier characterization, the LNA's total dose radiation response has been evaluated.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133416647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380953
D. Shi, J. East, M. Flynn
A novel on-chip capacitively-loaded, transmission-line-standing-wave resonator is employed in a low phase noise VCO, to achieve a measured phase noise of-117dBc/Hz at a 1MHz offset. The prototype 5 GHz VCO, implemented in 0.13 mum CMOS, dissipates 3 mW from a 1.2 V supply, and occupies a compact die area of 0.11mm2.
在低相位噪声压控振荡器中采用了一种新型片上电容负载的传输线驻波谐振器，在1MHz偏置下实现了117dbc /Hz的相位噪声测量。原型5 GHz压控振荡器采用0.13 μ m CMOS, 1.2 V电源功耗为3 mW，芯片面积紧凑，为0.11mm2。
{"title":"A Compact 5GHz Standing-Wave Resonator-based VCO in 0.13/spl mu/m CMOS","authors":"D. Shi, J. East, M. Flynn","doi":"10.1109/RFIC.2007.380953","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380953","url":null,"abstract":"A novel on-chip capacitively-loaded, transmission-line-standing-wave resonator is employed in a low phase noise VCO, to achieve a measured phase noise of-117dBc/Hz at a 1MHz offset. The prototype 5 GHz VCO, implemented in 0.13 mum CMOS, dissipates 3 mW from a 1.2 V supply, and occupies a compact die area of 0.11mm2.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"11 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113939202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380901
Yiping Han, L. Larson
A 5 GHz direct conversion transceiver is fabricated in a 0.13 mum CMOS process for WLAN 802.11a applications. The transmitter achieves -56 dBc LO leakage, -36 dBc sideband rejection, -43 dBc 3rd harmonic suppression at 5.4 GHz, and an EVM of 3.4% at 5.1 GHz with 60 mW power consumption. The receiver achieves 3.3 dB NF, 27 dB conversion gain, -12 dBm IIP3, and a measured 1/f noise corner of 110 kHz with 36 mW power consumption from a 1.2 V supply voltage. The active area was 0.9 mm2.
{"title":"A Low-Power 5GHz Transceiver in 0.13 /spl mu/m CMOS for OFDM Applications with Sub-mm2 Area","authors":"Yiping Han, L. Larson","doi":"10.1109/RFIC.2007.380901","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380901","url":null,"abstract":"A 5 GHz direct conversion transceiver is fabricated in a 0.13 mum CMOS process for WLAN 802.11a applications. The transmitter achieves -56 dBc LO leakage, -36 dBc sideband rejection, -43 dBc 3rd harmonic suppression at 5.4 GHz, and an EVM of 3.4% at 5.1 GHz with 60 mW power consumption. The receiver achieves 3.3 dB NF, 27 dB conversion gain, -12 dBm IIP3, and a measured 1/f noise corner of 110 kHz with 36 mW power consumption from a 1.2 V supply voltage. The active area was 0.9 mm2.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121239807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380990
Heeyong Yoo, Jongsik Kim, Tae Wook Kim, M. Jeong, Youngho Cho, Bonkee Kim, Hyunchol Shin, Boeun Kim, B. Ko
A low power high linear transmitter for mobile WiBro and WiMAX is developed. The transmitter is fabricated in a 0.18 mum 1P6M CMOS process for low power characteristics and SoC compatibility. To achieve high linearity performance with low power consumption, the transmitter employs new linearization methods. Linear transconductor is used for the transmitter mixer. The transconductor utilizes a negative feedback amplifier and a current mirror amplifier (CMA). In addition, a multiple-gated transistor (MGTR) with two auxiliary transistors and resistive source degeneration are used for the driver amplifier. With the proposed linearization techniques, a high linearity of 30.5 dBm OIP3 is achieved with 97.2 mW power consumption from a 1.8 V supply.
研制了一种适用于移动WiBro和WiMAX的低功率高线性发射机。该发射器采用0.18 μ m 1P6M CMOS工艺制造，具有低功耗特性和SoC兼容性。为了在低功耗下实现高线性性能，变送器采用了新的线性化方法。发射机混频器采用线性变换器。该晶体管采用一个负反馈放大器和一个电流镜像放大器(CMA)。此外，驱动放大器采用了带两个辅助晶体管的多门控晶体管(MGTR)和电阻源退化。采用所提出的线性化技术，在1.8 V电源的97.2 mW功耗下实现了30.5 dBm OIP3的高线性度。
{"title":"A 97.2 mW 1.8 GHz Low Power CMOS Transmitter for Mobile WiBro and WiMAX","authors":"Heeyong Yoo, Jongsik Kim, Tae Wook Kim, M. Jeong, Youngho Cho, Bonkee Kim, Hyunchol Shin, Boeun Kim, B. Ko","doi":"10.1109/RFIC.2007.380990","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380990","url":null,"abstract":"A low power high linear transmitter for mobile WiBro and WiMAX is developed. The transmitter is fabricated in a 0.18 mum 1P6M CMOS process for low power characteristics and SoC compatibility. To achieve high linearity performance with low power consumption, the transmitter employs new linearization methods. Linear transconductor is used for the transmitter mixer. The transconductor utilizes a negative feedback amplifier and a current mirror amplifier (CMA). In addition, a multiple-gated transistor (MGTR) with two auxiliary transistors and resistive source degeneration are used for the driver amplifier. With the proposed linearization techniques, a high linearity of 30.5 dBm OIP3 is achieved with 97.2 mW power consumption from a 1.8 V supply.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"282 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121369752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380975
J. Alvarado, K. Kornegay, D. Dawn, S. Pinel, J. Laskar
A monolithic 60 GHz low-noise amplifier (LNA) using a passive noise suppression technique and an enhanced hybrid transmission line structure, fabricated in a 0.12 mum SiGe BiCMOS process is presented. This design provides the entire circuit with a conductive path to ground the P-substrate. Near active device regions, noise injection and crosstalk paths are shunted to ground. Measurements of the single-stage LNA show peak performance at 59 GHz exhibiting a gain of 14.5 dB, a NF of 4.1 dB, a + 1.5 dBm output compression point, while consuming 4.5 mA from a 1.8 v supply. Across the entire V-band (57 - 64 GHz), the LNA provides a minimum gain of 12 dB with an average noise figure of 5 dB. This LNA has the highest known figure of merit reported for a 60 GHz application.
{"title":"60-GHz LNA using a Hybrid Transmission Line and Conductive Path to Ground Technique in Silicon","authors":"J. Alvarado, K. Kornegay, D. Dawn, S. Pinel, J. Laskar","doi":"10.1109/RFIC.2007.380975","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380975","url":null,"abstract":"A monolithic 60 GHz low-noise amplifier (LNA) using a passive noise suppression technique and an enhanced hybrid transmission line structure, fabricated in a 0.12 mum SiGe BiCMOS process is presented. This design provides the entire circuit with a conductive path to ground the P-substrate. Near active device regions, noise injection and crosstalk paths are shunted to ground. Measurements of the single-stage LNA show peak performance at 59 GHz exhibiting a gain of 14.5 dB, a NF of 4.1 dB, a + 1.5 dBm output compression point, while consuming 4.5 mA from a 1.8 v supply. Across the entire V-band (57 - 64 GHz), the LNA provides a minimum gain of 12 dB with an average noise figure of 5 dB. This LNA has the highest known figure of merit reported for a 60 GHz application.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129318823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380858
S. Rockwell, D. Lim, B. Bosco, J. Baker, B. Eliasson, K. Forsyth, M. Cromar
In this paper we present measurements, models, and circuit implementations for a new low cost, thin film, metal/double-insulator/metal (MIIM) based tunneling diode technology. The device technology uses two insulators to form a tunneling device with very high speed performance capability, and is potentially compatible with many substrate technologies. This technology can potentially reduce cost, size, and improve performance for applications associated with high-speed communications, automotive collision avoidance and navigation, and homeland security weapons detection. Measured results of DC, S-parameter, and responsivity measurements in the 60 GHz band will be presented, including unmatched responsivity at 60 GHz of over 1000 V/W at -20 dBm, which is competitive with detector diodes on GaAs or Sb-based materials. ADS-compatible non-linear models are developed and demonstrated, and an envelope detector design and results is presented.
{"title":"Characterization and Modeling of Metal/Double-Insulator/Metal Diodes for Millimeter Wave Wireless Receiver Applications","authors":"S. Rockwell, D. Lim, B. Bosco, J. Baker, B. Eliasson, K. Forsyth, M. Cromar","doi":"10.1109/RFIC.2007.380858","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380858","url":null,"abstract":"In this paper we present measurements, models, and circuit implementations for a new low cost, thin film, metal/double-insulator/metal (MIIM) based tunneling diode technology. The device technology uses two insulators to form a tunneling device with very high speed performance capability, and is potentially compatible with many substrate technologies. This technology can potentially reduce cost, size, and improve performance for applications associated with high-speed communications, automotive collision avoidance and navigation, and homeland security weapons detection. Measured results of DC, S-parameter, and responsivity measurements in the 60 GHz band will be presented, including unmatched responsivity at 60 GHz of over 1000 V/W at -20 dBm, which is competitive with detector diodes on GaAs or Sb-based materials. ADS-compatible non-linear models are developed and demonstrated, and an envelope detector design and results is presented.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114599478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380977
A. Maxim
Several coupled noise rejection techniques are proposed for LC oscillators operating in noisy mixed signal SoC environment. A simple metal guard ring around the LC-VCO can achieve up to lOdB of coupled noise rejection with a minimal area penalty and no additional processing steps. The best noise rejection (>60dB) was achieved with a full metal cage realized both in IC metal layers and in thick package layers. A compromise between cost, area and performance was achieved with a partial metal cage with no top plate and having graded lateral walls and a grid type bottom plate halo. Spur rejection up to 35 dB with only a 10% penalty in inductor quality factor were achieved. The different inductor structures were realized in 0.13 mum CMOS and the phase noise and spur rejection capability were investigated while operating on the same die with a large digital core.
针对LC振荡器在混合噪声SoC环境下工作的特点，提出了几种耦合噪声抑制技术。LC-VCO周围一个简单的金属保护环可以实现高达lOdB的耦合噪声抑制，面积损失最小，无需额外的处理步骤。在IC金属层和厚封装层中都实现了全金属笼，实现了最佳的噪声抑制(>60dB)。在成本、面积和性能之间达成了妥协，采用了没有顶板的部分金属笼，并具有渐变的侧壁和网格型底板晕。实现了高达35db的杂散抑制，电感质量因子仅损失10%。在0.13 μ m CMOS中实现了不同的电感结构，并研究了在同一芯片上工作时的相位噪声和杂散抑制能力。
{"title":"Notice of Violation of IEEE Publication PrinciplesA 10GHz Low Phase Noise 0.13μm CMOS LC-VCO for Mixed Signal SoCs Using Noise Rejection Caged Inductors","authors":"A. Maxim","doi":"10.1109/RFIC.2007.380977","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380977","url":null,"abstract":"Several coupled noise rejection techniques are proposed for LC oscillators operating in noisy mixed signal SoC environment. A simple metal guard ring around the LC-VCO can achieve up to lOdB of coupled noise rejection with a minimal area penalty and no additional processing steps. The best noise rejection (>60dB) was achieved with a full metal cage realized both in IC metal layers and in thick package layers. A compromise between cost, area and performance was achieved with a partial metal cage with no top plate and having graded lateral walls and a grid type bottom plate halo. Spur rejection up to 35 dB with only a 10% penalty in inductor quality factor were achieved. The different inductor structures were realized in 0.13 mum CMOS and the phase noise and spur rejection capability were investigated while operating on the same die with a large digital core.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115275739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380974
A. El Oualkadi, M. El Kaamouchi, J. Paillot, D. Vanhoenacker-Janvier, D. Flandre
This paper proposes to study the design of a novel high-Q fully integrated switched capacitor bandpass filter. This circuit, implemented in CMOS technology, allows a tunable high selectivity over a broad frequency band. The proposed architecture is intended to replace passive surface acoustic wave (SAW) filters in low-cost wireless radio-communication applications. To show the feasibility of the proposed filter a prototype has been fabricated and tested. Measurements show quality factors up to 300, and a tunable center frequency range of 290 MHz [240 - 530 MHz] with a bandwidth tuning.
{"title":"Fully Integrated High-Q Switched Capacitor Bandpass Filter with Center Frequency and Bandwidth Tuning","authors":"A. El Oualkadi, M. El Kaamouchi, J. Paillot, D. Vanhoenacker-Janvier, D. Flandre","doi":"10.1109/RFIC.2007.380974","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380974","url":null,"abstract":"This paper proposes to study the design of a novel high-Q fully integrated switched capacitor bandpass filter. This circuit, implemented in CMOS technology, allows a tunable high selectivity over a broad frequency band. The proposed architecture is intended to replace passive surface acoustic wave (SAW) filters in low-cost wireless radio-communication applications. To show the feasibility of the proposed filter a prototype has been fabricated and tested. Measurements show quality factors up to 300, and a tunable center frequency range of 290 MHz [240 - 530 MHz] with a bandwidth tuning.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114646665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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