Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380943
Chinmaya Mishra, U. Pfeiffer, R. Rassel, S. Reynolds
This paper presents circuits based on Schottky barrier diodes (SBDs) in IBM's 0.13-mum SiGe BiCMOS process. Circuits such as sub-harmonic up-conversion mixers and frequency doublers are demonstrated at frequencies beyond 100 GHz on silicon. These circuits enable power generation at millimeter wave frequencies on silicon. The frequency doublers can deliver >0 dBm output power at 110 GHz and the 2X sub-harmonic up converters exhibit peak conversion loss of <3 dB up to 120 GHz.
本文介绍了基于肖特基势垒二极管(sbd)的电路，采用IBM的0.13 μ m SiGe BiCMOS工艺。电路，如次谐波上变频混频器和倍频器在频率超过100 GHz的硅演示。这些电路可以在硅上以毫米波频率发电。倍频器在110 GHz时的输出功率大于0 dBm，而2X次谐波上变频器在120 GHz时的峰值转换损耗小于3 dB。
{"title":"Silicon Schottky Diode Power Converters Beyond 100 GHz","authors":"Chinmaya Mishra, U. Pfeiffer, R. Rassel, S. Reynolds","doi":"10.1109/RFIC.2007.380943","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380943","url":null,"abstract":"This paper presents circuits based on Schottky barrier diodes (SBDs) in IBM's 0.13-mum SiGe BiCMOS process. Circuits such as sub-harmonic up-conversion mixers and frequency doublers are demonstrated at frequencies beyond 100 GHz on silicon. These circuits enable power generation at millimeter wave frequencies on silicon. The frequency doublers can deliver >0 dBm output power at 110 GHz and the 2X sub-harmonic up converters exhibit peak conversion loss of <3 dB up to 120 GHz.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125337715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380843
Wenjian Chen, T. Copani, H. Barnaby, S. Kiaei
This paper presents an ultra-low power monolithic CMOS RF receiver, consisting of current re-use common gate LNA with inductive feedback gm-boosting, and followed by balanced I/Q mixers. The receiver is fabricated in a 0.13-mum CMOS digital process operating at 2.45 GHZ. The measurement results show that the RF receiver achieves a gain of 20 dB and a noise figure of 7.5 dB at 2 MHz. Input 1-dB compression point is -19 dBm and IIP3 is -10 tlBm, with 0.4 mA total current consumption from a 1.5-V supply.
{"title":"A 0.13-/spl mu/m CMOS Ultra-Low Power Front-End Receiver for Wireless Sensor Networks","authors":"Wenjian Chen, T. Copani, H. Barnaby, S. Kiaei","doi":"10.1109/RFIC.2007.380843","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380843","url":null,"abstract":"This paper presents an ultra-low power monolithic CMOS RF receiver, consisting of current re-use common gate LNA with inductive feedback gm-boosting, and followed by balanced I/Q mixers. The receiver is fabricated in a 0.13-mum CMOS digital process operating at 2.45 GHZ. The measurement results show that the RF receiver achieves a gain of 20 dB and a noise figure of 7.5 dB at 2 MHz. Input 1-dB compression point is -19 dBm and IIP3 is -10 tlBm, with 0.4 mA total current consumption from a 1.5-V supply.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"4 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126107084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380864
F. Rivet, Y. Deval, J. Bégueret, D. Dallet, D. Belot
Software defined radio (SDR) aims at bringing digital treatment chip closer to the antenna in a mobile terminal architecture. The main goal is to create a re-configurable radio architecture accepting all the cellular or non-cellular standards working in the 0-5 GHz frequency range. But, in this environment, the analog to digital conversion and the digital operations face issues like power supply and processing speed. The idea is to interface a preprocessing circuit between the antenna and a digital signal processor (DSP) to pre-condition the RF signal. This paper presents the design of an analog discrete-time device located between antenna and a DSP in standard radio architecture. It uses the principle of the discrete Fourier transform (DFT) to reduce the frequency of the DSP-input-signal treatment to fulfil the SDR purpose. It has been validated through system level simulation.
{"title":"A Disruptive Software-Defined Radio Receiver Architecture Based on Sampled Analog Signal Processing","authors":"F. Rivet, Y. Deval, J. Bégueret, D. Dallet, D. Belot","doi":"10.1109/RFIC.2007.380864","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380864","url":null,"abstract":"Software defined radio (SDR) aims at bringing digital treatment chip closer to the antenna in a mobile terminal architecture. The main goal is to create a re-configurable radio architecture accepting all the cellular or non-cellular standards working in the 0-5 GHz frequency range. But, in this environment, the analog to digital conversion and the digital operations face issues like power supply and processing speed. The idea is to interface a preprocessing circuit between the antenna and a digital signal processor (DSP) to pre-condition the RF signal. This paper presents the design of an analog discrete-time device located between antenna and a DSP in standard radio architecture. It uses the principle of the discrete Fourier transform (DFT) to reduce the frequency of the DSP-input-signal treatment to fulfil the SDR purpose. It has been validated through system level simulation.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126936646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380981
Ja-yol Lee, Sang-Heung Lee, Hae-cheon Kim, Hyun-Kyu Yu
A 45 - 60-GHz two-band double cross-coupled differential VCO is designed and fabricated using 0.25 mum SiG:C BiCMOS process technology whose fmax is greater than 200 GHz. The VCO provides tuning ranges of 44.9 - 48.9 GHz when its bias current is 13 mA and of 58 - 60.4 GHz when a bias current of 7 mA draws into the VCO. The phase noises of the VCO are measured as - 99 dBc/Hz from 48.86 GHz and - 93 dBc/Hz from 60.32 GHz, at 10 MHz offset, respectively. The VCO shows moderate FOMs of 156 dBc at 60.32 GHz and 158 dBc at 48.86 GHz.
{"title":"A 45-to-60-GHz Two-Band SiGe: C VCO for Millimeter-Wave Applications","authors":"Ja-yol Lee, Sang-Heung Lee, Hae-cheon Kim, Hyun-Kyu Yu","doi":"10.1109/RFIC.2007.380981","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380981","url":null,"abstract":"A 45 - 60-GHz two-band double cross-coupled differential VCO is designed and fabricated using 0.25 mum SiG:C BiCMOS process technology whose fmax is greater than 200 GHz. The VCO provides tuning ranges of 44.9 - 48.9 GHz when its bias current is 13 mA and of 58 - 60.4 GHz when a bias current of 7 mA draws into the VCO. The phase noises of the VCO are measured as - 99 dBc/Hz from 48.86 GHz and - 93 dBc/Hz from 60.32 GHz, at 10 MHz offset, respectively. The VCO shows moderate FOMs of 156 dBc at 60.32 GHz and 158 dBc at 48.86 GHz.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"189 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122053999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380936
H. Sharifi, S. Mohammadi
A fully integrated 10 Gb/s 1.3 to 1.55 mum CMOS optoelectronic receiver is demonstrated for the first time. By heterogeneously integrating of a CMOS transimpedance amplifier (TIA) with an InGaAs/InP PIN photodiode using a recently developed self-aligned wafer-level integration technology (SAWLIT), operation at 10 Gb/s is achieved. The CMOS transimpedance amplifier exhibits a transimpedance gain of 51 dBOmega and a bandwidth of 6.1 GHz.
{"title":"Heterogeneously Integrated 10Gb/s CMOS Optoelectronic Receiver for Long Haul Telecommunication","authors":"H. Sharifi, S. Mohammadi","doi":"10.1109/RFIC.2007.380936","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380936","url":null,"abstract":"A fully integrated 10 Gb/s 1.3 to 1.55 mum CMOS optoelectronic receiver is demonstrated for the first time. By heterogeneously integrating of a CMOS transimpedance amplifier (TIA) with an InGaAs/InP PIN photodiode using a recently developed self-aligned wafer-level integration technology (SAWLIT), operation at 10 Gb/s is achieved. The CMOS transimpedance amplifier exhibits a transimpedance gain of 51 dBOmega and a bandwidth of 6.1 GHz.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122073108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380956
Chien-Cheng Wei, H. Chiu, Wu-Shiung Feng
This paper presents a voltage-controlled oscillator (VCO) with low phase noise by employing the CMOS field-plate (FP) transistors. The proposed FP transistors perform the improvement in flicker noise (1/f noise) was demonstrated in our previous investigation. A complete large-signal model for FP transistors was established by modified BSIM4 model with lossy substrate networks. The proposed 12-GHz VCO with FP transistors was designed and fabricated in TSMC 0.13-mum CMOS process. The measured characteristic of phase noise is -122 dBc/Hz at 1-MHz offset frequency. Compare with a conventional VCO, this novel design shows that the proposed VCO achieves lower phase noise about 5 dBc at offset frequency from 100-kHz to 1-MHz.
{"title":"A 12-GHz Low Phase Noise VCO By Employing CMOS Field-Plate Transistors","authors":"Chien-Cheng Wei, H. Chiu, Wu-Shiung Feng","doi":"10.1109/RFIC.2007.380956","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380956","url":null,"abstract":"This paper presents a voltage-controlled oscillator (VCO) with low phase noise by employing the CMOS field-plate (FP) transistors. The proposed FP transistors perform the improvement in flicker noise (1/f noise) was demonstrated in our previous investigation. A complete large-signal model for FP transistors was established by modified BSIM4 model with lossy substrate networks. The proposed 12-GHz VCO with FP transistors was designed and fabricated in TSMC 0.13-mum CMOS process. The measured characteristic of phase noise is -122 dBc/Hz at 1-MHz offset frequency. Compare with a conventional VCO, this novel design shows that the proposed VCO achieves lower phase noise about 5 dBc at offset frequency from 100-kHz to 1-MHz.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121316502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a compact transmission line (TL) structure, which comprises one signal line surrounded by two vertical ground planes (VGPs). A V-band amplifier using VGP TLs for matching is also implemented in 130-nm CMOS technology with a peak gain of 18.3 dB at 52 GHz with a compact area of only 0.36 mm while consuming 19 mW from a 1.2-V supply. Compared to other V-band CMOS amplifiers using TLs for matching, this amplifier has the lowest power consumption and smallest chip size.
{"title":"Vertical-Ground-Plane Transmission Lines for Miniaturized Silicon-Based MMICs","authors":"Juin-Wei Huang, Chao-Shiun Wang, Chorng-Kuang Wang, Shin-Huang Yeh","doi":"10.1109/RFIC.2007.380947","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380947","url":null,"abstract":"This paper presents a compact transmission line (TL) structure, which comprises one signal line surrounded by two vertical ground planes (VGPs). A V-band amplifier using VGP TLs for matching is also implemented in 130-nm CMOS technology with a peak gain of 18.3 dB at 52 GHz with a compact area of only 0.36 mm while consuming 19 mW from a 1.2-V supply. Compared to other V-band CMOS amplifiers using TLs for matching, this amplifier has the lowest power consumption and smallest chip size.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134214920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380850
S. Pruvost, R. Cuchet, D. Pellissier, I. Telliez, M. Devulder, X. Gagnard, P. Ancey, M. Aid, F. Danneville, G. Dambrine, N. Rolland, S. Lépilliet
This paper presents a low area, low consumption, 40 GHz low noise amplifier (LNA), a down-converter and an oscillator, from which the performance of a 40 GHz wireless receiver can be estimated. The circuits were realized using a post-processing BCB above-IC technology and 0.13 mum SiGe:C BiCMOS HBT process, and their performance are compared with those obtained on circuits without post-processing. The 40 GHz LNA exhibits a noise figure of 2.2 dB with an associated gain of 17 dB and a DC power consumption of 20 mW. The measured double-sideband noise figure of the mixer is 4.7 dB with an associated conversion gain of 6.5 dB and a DC consumption of 4.8 mW. The 40 GHz oscillator has a phase noise of -107 dBc/Hz at 1 MHz offset from the carrier measured on a 50 Ohms load. The oscillator output power is 0 dBm for a DC consumption of 15 mW. Beyond these never published results in term of noise figure at 40 GHz, this post-processing technology gives the opportunity to determine the intrinsic noise figure value of the active device (HBT).
{"title":"40GHz Low Noise Receiver Circuits using BCB Above-Silicon Technology Optimized for Millimeter-wave Applications","authors":"S. Pruvost, R. Cuchet, D. Pellissier, I. Telliez, M. Devulder, X. Gagnard, P. Ancey, M. Aid, F. Danneville, G. Dambrine, N. Rolland, S. Lépilliet","doi":"10.1109/RFIC.2007.380850","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380850","url":null,"abstract":"This paper presents a low area, low consumption, 40 GHz low noise amplifier (LNA), a down-converter and an oscillator, from which the performance of a 40 GHz wireless receiver can be estimated. The circuits were realized using a post-processing BCB above-IC technology and 0.13 mum SiGe:C BiCMOS HBT process, and their performance are compared with those obtained on circuits without post-processing. The 40 GHz LNA exhibits a noise figure of 2.2 dB with an associated gain of 17 dB and a DC power consumption of 20 mW. The measured double-sideband noise figure of the mixer is 4.7 dB with an associated conversion gain of 6.5 dB and a DC consumption of 4.8 mW. The 40 GHz oscillator has a phase noise of -107 dBc/Hz at 1 MHz offset from the carrier measured on a 50 Ohms load. The oscillator output power is 0 dBm for a DC consumption of 15 mW. Beyond these never published results in term of noise figure at 40 GHz, this post-processing technology gives the opportunity to determine the intrinsic noise figure value of the active device (HBT).","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134372746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380831
M. Vidojkovic, M. Sanduleanu, J. van der Tang, P. Baltus, A. V. van Roermund
This paper presents a novel broadband, inductorless, resistive-feedback CMOS LNA. The LNA is designed for the frequency band 0.4 - 1 GHz. The measured power gain of the LNA is 16 dB at 1 GHz and the 3-dB bandwidth is 2 GHz. A noise figure of 3.5 dB and an IIP3 of -17 dBm are measured at 900 MHz. The S11 is better than -10 dB in the frequency band from 300 MHz up to 1 GHz. The current consumption is 14 mA from a 1.2 V supply. The circuit is designed in a baseline CMOS 90 nm low power (LP) process.
{"title":"A 1.2 V, Inductorless, Broadband LNA in 90 nm CMOS LP","authors":"M. Vidojkovic, M. Sanduleanu, J. van der Tang, P. Baltus, A. V. van Roermund","doi":"10.1109/RFIC.2007.380831","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380831","url":null,"abstract":"This paper presents a novel broadband, inductorless, resistive-feedback CMOS LNA. The LNA is designed for the frequency band 0.4 - 1 GHz. The measured power gain of the LNA is 16 dB at 1 GHz and the 3-dB bandwidth is 2 GHz. A noise figure of 3.5 dB and an IIP3 of -17 dBm are measured at 900 MHz. The S11 is better than -10 dB in the frequency band from 300 MHz up to 1 GHz. The current consumption is 14 mA from a 1.2 V supply. The circuit is designed in a baseline CMOS 90 nm low power (LP) process.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131997869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380928
K. Seemann, M. Hartmann, F. Cilek, A. Missoni, G. Holweg, R. Weigel
A nonlinear RFID frontend behavioral model has been developed. By using this model the simulation time for inlay optimizations can be decreased considerably and the models hide the IC manufacturer's intellectual properties. The inherent model order reduction is based on nonlinear state-space mapping using derivative coordinates and harmonic-balance simulations. Feedforward multi-layer-perceptron artificial-neural-networks have been used for the nonlinear multivariate system mapping. The behavioral modeling of RF power rectification, RF voltage limiting and backscatter modulation is demonstrated for a modern passive UHF-RFID CMOS frontend.
{"title":"Nonlinear Behavioral Modeling of Passive RFID-Transponder-Frontends","authors":"K. Seemann, M. Hartmann, F. Cilek, A. Missoni, G. Holweg, R. Weigel","doi":"10.1109/RFIC.2007.380928","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380928","url":null,"abstract":"A nonlinear RFID frontend behavioral model has been developed. By using this model the simulation time for inlay optimizations can be decreased considerably and the models hide the IC manufacturer's intellectual properties. The inherent model order reduction is based on nonlinear state-space mapping using derivative coordinates and harmonic-balance simulations. Feedforward multi-layer-perceptron artificial-neural-networks have been used for the nonlinear multivariate system mapping. The behavioral modeling of RF power rectification, RF voltage limiting and backscatter modulation is demonstrated for a modern passive UHF-RFID CMOS frontend.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"295 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116169156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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