Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380902
H. Morkner, M. Vice, M. Karakucuk, W. Abey, L. Nguyen, J. Kessler, R. Ruebusch
An enhancement mode PHEMT MMIC with integrated dual low noise amplifiers, dual switches, and dual distortion compensation power amplifiers is presented. It is used in an 802.11abgn FEM (front end module) which further integrates the antenna diplexer, LNA post filters, PA pre-filters, and baluns. The LNAs provide less than 1.2 dB noise figure in the 2.4/5-6 GHz receive chains at 16 dB gain and 10 mA. The switches can handle up to 30 dBm peak power with less than 1.4 dB loss and with 25 dB isolation. The power amplifier section provides fully matched 26 dB gain with 25 dBm of saturated power. In the 802.11g 2.4GHz transmit mode the MMIC gives over 20 Bm linear power out under 54 Mbps OFDM, at 4% EVM, while drawing only 123 mA of peak current. In the 802.11 a 5-6 GHz transmit mode the MMIC gives over 20 dBm linear power out under 54 Mbps OFDM at 6% EVM while drawing 149 mA of peak current. The MMIC has integrated all control functions for power down and mode select; while the power amplifiers have integrated directional couplers and temperature compensated power detection. This is the highest integration and performance level combination known to be published for 802.11abgn application specific integrated circuits.
{"title":"A Single Chip 802.11abgn Enhancement Mode PHEMT MMIC with dual LNAs, Switches, and Distortion Compensation Power Amplifiers","authors":"H. Morkner, M. Vice, M. Karakucuk, W. Abey, L. Nguyen, J. Kessler, R. Ruebusch","doi":"10.1109/RFIC.2007.380902","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380902","url":null,"abstract":"An enhancement mode PHEMT MMIC with integrated dual low noise amplifiers, dual switches, and dual distortion compensation power amplifiers is presented. It is used in an 802.11abgn FEM (front end module) which further integrates the antenna diplexer, LNA post filters, PA pre-filters, and baluns. The LNAs provide less than 1.2 dB noise figure in the 2.4/5-6 GHz receive chains at 16 dB gain and 10 mA. The switches can handle up to 30 dBm peak power with less than 1.4 dB loss and with 25 dB isolation. The power amplifier section provides fully matched 26 dB gain with 25 dBm of saturated power. In the 802.11g 2.4GHz transmit mode the MMIC gives over 20 Bm linear power out under 54 Mbps OFDM, at 4% EVM, while drawing only 123 mA of peak current. In the 802.11 a 5-6 GHz transmit mode the MMIC gives over 20 dBm linear power out under 54 Mbps OFDM at 6% EVM while drawing 149 mA of peak current. The MMIC has integrated all control functions for power down and mode select; while the power amplifiers have integrated directional couplers and temperature compensated power detection. This is the highest integration and performance level combination known to be published for 802.11abgn application specific integrated circuits.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124052187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380984
R. Tayrani
This paper describes the design and fabrication of a highly efficient broadband monolithic class-E power amplifier utilizing a new distributed class-E load topology. The amplifier maintains a simultaneous high PAE and output Power over 7.0 GHz of bandwidth. The HPA's measured performance shows a PAE range of (50 % to 82 %) and an output power of >25 dBm across 7-14 GHz. The new broadband load also allows the HPA to have excellent spectrally pure frequency response demonstrated by its low AM and PM noise. A single 0.25 um x 720 um GaAs pHEMT device is used in this circuit.
本文介绍了一种利用新型分布式e类负载拓扑结构的高效宽带单片e类功率放大器的设计和制造。放大器同时保持高PAE和输出功率超过7.0 GHz的带宽。HPA的测量性能显示PAE范围为(50%至82%)，7-14 GHz的输出功率>25 dBm。新的宽带负载还使HPA具有出色的频谱纯净频率响应，其低AM和PM噪声证明了这一点。该电路使用单个0.25 um x 720 um的GaAs pHEMT器件。
{"title":"A Highly Efficient Broadband (7-14 GHz) Monolithic Class E Power Amplifier for Space Based Radar","authors":"R. Tayrani","doi":"10.1109/RFIC.2007.380984","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380984","url":null,"abstract":"This paper describes the design and fabrication of a highly efficient broadband monolithic class-E power amplifier utilizing a new distributed class-E load topology. The amplifier maintains a simultaneous high PAE and output Power over 7.0 GHz of bandwidth. The HPA's measured performance shows a PAE range of (50 % to 82 %) and an output power of >25 dBm across 7-14 GHz. The new broadband load also allows the HPA to have excellent spectrally pure frequency response demonstrated by its low AM and PM noise. A single 0.25 um x 720 um GaAs pHEMT device is used in this circuit.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128169677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380939
B. Floyd
A 15 to 18-GHz frequency synthesizer is implemented in 0.13-mum SiGe BiCMOS technology as part of a 60-GHz transceiver chipset. It provides for RF channels of 56.5-64 GHz in 500-MHz steps, and features a phase-rotating multi-modulus divider capable of sub-integer division. Output frequency range from the synthesizer is 15.3 to 18 GHz. The measured RMS phase noise of the synthesizer is 0.9deg (1 MHz to 1 GHz integration), while phase noise at 100-kHz and 10-MHz offsets are -90 and -124 dBc/Hz, respectively. Reference spurs are -69 dBc; sub-integer spurs are -65 dBc; and power consumption is 145 mW.
{"title":"A 15 to 18-GHz Programmable Sub-Integer Frequency Synthesizer for a 60-GHz Transceiver","authors":"B. Floyd","doi":"10.1109/RFIC.2007.380939","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380939","url":null,"abstract":"A 15 to 18-GHz frequency synthesizer is implemented in 0.13-mum SiGe BiCMOS technology as part of a 60-GHz transceiver chipset. It provides for RF channels of 56.5-64 GHz in 500-MHz steps, and features a phase-rotating multi-modulus divider capable of sub-integer division. Output frequency range from the synthesizer is 15.3 to 18 GHz. The measured RMS phase noise of the synthesizer is 0.9deg (1 MHz to 1 GHz integration), while phase noise at 100-kHz and 10-MHz offsets are -90 and -124 dBc/Hz, respectively. Reference spurs are -69 dBc; sub-integer spurs are -65 dBc; and power consumption is 145 mW.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"38 10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125734001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380994
C. Fernando, K. Muhammad
We present an efficient approach for evaluating the performance of a wireless receiver in the presence of calibration and/or compensation algorithms and various sources of measurement error. Noise figure and linearity performance of a receiver can be easily predicted over process and temperature variation and statistical estimates can be obtained to predict yield.
{"title":"An Efficient Technique for Performance Analysis of a Receiver in the Presence of Calibration/Compensation Algorithms","authors":"C. Fernando, K. Muhammad","doi":"10.1109/RFIC.2007.380994","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380994","url":null,"abstract":"We present an efficient approach for evaluating the performance of a wireless receiver in the presence of calibration and/or compensation algorithms and various sources of measurement error. Noise figure and linearity performance of a receiver can be easily predicted over process and temperature variation and statistical estimates can be obtained to predict yield.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126108839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380934
J. Bulzacchelli, A. Rylyakov, D. Friedman
A decision-feedback equalizer (DFE) can compensate for severe signal distortion due to limited channel bandwidth, but its typical power consumption is too high for some applications. This paper describes three CMOS DFEs which embody different design techniques for improved power efficiency. The first one, with two taps, uses a soft decision technique to reduce the critical path delay of the first feedback tap, so that the analog summers can be operated at low currents. This DFE consumes 4.8 mW at 6 Gb/s. The second one, with one tap, employs speculation to relax the critical timing. Speculation increases the number of parallel data paths, but the power dissipation of each path is kept low by using a single switched-capacitor circuit for both sampling and DFE summation. This DFE consumes 5.0 mW at 6 Gb/s. The third one, with two taps, also employs speculation. High power efficiency (9.3 mW at 7 Gb/s) is achieved by implementing the analog summers as resettable integrators.
{"title":"Power-Efficient Decision-Feedback Equalizers for Multi-Gb/s CMOS Serial Links","authors":"J. Bulzacchelli, A. Rylyakov, D. Friedman","doi":"10.1109/RFIC.2007.380934","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380934","url":null,"abstract":"A decision-feedback equalizer (DFE) can compensate for severe signal distortion due to limited channel bandwidth, but its typical power consumption is too high for some applications. This paper describes three CMOS DFEs which embody different design techniques for improved power efficiency. The first one, with two taps, uses a soft decision technique to reduce the critical path delay of the first feedback tap, so that the analog summers can be operated at low currents. This DFE consumes 4.8 mW at 6 Gb/s. The second one, with one tap, employs speculation to relax the critical timing. Speculation increases the number of parallel data paths, but the power dissipation of each path is kept low by using a single switched-capacitor circuit for both sampling and DFE summation. This DFE consumes 5.0 mW at 6 Gb/s. The third one, with two taps, also employs speculation. High power efficiency (9.3 mW at 7 Gb/s) is achieved by implementing the analog summers as resettable integrators.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132353974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380871
W. Rahajandraibe, L. Zaid, V. Cheynet de Beaupre, G. Bas
The feasibility of a low cost, 2.5 volts supply phase-locked loop for HomeRF application is demonstrated. Based on IEEE 802.15.4 specifications, this low power and low cost, multi-function PLL is used both in a single conversion receiver as frequency synthesizer and in a direct conversion transmitter as a frequency shift keying (FSK) modulator. Measurement results of the PLL and the open loop modulator together with VCO performances are presented. All the circuits have been fully integrated using 0.28 mum CMOS technology.
论证了一种低成本、2.5伏电源锁相环用于HomeRF应用的可行性。基于IEEE 802.15.4规范，这种低功耗、低成本的多功能锁相环既可用于单转换接收机作为频率合成器，也可用于直接转换发射机作为频移键控(FSK)调制器。给出了锁相环和开环调制器的测量结果以及压控振荡器的性能。所有电路都采用0.28 μ m CMOS技术完全集成。
{"title":"Frequency Synthesizer and FSK Modulator for IEEE 802.15.4 Based Applications","authors":"W. Rahajandraibe, L. Zaid, V. Cheynet de Beaupre, G. Bas","doi":"10.1109/RFIC.2007.380871","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380871","url":null,"abstract":"The feasibility of a low cost, 2.5 volts supply phase-locked loop for HomeRF application is demonstrated. Based on IEEE 802.15.4 specifications, this low power and low cost, multi-function PLL is used both in a single conversion receiver as frequency synthesizer and in a direct conversion transmitter as a frequency shift keying (FSK) modulator. Measurement results of the PLL and the open loop modulator together with VCO performances are presented. All the circuits have been fully integrated using 0.28 mum CMOS technology.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130175288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380932
M. A. Arasu, Yuanjin Zheng, W. Yeoh
A dual-band up-converter (DB-UPC) for a dual-band direct sequence UWB transmitter is demonstrated in 0.18-mum CMOS. The DB-UPC translates a base-band UWB pulse to a 3-5 GHz low-band or 7-9 GHz high band. The DB-UPC consists of two mixers followed by a combiner. The high and low band mixers consist of a fully differential mixer core followed by a differential to single-ended converter. The DB-UPC has linear transfer characteristic for up to 0.7Vpp input pulse amplitude. Measured voltage gain and two-tone IIP3 of the DB-UPC are -8 dB, +10 dBm in the low-band and -14 dB, +14 dBm in the high-band respectively.
{"title":"A 3 to 9-GHz Dual-band Up-Converter for a DS-UWB Transmitter in 0.18-/spl mu/m CMOS","authors":"M. A. Arasu, Yuanjin Zheng, W. Yeoh","doi":"10.1109/RFIC.2007.380932","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380932","url":null,"abstract":"A dual-band up-converter (DB-UPC) for a dual-band direct sequence UWB transmitter is demonstrated in 0.18-mum CMOS. The DB-UPC translates a base-band UWB pulse to a 3-5 GHz low-band or 7-9 GHz high band. The DB-UPC consists of two mixers followed by a combiner. The high and low band mixers consist of a fully differential mixer core followed by a differential to single-ended converter. The DB-UPC has linear transfer characteristic for up to 0.7Vpp input pulse amplitude. Measured voltage gain and two-tone IIP3 of the DB-UPC are -8 dB, +10 dBm in the low-band and -14 dB, +14 dBm in the high-band respectively.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127806958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380828
T. Yuan, Yuanjin Zheng, Chyuen-Wei Ang, Lewei Li
In this paper, a fully integrated CMOS UWB transmitter is presented. The transmitter consists of a band-notched UWB antenna and a transmitter IC which integrates a pulse generator, a gating signal generator and driver amplifiers. The drive amplifier employs a 2-stage amplifier-a class-E amplifier and a class-A amplifier with switch control, to significantly reduce power consumption. Fabricated using a 0.18-mum CMOS process, the generated pulse is then passed through the driver amplifier (DA) which not only drives the antenna but also shapes the generated digital pulse in the FCC spectral mask.
本文介绍了一种全集成 CMOS UWB 发射器。该发射器由一个带状缺口 UWB 天线和一个发射器集成电路组成，其中集成了脉冲发生器、门控信号发生器和驱动放大器。驱动放大器采用两级放大器--一个 E 类放大器和一个带开关控制的 A 类放大器，从而大大降低了功耗。产生的脉冲采用 0.18 微米 CMOS 工艺制造，然后通过驱动放大器 (DA)，该放大器不仅驱动天线，还能在 FCC 频谱掩模中形成产生的数字脉冲。
{"title":"A Fully Integrated CMOS Transmitter for Ultra-wideband Applications","authors":"T. Yuan, Yuanjin Zheng, Chyuen-Wei Ang, Lewei Li","doi":"10.1109/RFIC.2007.380828","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380828","url":null,"abstract":"In this paper, a fully integrated CMOS UWB transmitter is presented. The transmitter consists of a band-notched UWB antenna and a transmitter IC which integrates a pulse generator, a gating signal generator and driver amplifiers. The drive amplifier employs a 2-stage amplifier-a class-E amplifier and a class-A amplifier with switch control, to significantly reduce power consumption. Fabricated using a 0.18-mum CMOS process, the generated pulse is then passed through the driver amplifier (DA) which not only drives the antenna but also shapes the generated digital pulse in the FCC spectral mask.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"139-140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131421428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380970
C. Huang, W. Vaillancourt, C. Masse, J. Soricelli, T. Quaglietta, M. Doherty, A. Long, C. Reiss, G. Rabjohn, A. Parolin
A highly integrated 5 x 5 x 0.9 mm dual-band wireless LAN front-end module (FEM) is presented. The FEM features 29 dB gain and 19 dBm at 54 Mbps with EVM < 3% and 180 mA for 2.4 to 2.5 GHz. For 4.9 to 5.9 GHz transmission, the FEM delivers 25 dB gain and 17 dBm at 54 Mbps with EVM < 3% and 195 mA. The FEM's receive chains can be realized either with LAN having >11.4 dB gain LNA gain with NF < 2.5 dB for the low band and < 2.8 dB for the high band or with used a RX diplexer with <1 insertion loss. The FEM significantly simplifies 802.11 a/b/g radio designs and provides an effective building block for multichannel 802.11n radios designs.
{"title":"A 5 x 5 mm Highly Integrated Dual-band WLAN Front-End Module Simplifies 802.11 a/b/g and 802.11n Radio Designs","authors":"C. Huang, W. Vaillancourt, C. Masse, J. Soricelli, T. Quaglietta, M. Doherty, A. Long, C. Reiss, G. Rabjohn, A. Parolin","doi":"10.1109/RFIC.2007.380970","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380970","url":null,"abstract":"A highly integrated 5 x 5 x 0.9 mm dual-band wireless LAN front-end module (FEM) is presented. The FEM features 29 dB gain and 19 dBm at 54 Mbps with EVM < 3% and 180 mA for 2.4 to 2.5 GHz. For 4.9 to 5.9 GHz transmission, the FEM delivers 25 dB gain and 17 dBm at 54 Mbps with EVM < 3% and 195 mA. The FEM's receive chains can be realized either with LAN having >11.4 dB gain LNA gain with NF < 2.5 dB for the low band and < 2.8 dB for the high band or with used a RX diplexer with <1 insertion loss. The FEM significantly simplifies 802.11 a/b/g radio designs and provides an effective building block for multichannel 802.11n radios designs.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124182507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-03DOI: 10.1109/RFIC.2007.380927
B. Nicolle, W. Tatinian, J.-J. Mayol, J. Oudinot, G. Jacquemod
In this paper, we present a design methodology based on a multi-simulator approach instead of using co-simulation. We based our study on a phase locked loop (PLL) used in RF transceivers for frequency synthesis. We used Simulink as block diagram simulator, ADVance MS (ADMS) as behavioral simulator and Eldo as transistor-level simulator. The proposed results show the accuracy and simulation time for each description level.
在本文中，我们提出了一种基于多模拟器方法的设计方法，而不是使用联合仿真。我们的研究基于射频收发器中用于频率合成的锁相环(PLL)。我们使用Simulink作为框图模拟器，ADVance MS (ADMS)作为行为模拟器，Eldo作为晶体管级模拟器。结果表明，在每个描述层次上，所提方法的精度和仿真时间均有所提高。
{"title":"Top-Down PLL Design Methodology Combining Block Diagram, Behavioral, and Transistor-Level Simulators","authors":"B. Nicolle, W. Tatinian, J.-J. Mayol, J. Oudinot, G. Jacquemod","doi":"10.1109/RFIC.2007.380927","DOIUrl":"https://doi.org/10.1109/RFIC.2007.380927","url":null,"abstract":"In this paper, we present a design methodology based on a multi-simulator approach instead of using co-simulation. We based our study on a phase locked loop (PLL) used in RF transceivers for frequency synthesis. We used Simulink as block diagram simulator, ADVance MS (ADMS) as behavioral simulator and Eldo as transistor-level simulator. The proposed results show the accuracy and simulation time for each description level.","PeriodicalId":356468,"journal":{"name":"2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114879463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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