Pub Date : 2000-11-13DOI: 10.1109/SMELEC.2000.932444
Y. Hua, S. Redkar, L. An, G. Ang
In this paper, silicon nodules due to Si precipitation were investigated in wafer fabrication. Line inspection found particle contamination on bondpads and large metal 1 lines of some wafers. Cross sectional SEM results showed that some nodules were found in the metal 1 layer. EDX analysis confirmed that they were Si nodules as a high Si peak was detected on the nodules. These nodules had resulted in open failure in some metal lines. Based on the failure analysis results, we concluded that the silicon nodules were due to silicon precipitation. The preventive actions taken were to check the target if the Si value in Al exceeds the normal value, to control the parameter strictly during metal deposition and to reduce the thermal cycles after metal deposition.
{"title":"A study on silicon nodules due to the Si precipitation in wafer fabrication","authors":"Y. Hua, S. Redkar, L. An, G. Ang","doi":"10.1109/SMELEC.2000.932444","DOIUrl":"https://doi.org/10.1109/SMELEC.2000.932444","url":null,"abstract":"In this paper, silicon nodules due to Si precipitation were investigated in wafer fabrication. Line inspection found particle contamination on bondpads and large metal 1 lines of some wafers. Cross sectional SEM results showed that some nodules were found in the metal 1 layer. EDX analysis confirmed that they were Si nodules as a high Si peak was detected on the nodules. These nodules had resulted in open failure in some metal lines. Based on the failure analysis results, we concluded that the silicon nodules were due to silicon precipitation. The preventive actions taken were to check the target if the Si value in Al exceeds the normal value, to control the parameter strictly during metal deposition and to reduce the thermal cycles after metal deposition.","PeriodicalId":359114,"journal":{"name":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123940597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-13DOI: 10.1109/SMELEC.2000.932305
E. C. Low, L. An, Y. Hua, Yogaspari
The poly residue problem in wafer fabrication was investigated in this paper. Surface and cross sectional SEM (scanning electron microscopy) was used to identify the root cause. After poly etching, particle contamination was found at the N-well and field oxide overlap region. Some wafers were scrapped due to this issue. To identify the root cause and solution, some affected wafers were subjected to surface and cross sectional SEM. Surface SEM inspection found the particles at the edge of field oxide. Cross sectional SEM and EDX confirmed that it was poly residue. The residue was due to the high topography at the edge of the field oxide, thus causing higher poly thickness. The difference in height resulted in the vertical thickness of the slope of ONO and poly layers to be thicker than that of the planar layer. During the poly etch process, which was anisotropic, the planar poly could be etched away completely but the poly at the slope might not be etched away as it was thicker than the planar layer. Hence some poly residue was left behind. After investigation, the solutions used are to optimize the poly etching recipe by removing He clamp flow at the break through step, and to increase the isotropic etch and etching time from 80 s to 100 s. The poly residue is then eliminated after implementing the new etch recipe.
{"title":"Failure analysis and elimination of poly residues contamination in wafer fabrication","authors":"E. C. Low, L. An, Y. Hua, Yogaspari","doi":"10.1109/SMELEC.2000.932305","DOIUrl":"https://doi.org/10.1109/SMELEC.2000.932305","url":null,"abstract":"The poly residue problem in wafer fabrication was investigated in this paper. Surface and cross sectional SEM (scanning electron microscopy) was used to identify the root cause. After poly etching, particle contamination was found at the N-well and field oxide overlap region. Some wafers were scrapped due to this issue. To identify the root cause and solution, some affected wafers were subjected to surface and cross sectional SEM. Surface SEM inspection found the particles at the edge of field oxide. Cross sectional SEM and EDX confirmed that it was poly residue. The residue was due to the high topography at the edge of the field oxide, thus causing higher poly thickness. The difference in height resulted in the vertical thickness of the slope of ONO and poly layers to be thicker than that of the planar layer. During the poly etch process, which was anisotropic, the planar poly could be etched away completely but the poly at the slope might not be etched away as it was thicker than the planar layer. Hence some poly residue was left behind. After investigation, the solutions used are to optimize the poly etching recipe by removing He clamp flow at the break through step, and to increase the isotropic etch and etching time from 80 s to 100 s. The poly residue is then eliminated after implementing the new etch recipe.","PeriodicalId":359114,"journal":{"name":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114030897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-13DOI: 10.1109/SMELEC.2000.932445
M. F. Zakaria, B. Majlis
A PHEMT-based MMIC amplifier to be used as a gain block for transmit and receive circuits was designed using Libra series IV CAD based on the GMMT H40 process library. The simulated S-parameters show very good amplifier performance as required by the specification in the frequency band of 1-3 GHz. The input and output return loss are less than -15 dB, gain is 17 dB and noise figure is less than 2.8 dB. After simulation and optimization, the schematic circuit was translated into a layout pattern with a die size of 1.3 mm/spl times/1.4 mm.
{"title":"1-3 GHz MMIC amplifier design for transmit/receive applications","authors":"M. F. Zakaria, B. Majlis","doi":"10.1109/SMELEC.2000.932445","DOIUrl":"https://doi.org/10.1109/SMELEC.2000.932445","url":null,"abstract":"A PHEMT-based MMIC amplifier to be used as a gain block for transmit and receive circuits was designed using Libra series IV CAD based on the GMMT H40 process library. The simulated S-parameters show very good amplifier performance as required by the specification in the frequency band of 1-3 GHz. The input and output return loss are less than -15 dB, gain is 17 dB and noise figure is less than 2.8 dB. After simulation and optimization, the schematic circuit was translated into a layout pattern with a die size of 1.3 mm/spl times/1.4 mm.","PeriodicalId":359114,"journal":{"name":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114739236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-13DOI: 10.1109/SMELEC.2000.932326
Y. Hua, S. Redkar, L. An, G. Ang
In this paper, a case of bondpad peeling was investigated. EDX (energy-dispersive X-ray microanalysis) and AES (Auger electron spectroscopy) techniques were used to identify the possible root cause. Based on EDX and AES results, it is concluded that the bondpad peeling problem was due to significant carbon contamination on the peeled area of the bondpad, which might contribute to the bondpad peeling problem. EDX and AES results also confirmed the peeling occurred between the barrier metal and BPSG layers. The high C contamination had resulted in poor adhesion between the barrier metal and BPSG layers and resulted in the peeling problem. The high C contamination on the BPSG layer was introduced during the wafer fab process. It may be due to incomplete contact process resist strip or insufficient pre-clean before barrier metal deposition. In this paper, we also discuss the difference between EDX and AES analysis techniques and use the contamination diagram introduced by us.
{"title":"Auger electron spectroscopy studies on bondpad peeling failure in wafer fabrication","authors":"Y. Hua, S. Redkar, L. An, G. Ang","doi":"10.1109/SMELEC.2000.932326","DOIUrl":"https://doi.org/10.1109/SMELEC.2000.932326","url":null,"abstract":"In this paper, a case of bondpad peeling was investigated. EDX (energy-dispersive X-ray microanalysis) and AES (Auger electron spectroscopy) techniques were used to identify the possible root cause. Based on EDX and AES results, it is concluded that the bondpad peeling problem was due to significant carbon contamination on the peeled area of the bondpad, which might contribute to the bondpad peeling problem. EDX and AES results also confirmed the peeling occurred between the barrier metal and BPSG layers. The high C contamination had resulted in poor adhesion between the barrier metal and BPSG layers and resulted in the peeling problem. The high C contamination on the BPSG layer was introduced during the wafer fab process. It may be due to incomplete contact process resist strip or insufficient pre-clean before barrier metal deposition. In this paper, we also discuss the difference between EDX and AES analysis techniques and use the contamination diagram introduced by us.","PeriodicalId":359114,"journal":{"name":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132107641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-13DOI: 10.1109/SMELEC.2000.932451
I. Ahmad, N. B. Sulaiman
In this paper, the scenario of the microelectronics industry in Malaysia is described. The government's policies, infrastructure, and government-industry partnership program, as well incentives provided by the government to nourish the industry were also discussed. A special wafer fabrication task force has been formed to ensure the success of this strategic project.
{"title":"Review on policies, research & development in microelectronics industry in Malaysia","authors":"I. Ahmad, N. B. Sulaiman","doi":"10.1109/SMELEC.2000.932451","DOIUrl":"https://doi.org/10.1109/SMELEC.2000.932451","url":null,"abstract":"In this paper, the scenario of the microelectronics industry in Malaysia is described. The government's policies, infrastructure, and government-industry partnership program, as well incentives provided by the government to nourish the industry were also discussed. A special wafer fabrication task force has been formed to ensure the success of this strategic project.","PeriodicalId":359114,"journal":{"name":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115377211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-13DOI: 10.1109/SMELEC.2000.932468
A. Ehsan, S. Shaari, B. Y. Majlis
The work presented here shows the effects of RF power of an RIE system on silicon etching. A p-type silicon [100] wafer is etched under four RF power levels, which are 40, 60, 80 and 100 W. The etch depth plotted shows a linear increase with RF power for a fixed etch time at low RF power. However, the etch depth shows a tendency to saturate at a higher RF power level. The behaviour is believed to be caused by the existence of a sheath layer when plasma is generated in the process chamber.
{"title":"The saturation effect of etch depth at high RF power in CF/sub 4/ plasma RIE silicon etching","authors":"A. Ehsan, S. Shaari, B. Y. Majlis","doi":"10.1109/SMELEC.2000.932468","DOIUrl":"https://doi.org/10.1109/SMELEC.2000.932468","url":null,"abstract":"The work presented here shows the effects of RF power of an RIE system on silicon etching. A p-type silicon [100] wafer is etched under four RF power levels, which are 40, 60, 80 and 100 W. The etch depth plotted shows a linear increase with RF power for a fixed etch time at low RF power. However, the etch depth shows a tendency to saturate at a higher RF power level. The behaviour is believed to be caused by the existence of a sheath layer when plasma is generated in the process chamber.","PeriodicalId":359114,"journal":{"name":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114726369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-13DOI: 10.1109/SMELEC.2000.932463
A. Mat, H. Musa, B. Y. Majlis
The structural differences between thermally grown SiO/sub 2/ prepared using three different gas mixtures was studied using infrared measurements, refractive index measurements and selective etching techniques. The data shows that the highest degree of porosity is found in materials grown in an ammonia atmosphere.
{"title":"Structural characteristics of thermally grown SiO/sub 2/ prepared by a home made furnace","authors":"A. Mat, H. Musa, B. Y. Majlis","doi":"10.1109/SMELEC.2000.932463","DOIUrl":"https://doi.org/10.1109/SMELEC.2000.932463","url":null,"abstract":"The structural differences between thermally grown SiO/sub 2/ prepared using three different gas mixtures was studied using infrared measurements, refractive index measurements and selective etching techniques. The data shows that the highest degree of porosity is found in materials grown in an ammonia atmosphere.","PeriodicalId":359114,"journal":{"name":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128155832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-13DOI: 10.1109/SMELEC.2000.932449
A. Daud, T. Kunimoto, R. Yoshimatsu, K. Ohmi, S. Tanaka, H. Kobayashi
CaMgSi/sub 2/O/sub 6/:Eu (CMS:Eu) powder phosphors showing blue and red emissions were examined for vacuum UV (VUV) excitation applications. Nearly single phased CMS powder phosphors with either Eu/sup 2+/ or Eu/sup 3+/ activator can be synthesized using EuF/sub 3/ or Eu/sub 2/O/sub 3/ as source material, respectively. Under VUV excitation, the PL spectra show a good blue emission from Eu/sup 2+/ and a good red emission from Eu/sup 3+/ in the CMS host. At present, the PL intensity of CMS:Eu/sup 2+/ under 147 nm excitation is about 50 % that of BAM:Eu/sup 2+/.
{"title":"Blue and red emitting Eu activated CaMgSi/sub 2/O/sub 6/ VUV phosphors","authors":"A. Daud, T. Kunimoto, R. Yoshimatsu, K. Ohmi, S. Tanaka, H. Kobayashi","doi":"10.1109/SMELEC.2000.932449","DOIUrl":"https://doi.org/10.1109/SMELEC.2000.932449","url":null,"abstract":"CaMgSi/sub 2/O/sub 6/:Eu (CMS:Eu) powder phosphors showing blue and red emissions were examined for vacuum UV (VUV) excitation applications. Nearly single phased CMS powder phosphors with either Eu/sup 2+/ or Eu/sup 3+/ activator can be synthesized using EuF/sub 3/ or Eu/sub 2/O/sub 3/ as source material, respectively. Under VUV excitation, the PL spectra show a good blue emission from Eu/sup 2+/ and a good red emission from Eu/sup 3+/ in the CMS host. At present, the PL intensity of CMS:Eu/sup 2+/ under 147 nm excitation is about 50 % that of BAM:Eu/sup 2+/.","PeriodicalId":359114,"journal":{"name":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127129308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-13DOI: 10.1109/SMELEC.2000.932473
S. Shaari, Swee Leong Kok, O. Siah
An optical network device that is formed by three cascaded directional couplers is discussed in this paper. Wavelengths of 1535.04 nm, 1545.32 nm, 1555.75 nm and 1565.50 nm from ITU channels are the input signal sources that are used to study propagation in the designed device. The output results of these wavelengths through this optical network device are analyzed with the help of a BPM CAD simulator. The results of the analysis include insertion loss, crosstalk and bandwidth. For real device design and fabrication, the bending loss of this introduced optical network device is also discussed.
{"title":"Design and characteristics of four-channel 1200 GHz spacing 1550 nm WDM device using cascaded directional couplers","authors":"S. Shaari, Swee Leong Kok, O. Siah","doi":"10.1109/SMELEC.2000.932473","DOIUrl":"https://doi.org/10.1109/SMELEC.2000.932473","url":null,"abstract":"An optical network device that is formed by three cascaded directional couplers is discussed in this paper. Wavelengths of 1535.04 nm, 1545.32 nm, 1555.75 nm and 1565.50 nm from ITU channels are the input signal sources that are used to study propagation in the designed device. The output results of these wavelengths through this optical network device are analyzed with the help of a BPM CAD simulator. The results of the analysis include insertion loss, crosstalk and bandwidth. For real device design and fabrication, the bending loss of this introduced optical network device is also discussed.","PeriodicalId":359114,"journal":{"name":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130132681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-13DOI: 10.1109/SMELEC.2000.932446
A.F.A. Rahim, A.F.A. Rahim, M. R. Hashim, S.A.M. Saari, M. Ahmad, M. Wahab, W.S.W. Adini, M. I. Syono
Bipolar transistors are well known for their high current driving capability and current gains, while CMOS transistors are dominant in the integrated circuit market because of their low power consumption and small size advantage. The combination of both types of transistor on the same chip provides a high performance circuit with a high packing density. In this work, 0.5 /spl mu/m BiCMOS technology is fully utilized to realize silicon bipolar transistors with optimized performance. Preliminary electrical results are presented on bipolar transistors fabricated for the first time in Malaysia. Significant improvements in electrical device performance can be achieved by optimizing the emitter drive-in temperature and choice of annealing system.
{"title":"Fabrication and electrical characterization of silicon bipolar transistors in a 0.5-/spl mu/m based BiCMOS technology","authors":"A.F.A. Rahim, A.F.A. Rahim, M. R. Hashim, S.A.M. Saari, M. Ahmad, M. Wahab, W.S.W. Adini, M. I. Syono","doi":"10.1109/SMELEC.2000.932446","DOIUrl":"https://doi.org/10.1109/SMELEC.2000.932446","url":null,"abstract":"Bipolar transistors are well known for their high current driving capability and current gains, while CMOS transistors are dominant in the integrated circuit market because of their low power consumption and small size advantage. The combination of both types of transistor on the same chip provides a high performance circuit with a high packing density. In this work, 0.5 /spl mu/m BiCMOS technology is fully utilized to realize silicon bipolar transistors with optimized performance. Preliminary electrical results are presented on bipolar transistors fabricated for the first time in Malaysia. Significant improvements in electrical device performance can be achieved by optimizing the emitter drive-in temperature and choice of annealing system.","PeriodicalId":359114,"journal":{"name":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132154895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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