Pub Date : 2000-11-13DOI: 10.1109/SMELEC.2000.932472
Jasruddin, W. W. Wenas, T. Winata, M. Barmawi
The growth of hydrogenated amorphous silicon (a-Si:H) and hydrogenated amorphous silicon nitride (a-SiN:H) films was studied by plasma enhanced chemical vapor deposition (PECVD) method. 10% silane (SiH/sub 4/) diluted in hydrogen (H/sub 2/) gas and 100% ammonia (NH/sub 3/) gas were used as gas sources. The optical band-gap and deposition rate of a-Si:H film were found to vary from 1.70 to 1.95 eV and 51 to 84 /spl Aring//min, respectively, when the SiH/sub 4/ gas flow rate varied from 5 to 11 sccm. The widest optical bandgap of a-SiN:H films of 3.69 eV and lowest dark conductivity of 1.07/spl times/10/sup -11/ Scm/sup -1/ were obtained at NH/sub 3/ gas fraction of 60% at SiH/sub 4/ flow rate of 7 sccm. It is also shown that a wider optical bandgap for a-SiN:H can be obtained at a SiH/sub 4/ gas flow rate of 5 sccm, where its value reaches 3.97 eV at NH/sub 3/ gas fraction of 25%, whilst its dark conductivity reaches a lower value of 1.05/spl times/10/sup -12/ Scm/sup -1/. The application of the films as a gate insulator in the thin film transistor (TFT) device was also studied. The lowest dark conductivity of the a-SiN:H film resulted in a better device threshold voltage.
{"title":"Growth study of wide bandgap a-Si:H and a-SiN:H by PECVD method for application in thin film transistor","authors":"Jasruddin, W. W. Wenas, T. Winata, M. Barmawi","doi":"10.1109/SMELEC.2000.932472","DOIUrl":"https://doi.org/10.1109/SMELEC.2000.932472","url":null,"abstract":"The growth of hydrogenated amorphous silicon (a-Si:H) and hydrogenated amorphous silicon nitride (a-SiN:H) films was studied by plasma enhanced chemical vapor deposition (PECVD) method. 10% silane (SiH/sub 4/) diluted in hydrogen (H/sub 2/) gas and 100% ammonia (NH/sub 3/) gas were used as gas sources. The optical band-gap and deposition rate of a-Si:H film were found to vary from 1.70 to 1.95 eV and 51 to 84 /spl Aring//min, respectively, when the SiH/sub 4/ gas flow rate varied from 5 to 11 sccm. The widest optical bandgap of a-SiN:H films of 3.69 eV and lowest dark conductivity of 1.07/spl times/10/sup -11/ Scm/sup -1/ were obtained at NH/sub 3/ gas fraction of 60% at SiH/sub 4/ flow rate of 7 sccm. It is also shown that a wider optical bandgap for a-SiN:H can be obtained at a SiH/sub 4/ gas flow rate of 5 sccm, where its value reaches 3.97 eV at NH/sub 3/ gas fraction of 25%, whilst its dark conductivity reaches a lower value of 1.05/spl times/10/sup -12/ Scm/sup -1/. The application of the films as a gate insulator in the thin film transistor (TFT) device was also studied. The lowest dark conductivity of the a-SiN:H film resulted in a better device threshold voltage.","PeriodicalId":359114,"journal":{"name":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115588975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-13DOI: 10.1109/SMELEC.2000.932456
L. Lee, B.S. Suparjo, R. Wagiran, R. Sidek
Programmable digital signal processors (pDSPs) are microprocessors that are specialized to perform well in digital signal processing intensive applications. A standard microprocessor can do most pDSP operations. However, the pDSP chip has better ability to perform number crunching algorithms in real-time, and pDSPs are highly flexible because they can be reprogrammed. The major objective of this research is to design and implement a general-purpose programmable DSP core (digital signal processor core). The architecture of the pDSP core must be designed in such a way that parallel processing can be exploited and computational units can be integrated into the core with ease. The pDSP designed is a fixed-point DSP based on a very long instruction word (VLIW) architecture. One way to overcome the performance limitation is to use field programmable gate array (FPGA) technology, a technology which gives the designer a higher degree of parallelism and ease of pDSP design.
{"title":"DSP design using VLIW architecture","authors":"L. Lee, B.S. Suparjo, R. Wagiran, R. Sidek","doi":"10.1109/SMELEC.2000.932456","DOIUrl":"https://doi.org/10.1109/SMELEC.2000.932456","url":null,"abstract":"Programmable digital signal processors (pDSPs) are microprocessors that are specialized to perform well in digital signal processing intensive applications. A standard microprocessor can do most pDSP operations. However, the pDSP chip has better ability to perform number crunching algorithms in real-time, and pDSPs are highly flexible because they can be reprogrammed. The major objective of this research is to design and implement a general-purpose programmable DSP core (digital signal processor core). The architecture of the pDSP core must be designed in such a way that parallel processing can be exploited and computational units can be integrated into the core with ease. The pDSP designed is a fixed-point DSP based on a very long instruction word (VLIW) architecture. One way to overcome the performance limitation is to use field programmable gate array (FPGA) technology, a technology which gives the designer a higher degree of parallelism and ease of pDSP design.","PeriodicalId":359114,"journal":{"name":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","volume":"192 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128609166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-13DOI: 10.1109/SMELEC.2000.932469
G. Tan, B. S. Surparjo, R. Wagiran, R. Sidek
This paper describes a high-speed current switching CMOS digital analog converter (DAC) circuit that achieves 8-bit resolution, low differential nonlinearity (DNL), 20M samples per second conversion rate, low glitch energy and 5 V power supply voltage by using the MOSIS SCNA20 2 /spl mu/m process. The converter is based on current division by using a segmentation technique. The current switching is used instead of voltage switching because current can be switched in and out of a circuit faster than voltage. The developed DAC employs two internal DACs. Each internal DAC has its own advantages. This DAC used thermometer code for three bit MSBs and R2R ladder for 5 bit LSBs.
{"title":"The design of 8-bit CMOS digital to analog converter","authors":"G. Tan, B. S. Surparjo, R. Wagiran, R. Sidek","doi":"10.1109/SMELEC.2000.932469","DOIUrl":"https://doi.org/10.1109/SMELEC.2000.932469","url":null,"abstract":"This paper describes a high-speed current switching CMOS digital analog converter (DAC) circuit that achieves 8-bit resolution, low differential nonlinearity (DNL), 20M samples per second conversion rate, low glitch energy and 5 V power supply voltage by using the MOSIS SCNA20 2 /spl mu/m process. The converter is based on current division by using a segmentation technique. The current switching is used instead of voltage switching because current can be switched in and out of a circuit faster than voltage. The developed DAC employs two internal DACs. Each internal DAC has its own advantages. This DAC used thermometer code for three bit MSBs and R2R ladder for 5 bit LSBs.","PeriodicalId":359114,"journal":{"name":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126774454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-13DOI: 10.1109/SMELEC.2000.932474
S. A. Halim, S. Koh, S. P. Chow, H. Zainuddin, K. Lim, O.S. Yu, K. K. Kabashi
The transport properties of La/sub 0.67/Ca/sub 0.33/Mn/sub 1-x/Zr/sub x/O/sub 3/ ceramics exhibit the transition of semiconducting to metallic conductivity at T/sub P/ and the magnetic properties observed in the /spl chi/-temperature curves show transition from paramagnetic to ferromagnetic at T/sub C/. The coexistence of T/sub C/ and T/sub P/ are due to the double exchange interaction of two electrons in Mn/sup 3+/-O/sup 2-/-Mn/sup 4+/ and Mn/sup 4+/-O/sup 2-/-Mn/sup 3+/ configuration which brings the system below T/sub C/ into a metallic state. Hence it is observed that the Curie temperature T/sub C/ is closely related to the sharp decrease in the electrical resistivity of the samples. However, both transition temperatures shift to lower temperatures as zirconium doping increases, indicating the loss of ferromagnetic order and transport properties. As for the transport properties, the semiconductor model ln(/spl sigma/)/spl sim/(E/sub a//kT) was used to explain the conduction mechanism of perovskite manganites above T/sub P/. It was concluded that the total conductivity, /spl sigma//sub tot/, consists of the intrinsic and the extrinsic components, such that /spl sigma//sub tot/=/spl sigma//sub int/+/spl sigma//sub ext/. The activation energy increases initially from 0.056 eV to a maximum value of 0.082 eV at x=0.01 and decreases to 0.022 eV at a composition of x=0.20 for the extrinsic region.
{"title":"Effect of Zr doping on the semiconducting properties of La/sub 0.67/Ca/sub 0.33/MnO/sub 3/ ceramics","authors":"S. A. Halim, S. Koh, S. P. Chow, H. Zainuddin, K. Lim, O.S. Yu, K. K. Kabashi","doi":"10.1109/SMELEC.2000.932474","DOIUrl":"https://doi.org/10.1109/SMELEC.2000.932474","url":null,"abstract":"The transport properties of La/sub 0.67/Ca/sub 0.33/Mn/sub 1-x/Zr/sub x/O/sub 3/ ceramics exhibit the transition of semiconducting to metallic conductivity at T/sub P/ and the magnetic properties observed in the /spl chi/-temperature curves show transition from paramagnetic to ferromagnetic at T/sub C/. The coexistence of T/sub C/ and T/sub P/ are due to the double exchange interaction of two electrons in Mn/sup 3+/-O/sup 2-/-Mn/sup 4+/ and Mn/sup 4+/-O/sup 2-/-Mn/sup 3+/ configuration which brings the system below T/sub C/ into a metallic state. Hence it is observed that the Curie temperature T/sub C/ is closely related to the sharp decrease in the electrical resistivity of the samples. However, both transition temperatures shift to lower temperatures as zirconium doping increases, indicating the loss of ferromagnetic order and transport properties. As for the transport properties, the semiconductor model ln(/spl sigma/)/spl sim/(E/sub a//kT) was used to explain the conduction mechanism of perovskite manganites above T/sub P/. It was concluded that the total conductivity, /spl sigma//sub tot/, consists of the intrinsic and the extrinsic components, such that /spl sigma//sub tot/=/spl sigma//sub int/+/spl sigma//sub ext/. The activation energy increases initially from 0.056 eV to a maximum value of 0.082 eV at x=0.01 and decreases to 0.022 eV at a composition of x=0.20 for the extrinsic region.","PeriodicalId":359114,"journal":{"name":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127092352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-13DOI: 10.1109/SMELEC.2000.932441
A. Omar, I. Ahmad, A. Alias
The effect of phosphorus, doped in-situ and by ion implantation on polysilicon, as a gate electrode of 0.5 /spl mu/m CMOS was investigated. The result shows that two-step annealing is required to cure the radiation damage and activate the dopant in reducing the sheet resistance of the ion implanted gate electrode. The introduction of phosphorus from 7/spl times/10/sup 15/ to 3/spl times/10/sup 16//cm/sup 3/ by ion implantation at 40 keV has reduced the sheet resistance from 100 /spl Omega///spl square/ to 25 /spl Omega///spl square/, comparable to the gate produced by in-situ phosphorus doping. The polysilicon gate electrode microstructures were studied using TEM, and it was found that grains of samples in in-situ doped polysilicon are larger than in other samples.
{"title":"Electrical and microstructures properties of polygate electrode in 0.5 /spl mu/m CMOS devices","authors":"A. Omar, I. Ahmad, A. Alias","doi":"10.1109/SMELEC.2000.932441","DOIUrl":"https://doi.org/10.1109/SMELEC.2000.932441","url":null,"abstract":"The effect of phosphorus, doped in-situ and by ion implantation on polysilicon, as a gate electrode of 0.5 /spl mu/m CMOS was investigated. The result shows that two-step annealing is required to cure the radiation damage and activate the dopant in reducing the sheet resistance of the ion implanted gate electrode. The introduction of phosphorus from 7/spl times/10/sup 15/ to 3/spl times/10/sup 16//cm/sup 3/ by ion implantation at 40 keV has reduced the sheet resistance from 100 /spl Omega///spl square/ to 25 /spl Omega///spl square/, comparable to the gate produced by in-situ phosphorus doping. The polysilicon gate electrode microstructures were studied using TEM, and it was found that grains of samples in in-situ doped polysilicon are larger than in other samples.","PeriodicalId":359114,"journal":{"name":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128311992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-13DOI: 10.1109/SMELEC.2000.932302
C. H. Tan, J. David, G. Rees, R. C. Tozer, K.F. Li
Avalanche photodiodes with thin avalanche multiplication regions were found to exhibit lower excess noise than those predicted by the conventional local noise theory. Experimental excess noise measurements on a range of sub-micron Al/sub 0.6/Ga/sub 0.4/As and Al/sub 0.15/Ga/sub 0.85/As homojunction p/sup +/in/sup +/ diodes show that the excess noise decreases as the avalanche width is reduced below 1 /spl mu/m. The Al/sub 0.6/Ga/sub 0.4/As p/sup +/in/sup +/ diodes show extremely low excess noise despite the electron and hole ionization coefficients being very similar. Modelling using a nonlocal model indicates that dead space plays an important role in determining the excess noise in thin avalanching regions.
{"title":"Low avalanche excess noise in thin Al/sub x/Ga/sub 1-x/As (x=0.15 and 0.60) avalanche photodiodes","authors":"C. H. Tan, J. David, G. Rees, R. C. Tozer, K.F. Li","doi":"10.1109/SMELEC.2000.932302","DOIUrl":"https://doi.org/10.1109/SMELEC.2000.932302","url":null,"abstract":"Avalanche photodiodes with thin avalanche multiplication regions were found to exhibit lower excess noise than those predicted by the conventional local noise theory. Experimental excess noise measurements on a range of sub-micron Al/sub 0.6/Ga/sub 0.4/As and Al/sub 0.15/Ga/sub 0.85/As homojunction p/sup +/in/sup +/ diodes show that the excess noise decreases as the avalanche width is reduced below 1 /spl mu/m. The Al/sub 0.6/Ga/sub 0.4/As p/sup +/in/sup +/ diodes show extremely low excess noise despite the electron and hole ionization coefficients being very similar. Modelling using a nonlocal model indicates that dead space plays an important role in determining the excess noise in thin avalanching regions.","PeriodicalId":359114,"journal":{"name":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128523740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-13DOI: 10.1109/SMELEC.2000.932461
N. Sulaiman, P. Ashburn
Vertical MOSFETs are a promising approach for ultra short channel length transistors. Theoretically, vertical MOSFETs have small lateral size due to their three-dimensional geometry channel compared to the three-dimensional type of conventional MOSFETs. Thus, vertical transistors are very attractive for high density integrated circuits (ICs). The feasibility study concentrates on the layouts of conventional and vertical CMOS for inverter and two-input NOR gates to validate the theory. In this study, the size of the active area and the overall area for gates designed using both types of transistor were compared and analyzed. Based on the comparison, the size of the active area for the gates designed using both types of transistors were equal. However, the overall area of the gates designed using vertical MOSFETs were larger than that of conventional MOSFETs due to the limitation of interconnection of metal between the transistors. Based on the study, although the channel size can be optimized, due to the interconnection requirement in IC implementation, the overall IC area cannot be minimized.
{"title":"Feasibility study on vertical CMOS gates","authors":"N. Sulaiman, P. Ashburn","doi":"10.1109/SMELEC.2000.932461","DOIUrl":"https://doi.org/10.1109/SMELEC.2000.932461","url":null,"abstract":"Vertical MOSFETs are a promising approach for ultra short channel length transistors. Theoretically, vertical MOSFETs have small lateral size due to their three-dimensional geometry channel compared to the three-dimensional type of conventional MOSFETs. Thus, vertical transistors are very attractive for high density integrated circuits (ICs). The feasibility study concentrates on the layouts of conventional and vertical CMOS for inverter and two-input NOR gates to validate the theory. In this study, the size of the active area and the overall area for gates designed using both types of transistor were compared and analyzed. Based on the comparison, the size of the active area for the gates designed using both types of transistors were equal. However, the overall area of the gates designed using vertical MOSFETs were larger than that of conventional MOSFETs due to the limitation of interconnection of metal between the transistors. Based on the study, although the channel size can be optimized, due to the interconnection requirement in IC implementation, the overall IC area cannot be minimized.","PeriodicalId":359114,"journal":{"name":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129582541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-13DOI: 10.1109/SMELEC.2000.932300
W. Chaisirithavornkul, V. Kasemsuwan
A physical DC model for short channel MOSFET is presented. The model accounts for several second order effects including the vertical and horizontal mobility degradations, velocity saturation, and the channel length modulation. Accurate electric widths at the saturation point and the drain field around the drain end is obtained through the quasi two dimensional approximation (QTDA) using Gaussian surface with trapezoidal shape. The theoretical predictions of the model show good agreement with experimental data available in the literature over a wide range of biasing conditions.
{"title":"A physical DC model of short channel MOS transistor using trapezoidal Gaussian surface","authors":"W. Chaisirithavornkul, V. Kasemsuwan","doi":"10.1109/SMELEC.2000.932300","DOIUrl":"https://doi.org/10.1109/SMELEC.2000.932300","url":null,"abstract":"A physical DC model for short channel MOSFET is presented. The model accounts for several second order effects including the vertical and horizontal mobility degradations, velocity saturation, and the channel length modulation. Accurate electric widths at the saturation point and the drain field around the drain end is obtained through the quasi two dimensional approximation (QTDA) using Gaussian surface with trapezoidal shape. The theoretical predictions of the model show good agreement with experimental data available in the literature over a wide range of biasing conditions.","PeriodicalId":359114,"journal":{"name":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133398895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-13DOI: 10.1109/SMELEC.2000.932460
A. Andreev, J. Ngarmnil, K. Nandhasri
The paper presents a mathematical model applicable both for calculation of the 3D magnetic field outside a rectangular coil and demagnetization and stray field of a rectangular saturated ferromagnetic prism. An infinite thin surface current with surface density j (A/cm) has been used to model the coil block. Different mathematical models for analysis of the magnetic microelectronic components are discussed. Results of the calculation are presented.
{"title":"Universal method for the calculation of magnetic microelectronic components: the saturated ferromagnetic rectangular prism and the rectangular coil","authors":"A. Andreev, J. Ngarmnil, K. Nandhasri","doi":"10.1109/SMELEC.2000.932460","DOIUrl":"https://doi.org/10.1109/SMELEC.2000.932460","url":null,"abstract":"The paper presents a mathematical model applicable both for calculation of the 3D magnetic field outside a rectangular coil and demagnetization and stray field of a rectangular saturated ferromagnetic prism. An infinite thin surface current with surface density j (A/cm) has been used to model the coil block. Different mathematical models for analysis of the magnetic microelectronic components are discussed. Results of the calculation are presented.","PeriodicalId":359114,"journal":{"name":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127010095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-13DOI: 10.1109/SMELEC.2000.932462
K. Lai, P. Lim, W. Chim, Yang Pan
Process variation in the buffered oxide etch (BOE) duration during tunnel window formation can cause floating-gate tunnel-oxide (FLOTOX) electrically erasable and programmable read-only memory (EEPROM) devices to exhibit enhanced window closure effect during write/erase endurance tests. Electrical and physical characterisation of devices with insufficient BOE duration indicated the presence of a poor quality or "crabby" oxide region (exhibiting enhanced electron trapping) remaining after tunnel window formation before tunnel oxide growth.
{"title":"Process variation during tunnel window formation and its impact on the reliability performance of FLOTOX EEPROM devices","authors":"K. Lai, P. Lim, W. Chim, Yang Pan","doi":"10.1109/SMELEC.2000.932462","DOIUrl":"https://doi.org/10.1109/SMELEC.2000.932462","url":null,"abstract":"Process variation in the buffered oxide etch (BOE) duration during tunnel window formation can cause floating-gate tunnel-oxide (FLOTOX) electrically erasable and programmable read-only memory (EEPROM) devices to exhibit enhanced window closure effect during write/erase endurance tests. Electrical and physical characterisation of devices with insufficient BOE duration indicated the presence of a poor quality or \"crabby\" oxide region (exhibiting enhanced electron trapping) remaining after tunnel window formation before tunnel oxide growth.","PeriodicalId":359114,"journal":{"name":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125533134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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