Pub Date : 2000-11-13DOI: 10.1109/SMELEC.2000.932298
H. Iwai, S. Ohmi
Progress of MOS LSI has been achieved by continuous downsizing of its components. However, the downsizing of CMOS devices is now facing severe difficulties at the 0.1 /spl mu/m generation because of various expected limitations. In order to overcome the problems, introduction of new materials and device structures are investigated. This paper explains the difficulties of downsizing CMOS devices below 0.1 /spl mu/m, and then, future CMOS technologies for new materials, processes and structures which are expected to solve the problems.
{"title":"Problems and solutions for downsizing CMOS below 0.1 /spl mu/m","authors":"H. Iwai, S. Ohmi","doi":"10.1109/SMELEC.2000.932298","DOIUrl":"https://doi.org/10.1109/SMELEC.2000.932298","url":null,"abstract":"Progress of MOS LSI has been achieved by continuous downsizing of its components. However, the downsizing of CMOS devices is now facing severe difficulties at the 0.1 /spl mu/m generation because of various expected limitations. In order to overcome the problems, introduction of new materials and device structures are investigated. This paper explains the difficulties of downsizing CMOS devices below 0.1 /spl mu/m, and then, future CMOS technologies for new materials, processes and structures which are expected to solve the problems.","PeriodicalId":359114,"journal":{"name":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115035884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-13DOI: 10.1109/SMELEC.2000.932304
M. Hussin, S.A.M. Saari, A.F.A. Rahim, R. Ayub, M. Ahmad
Short channel devices suffer from punchthrough leakage due to barrier lowering induced by drain bias (DIBL). The device engineering strategy aims at reducing leakage from surface, sub-surface and bulk current paths. In deep sub-micron devices, bulk punchthrough is the major contributor to the DIBL leakage. This paper describes process optimization that requires some trade-offs between device parameters such as off-state current leakage, drive current and threshold voltage, to meet technology specifications. In this work we optimize well, channel, pocket and drain implant and anneal parameters to achieve the desired device characteristics.
{"title":"Blanket and pocket anti punchthrough device design approaches in 0.35-/spl mu/m CMOS technology development","authors":"M. Hussin, S.A.M. Saari, A.F.A. Rahim, R. Ayub, M. Ahmad","doi":"10.1109/SMELEC.2000.932304","DOIUrl":"https://doi.org/10.1109/SMELEC.2000.932304","url":null,"abstract":"Short channel devices suffer from punchthrough leakage due to barrier lowering induced by drain bias (DIBL). The device engineering strategy aims at reducing leakage from surface, sub-surface and bulk current paths. In deep sub-micron devices, bulk punchthrough is the major contributor to the DIBL leakage. This paper describes process optimization that requires some trade-offs between device parameters such as off-state current leakage, drive current and threshold voltage, to meet technology specifications. In this work we optimize well, channel, pocket and drain implant and anneal parameters to achieve the desired device characteristics.","PeriodicalId":359114,"journal":{"name":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130764554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-13DOI: 10.1109/SMELEC.2000.932467
W.B. Puah, B. Suparjo, R. Wagiran, R. Sidek
Asynchronous processors are an attractive research field, since they offer many advantages over synchronous processors. Field-programmable gate arrays (FPGA), one of the dominant media at present for prototyping and implementing digital circuits, is used to construct an 8-bit asynchronous RISC processor. The asynchronous processor employs the conceptual framework of a Sutherland micropipeline, a modular approach to design of asynchronous circuits.
{"title":"Rapid prototyping asynchronous processor","authors":"W.B. Puah, B. Suparjo, R. Wagiran, R. Sidek","doi":"10.1109/SMELEC.2000.932467","DOIUrl":"https://doi.org/10.1109/SMELEC.2000.932467","url":null,"abstract":"Asynchronous processors are an attractive research field, since they offer many advantages over synchronous processors. Field-programmable gate arrays (FPGA), one of the dominant media at present for prototyping and implementing digital circuits, is used to construct an 8-bit asynchronous RISC processor. The asynchronous processor employs the conceptual framework of a Sutherland micropipeline, a modular approach to design of asynchronous circuits.","PeriodicalId":359114,"journal":{"name":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133104483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-13DOI: 10.1109/SMELEC.2000.932327
Mursyidah, M. Salleh, M. Yahaya, R. Daik, H. Ooi
Polymer based light emitting diodes (LED) are potentially useful in display technology. The basic structure of this device consists of a hole transport layer (p-type) and an electron transport layer (n-type). This paper reports a study on poly(4,4'-diphenylene diphenylvinylene) (PDPV) thin films for a hole transport layer in the device. The multilayer PDPV films were deposited on glass and ITO-covered glass substrates using the Langmuir Blodgett (LB) technique. Aluminum was deposited on the PDPV film as an electron injector and also as the electrode. The film was characterized by measuring the electrical properties, optical absorption and topography image. The sheet resistance of the PDPV film deposited on glass was (6.3/spl plusmn/0.1)/spl times/10/sup 8/ /spl Omega/ per square and the energy gap of the film was 2.95/spl plusmn/0.01 eV. The performances of the devices with ITO/PDPV/Al structure were studied through the current-voltage curves measured in the dark. It was found that the device showed typical diode properties.
{"title":"Poly(4,4'-diphenylene diphenylvinylene) Langmuir Blodgett thin films as a hole transport layer in polymer light emitting diode","authors":"Mursyidah, M. Salleh, M. Yahaya, R. Daik, H. Ooi","doi":"10.1109/SMELEC.2000.932327","DOIUrl":"https://doi.org/10.1109/SMELEC.2000.932327","url":null,"abstract":"Polymer based light emitting diodes (LED) are potentially useful in display technology. The basic structure of this device consists of a hole transport layer (p-type) and an electron transport layer (n-type). This paper reports a study on poly(4,4'-diphenylene diphenylvinylene) (PDPV) thin films for a hole transport layer in the device. The multilayer PDPV films were deposited on glass and ITO-covered glass substrates using the Langmuir Blodgett (LB) technique. Aluminum was deposited on the PDPV film as an electron injector and also as the electrode. The film was characterized by measuring the electrical properties, optical absorption and topography image. The sheet resistance of the PDPV film deposited on glass was (6.3/spl plusmn/0.1)/spl times/10/sup 8/ /spl Omega/ per square and the energy gap of the film was 2.95/spl plusmn/0.01 eV. The performances of the devices with ITO/PDPV/Al structure were studied through the current-voltage curves measured in the dark. It was found that the device showed typical diode properties.","PeriodicalId":359114,"journal":{"name":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","volume":"311 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133240544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-13DOI: 10.1109/SMELEC.2000.932442
J. Ngarmnil, W. Sangnak
At present, most CMOS technologies are based on the use of BSIM3v3 MOSFET model, which has been intensively developed to meet the requirements for optimum accuracy. This results in a very accurate and complex MOSFET model, which affects designers, especially when performing hand calculations during the analysis and synthesis process. This paper presents an essential concept of BSIM3v3 key parameter extraction for efficient CMOS circuit design. Key parameter extractions from various CMOS SPICE parameter files are presented. Design examples on HSPICE are given to demonstrate the performance of the methodology.
{"title":"BSIM3v3 key parameter extractions for efficient circuit designs","authors":"J. Ngarmnil, W. Sangnak","doi":"10.1109/SMELEC.2000.932442","DOIUrl":"https://doi.org/10.1109/SMELEC.2000.932442","url":null,"abstract":"At present, most CMOS technologies are based on the use of BSIM3v3 MOSFET model, which has been intensively developed to meet the requirements for optimum accuracy. This results in a very accurate and complex MOSFET model, which affects designers, especially when performing hand calculations during the analysis and synthesis process. This paper presents an essential concept of BSIM3v3 key parameter extraction for efficient CMOS circuit design. Key parameter extractions from various CMOS SPICE parameter files are presented. Design examples on HSPICE are given to demonstrate the performance of the methodology.","PeriodicalId":359114,"journal":{"name":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","volume":"169 1-4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126018538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-13DOI: 10.1109/SMELEC.2000.932457
A. You, D. Ong
A full band Monte Carlo model is developed to simulate high field carrier transport in bulk InP. The realistic energy band structure used in this model is generated from the local empirical pseudopotential method. The simulated steady-state mean drift velocity and mean energy of electrons and holes as a function of electric fields are consistent with previous reported results. In our model, the electron and hole ionization coefficients are fitted to the available experimental data in the electric field range from 400 kV/cm to 900 kV/cm by a 'softer' threshold than the Keldysh model used in other full band Monte Carlo models described in the literature.
{"title":"Monte Carlo modeling of high field carrier transport in bulk InP","authors":"A. You, D. Ong","doi":"10.1109/SMELEC.2000.932457","DOIUrl":"https://doi.org/10.1109/SMELEC.2000.932457","url":null,"abstract":"A full band Monte Carlo model is developed to simulate high field carrier transport in bulk InP. The realistic energy band structure used in this model is generated from the local empirical pseudopotential method. The simulated steady-state mean drift velocity and mean energy of electrons and holes as a function of electric fields are consistent with previous reported results. In our model, the electron and hole ionization coefficients are fitted to the available experimental data in the electric field range from 400 kV/cm to 900 kV/cm by a 'softer' threshold than the Keldysh model used in other full band Monte Carlo models described in the literature.","PeriodicalId":359114,"journal":{"name":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127670605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-13DOI: 10.1109/SMELEC.2000.932475
M. Hasan, M. U. Siddiqi
With integration and miniaturization of electronic components, physical access to the boundary of the components on a printed circuit board or system is almost impossible. The IEEE 1149.1 and the boundary scan test have evolved to meet this challenge by electronically accessing the component boundary. In this paper, application of boundary scan test techniques at different levels of digital systems is discussed. Test generation for different interconnection faults on printed circuit boards and test application through the standard test access port is considered. Acceptance and potential capabilities of the method are presented.
{"title":"Hierarchical test approach using boundary scan test","authors":"M. Hasan, M. U. Siddiqi","doi":"10.1109/SMELEC.2000.932475","DOIUrl":"https://doi.org/10.1109/SMELEC.2000.932475","url":null,"abstract":"With integration and miniaturization of electronic components, physical access to the boundary of the components on a printed circuit board or system is almost impossible. The IEEE 1149.1 and the boundary scan test have evolved to meet this challenge by electronically accessing the component boundary. In this paper, application of boundary scan test techniques at different levels of digital systems is discussed. Test generation for different interconnection faults on printed circuit boards and test application through the standard test access port is considered. Acceptance and potential capabilities of the method are presented.","PeriodicalId":359114,"journal":{"name":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128752468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-13DOI: 10.1109/SMELEC.2000.932465
K. Khalid, A. Shaari
This paper presents a unified approach to the analysis of the shielded microstrip with multilayered dielectrics, using a variational technique in the Fourier transform domain. The analysis involves the calculation of the effective dielectric constant, characteristic impedance and dielectric loss of this system. The application of this approach for the development of a microstrip moisture sensor is presented. A rigorous general procedure for determination of the potential function using the transfer matrix approach has been developed. Interesting theoretical results are obtained from the analysis where effective dielectric constant, characteristic impedance and dielectric loss of the sensor are drastically effected by the thickness of the covering layer.
{"title":"Analysis of multilayered microstrip and its application for designing microstrip moisture sensor","authors":"K. Khalid, A. Shaari","doi":"10.1109/SMELEC.2000.932465","DOIUrl":"https://doi.org/10.1109/SMELEC.2000.932465","url":null,"abstract":"This paper presents a unified approach to the analysis of the shielded microstrip with multilayered dielectrics, using a variational technique in the Fourier transform domain. The analysis involves the calculation of the effective dielectric constant, characteristic impedance and dielectric loss of this system. The application of this approach for the development of a microstrip moisture sensor is presented. A rigorous general procedure for determination of the potential function using the transfer matrix approach has been developed. Interesting theoretical results are obtained from the analysis where effective dielectric constant, characteristic impedance and dielectric loss of the sensor are drastically effected by the thickness of the covering layer.","PeriodicalId":359114,"journal":{"name":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116864644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-13DOI: 10.1109/SMELEC.2000.932453
G. Omar, N. Tamaldin, M. Muhamad, Tan Chong Hock
The trend in microelectronic packaging is towards thinner and smaller packages. To achieve this, the die must be smaller and thinner as well, which means greater susceptibility to process related failures, especially in the front-end processes. Silicon strength has been recognized as an important parameter in wafer processing, packaging and die assembly due to process-induced stresses. The strength of the silicon wafer is heavily dependent on how the backside surface is prepared prior to metal deposition. Flaws such as small microcracks or etch pits can occur during backside processes, causing the strength of the silicon to decrease, leading to fracture. This paper investigates the effect of die strength on the surface morphology using a ball breaker test and atomic force microscopy (AFM). The die strength was characterized using the ball breaker test while surface morphology was characterized using AFM. The methodologies of the ball breaker test and AFM were documented. The evaluation was performed for wafers with wet etch, smooth grind and rough grind types of backside surface finish. It shows that wet etched wafers have the highest strength and rough grind have the lowest.
{"title":"Correlation of silicon wafer strength to the surface morphology","authors":"G. Omar, N. Tamaldin, M. Muhamad, Tan Chong Hock","doi":"10.1109/SMELEC.2000.932453","DOIUrl":"https://doi.org/10.1109/SMELEC.2000.932453","url":null,"abstract":"The trend in microelectronic packaging is towards thinner and smaller packages. To achieve this, the die must be smaller and thinner as well, which means greater susceptibility to process related failures, especially in the front-end processes. Silicon strength has been recognized as an important parameter in wafer processing, packaging and die assembly due to process-induced stresses. The strength of the silicon wafer is heavily dependent on how the backside surface is prepared prior to metal deposition. Flaws such as small microcracks or etch pits can occur during backside processes, causing the strength of the silicon to decrease, leading to fracture. This paper investigates the effect of die strength on the surface morphology using a ball breaker test and atomic force microscopy (AFM). The die strength was characterized using the ball breaker test while surface morphology was characterized using AFM. The methodologies of the ball breaker test and AFM were documented. The evaluation was performed for wafers with wet etch, smooth grind and rough grind types of backside surface finish. It shows that wet etched wafers have the highest strength and rough grind have the lowest.","PeriodicalId":359114,"journal":{"name":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114223584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-13DOI: 10.1109/SMELEC.2000.932438
S. M. Aziz, A. Harun-ur Rashid, M. Karim
Complementary pass-transistor logic (CPL) circuits result in speed improvement and power reduction compared to conventional static CMOS logic. However, the behaviour of this logic family under fault has not yet been studied. This paper presents the results of an investigation into the behaviour of CPL circuits under various single faults. It is shown that all single transistor stuck-on faults are only detectable by I/sub DDQ/ testing, while all single stuck-open faults are only detectable by logic monitoring. The majority of the single bridging faults between the gate and source/drain terminals of the MOS transistors can be detected by current monitoring while a few are undetectable.
{"title":"Fault characterisation of complementary pass-transistor logic circuits","authors":"S. M. Aziz, A. Harun-ur Rashid, M. Karim","doi":"10.1109/SMELEC.2000.932438","DOIUrl":"https://doi.org/10.1109/SMELEC.2000.932438","url":null,"abstract":"Complementary pass-transistor logic (CPL) circuits result in speed improvement and power reduction compared to conventional static CMOS logic. However, the behaviour of this logic family under fault has not yet been studied. This paper presents the results of an investigation into the behaviour of CPL circuits under various single faults. It is shown that all single transistor stuck-on faults are only detectable by I/sub DDQ/ testing, while all single stuck-open faults are only detectable by logic monitoring. The majority of the single bridging faults between the gate and source/drain terminals of the MOS transistors can be detected by current monitoring while a few are undetectable.","PeriodicalId":359114,"journal":{"name":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121561529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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