Pub Date : 2000-11-13DOI: 10.1109/SMELEC.2000.932436
V. Kasemsuwan
An analytical transit time model for short channel MOSFETs is presented. Several second order effects such as short channel and narrow width effects, mobility degradation, parasitic drain and source resistance, velocity saturation and channel length modulation are included in the model. The model shows good agreements with experimental and two dimensional numerical data over a wide range of biasing conditions.
{"title":"An analytical transit time model for short channel MOSFET's","authors":"V. Kasemsuwan","doi":"10.1109/SMELEC.2000.932436","DOIUrl":"https://doi.org/10.1109/SMELEC.2000.932436","url":null,"abstract":"An analytical transit time model for short channel MOSFETs is presented. Several second order effects such as short channel and narrow width effects, mobility degradation, parasitic drain and source resistance, velocity saturation and channel length modulation are included in the model. The model shows good agreements with experimental and two dimensional numerical data over a wide range of biasing conditions.","PeriodicalId":359114,"journal":{"name":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","volume":"371 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133964796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-13DOI: 10.1109/SMELEC.2000.932466
B. Bais, B. A. Ghafar, B. Y. Majlis
The uniformity of silicon dioxide as a passivation layer deposited by PECVD using IPL 2000 E/D was studied. A four inch wafer was used for the deposition using the PECVD technique with two reactant gases, silane (SiH/sub 4/) and nitrous oxide (N/sub 2/O), with substrate temperature of 300 /spl deg/C. Four samples were deposited at different times: 5, 10, 15 and 20 minutes. The deposited oxide thickness and its respective refractive index were measured using an ellipsometer and plotted against the deposition time. The deposition parameters were also observed and reported.
{"title":"A uniformity study of PECVD SiO/sub 2/ using IPL 2000 E/D","authors":"B. Bais, B. A. Ghafar, B. Y. Majlis","doi":"10.1109/SMELEC.2000.932466","DOIUrl":"https://doi.org/10.1109/SMELEC.2000.932466","url":null,"abstract":"The uniformity of silicon dioxide as a passivation layer deposited by PECVD using IPL 2000 E/D was studied. A four inch wafer was used for the deposition using the PECVD technique with two reactant gases, silane (SiH/sub 4/) and nitrous oxide (N/sub 2/O), with substrate temperature of 300 /spl deg/C. Four samples were deposited at different times: 5, 10, 15 and 20 minutes. The deposited oxide thickness and its respective refractive index were measured using an ellipsometer and plotted against the deposition time. The deposition parameters were also observed and reported.","PeriodicalId":359114,"journal":{"name":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","volume":"67 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133135960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-13DOI: 10.1109/SMELEC.2000.932299
C. Beenakker
This paper addresses new developments related to silicon technology and silicon devices in the areas of high speed integrated circuits, intelligent sensors, solar cells and large area electronics. These areas benefit strongly from the rapid advances made in ULSI technology without directly needing lateral dimensions in the 100 nm region and the extremely high investments related to these. As such, they form highly relevant research areas, which can successfully be executed in an academic environment. As examples, silicon-on-anything technology, high speed biochemical analysis systems, high speed deposition systems for solar cells and a new approach for making location controlled high performance TFTs on glass substrates are discussed briefly.
{"title":"New developments in silicon technology","authors":"C. Beenakker","doi":"10.1109/SMELEC.2000.932299","DOIUrl":"https://doi.org/10.1109/SMELEC.2000.932299","url":null,"abstract":"This paper addresses new developments related to silicon technology and silicon devices in the areas of high speed integrated circuits, intelligent sensors, solar cells and large area electronics. These areas benefit strongly from the rapid advances made in ULSI technology without directly needing lateral dimensions in the 100 nm region and the extremely high investments related to these. As such, they form highly relevant research areas, which can successfully be executed in an academic environment. As examples, silicon-on-anything technology, high speed biochemical analysis systems, high speed deposition systems for solar cells and a new approach for making location controlled high performance TFTs on glass substrates are discussed briefly.","PeriodicalId":359114,"journal":{"name":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130335001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-13DOI: 10.1109/SMELEC.2000.932470
S. Shaari, Mah Siew Kien
An analysis is made of the relationships between bandwidth, length increment, number of channels, number of waveguides and channel spacings in silica-based arrayed waveguide WDM. The study is based on beam propagation calculations on AWG structures of up to twenty channels. The AWGs are designed on a silica substrate with waveguide refractive index of 1.584 and layer refractive index of 1.522.
{"title":"Design implementation of up to 20 channel silica-based arrayed waveguide WDM","authors":"S. Shaari, Mah Siew Kien","doi":"10.1109/SMELEC.2000.932470","DOIUrl":"https://doi.org/10.1109/SMELEC.2000.932470","url":null,"abstract":"An analysis is made of the relationships between bandwidth, length increment, number of channels, number of waveguides and channel spacings in silica-based arrayed waveguide WDM. The study is based on beam propagation calculations on AWG structures of up to twenty channels. The AWGs are designed on a silica substrate with waveguide refractive index of 1.584 and layer refractive index of 1.522.","PeriodicalId":359114,"journal":{"name":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126049943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-13DOI: 10.1109/SMELEC.2000.932471
C.L. Lee, R. Wagiran, B.S. Suparjo, R. Sidek
This paper presents a low power pipelined-burst synchronized static random access memory. Low-power techniques are reviewed for capacitance reduction by using a divided word-line structure, and for operating voltage reduction by using a current-mode sensing technique for the sense amplifier. The SRAM is designed with address burst mode operation and selective byte write operation.
{"title":"The design of low-power CMOS pipelined-burst SRAM","authors":"C.L. Lee, R. Wagiran, B.S. Suparjo, R. Sidek","doi":"10.1109/SMELEC.2000.932471","DOIUrl":"https://doi.org/10.1109/SMELEC.2000.932471","url":null,"abstract":"This paper presents a low power pipelined-burst synchronized static random access memory. Low-power techniques are reviewed for capacitance reduction by using a divided word-line structure, and for operating voltage reduction by using a current-mode sensing technique for the sense amplifier. The SRAM is designed with address burst mode operation and selective byte write operation.","PeriodicalId":359114,"journal":{"name":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129211708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-13DOI: 10.1109/SMELEC.2000.932458
K. Nandhasri, J. Ngarmnil
A novel hysteresis tunable voltage comparator is presented. The circuit is basically a simple voltage comparator embedded with a positive feedback scheme to create the hysteresis. In this work, two floating-gate MOSFETs (FGMOS), are employed to perform the feedback where one of the control gate voltages is used to tune an amount of the feedback current for the input devices. As a result, V/sub TRP+/ and V/sub TRP-/ of the comparator can be tuned electronically. The proposed idea is implementable on standard double-poly CMOS processes. Since the design is normally incorporated with the FGMOS layout in order to get the value of the gate capacitances effectively, Magic Program is used to create the layouts on the AMI 1.2 /spl mu/m CMOS process available through MOSIS. Simulation results from HSPICE are given to demonstrate the functionality.
{"title":"Hysteresis tunable FGMOS comparator","authors":"K. Nandhasri, J. Ngarmnil","doi":"10.1109/SMELEC.2000.932458","DOIUrl":"https://doi.org/10.1109/SMELEC.2000.932458","url":null,"abstract":"A novel hysteresis tunable voltage comparator is presented. The circuit is basically a simple voltage comparator embedded with a positive feedback scheme to create the hysteresis. In this work, two floating-gate MOSFETs (FGMOS), are employed to perform the feedback where one of the control gate voltages is used to tune an amount of the feedback current for the input devices. As a result, V/sub TRP+/ and V/sub TRP-/ of the comparator can be tuned electronically. The proposed idea is implementable on standard double-poly CMOS processes. Since the design is normally incorporated with the FGMOS layout in order to get the value of the gate capacitances effectively, Magic Program is used to create the layouts on the AMI 1.2 /spl mu/m CMOS process available through MOSIS. Simulation results from HSPICE are given to demonstrate the functionality.","PeriodicalId":359114,"journal":{"name":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134150564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-13DOI: 10.1109/SMELEC.2000.932464
S. Shaari, M. Shong
The most significant feature of a fiber Bragg grating is the relatively narrow bandwidth of its reflection spectrum. In certain cases where a wider bandwidth is needed, we must modify the fiber Bragg grating. The best way to achieve this is by using a short grating length in the design of the fiber Bragg grating. The characteristics of short grating length have been observed using coupled mode theory methods. The short grating behaviour is clearly shown and discussed in this paper.
{"title":"Characteristics of large bandwidth fiber Bragg grating with short grating length","authors":"S. Shaari, M. Shong","doi":"10.1109/SMELEC.2000.932464","DOIUrl":"https://doi.org/10.1109/SMELEC.2000.932464","url":null,"abstract":"The most significant feature of a fiber Bragg grating is the relatively narrow bandwidth of its reflection spectrum. In certain cases where a wider bandwidth is needed, we must modify the fiber Bragg grating. The best way to achieve this is by using a short grating length in the design of the fiber Bragg grating. The characteristics of short grating length have been observed using coupled mode theory methods. The short grating behaviour is clearly shown and discussed in this paper.","PeriodicalId":359114,"journal":{"name":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116767722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-13DOI: 10.1109/SMELEC.2000.932452
A.A.A. Rahman, Z.A.A. Rashid, M. Othman
The first Malaysian made 16-bit RISC processor, the Pesona16/sup TM/, designed and developed by MIMOS is described in terms of its architecture, programming model and its functional capabilities. Performance analysis and comparison with other similar 16-bit processors in the market are also made.
{"title":"The Pesona16/sup TM/ RISC 16-bit microprocessor-architecture, functional configurations, and performances","authors":"A.A.A. Rahman, Z.A.A. Rashid, M. Othman","doi":"10.1109/SMELEC.2000.932452","DOIUrl":"https://doi.org/10.1109/SMELEC.2000.932452","url":null,"abstract":"The first Malaysian made 16-bit RISC processor, the Pesona16/sup TM/, designed and developed by MIMOS is described in terms of its architecture, programming model and its functional capabilities. Performance analysis and comparison with other similar 16-bit processors in the market are also made.","PeriodicalId":359114,"journal":{"name":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117182147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-13DOI: 10.1109/SMELEC.2000.932459
P. Tan, S.B. Suparjo, R. Wagiran, R. Sidek
An 8-bit CMOS analog-to-digital converter (ADC) has been designed using a more efficient architecture. The simplified multistep 8-bit ADC requires two 4-bit full-flash cycles by using a modified 4-bit full-flash ADC with a voltage estimator. The speed of this new architecture is similar to conventional half-flash ADC but the die area consumption is much less due to reduced numbers of comparators and resistors.
{"title":"An efficient architecture of 8-bit CMOS analog-to-digital converter","authors":"P. Tan, S.B. Suparjo, R. Wagiran, R. Sidek","doi":"10.1109/SMELEC.2000.932459","DOIUrl":"https://doi.org/10.1109/SMELEC.2000.932459","url":null,"abstract":"An 8-bit CMOS analog-to-digital converter (ADC) has been designed using a more efficient architecture. The simplified multistep 8-bit ADC requires two 4-bit full-flash cycles by using a modified 4-bit full-flash ADC with a voltage estimator. The speed of this new architecture is similar to conventional half-flash ADC but the die area consumption is much less due to reduced numbers of comparators and resistors.","PeriodicalId":359114,"journal":{"name":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114618576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-11-13DOI: 10.1109/SMELEC.2000.932447
W.F. Yaakob, Aiman Beg, A.A.A. Rahman, R. Kassim, M. Ahmad
The driving forces in developing a methodology to convert board-level designs to chip are design productivity and profit. The methodology gives significant productivity through reuse of existing designs. It must overcome on-chip system design bottlenecks; functional verification and timing convergence. Decisions must be made on components to be integrated on the same silicon, and hardware-software co-simulation strategy. This paper describes a system-on-a-chip design approach in developing a robotic controller for industrial applications.
{"title":"System-on-a-chip approach for industrial robotic controller design","authors":"W.F. Yaakob, Aiman Beg, A.A.A. Rahman, R. Kassim, M. Ahmad","doi":"10.1109/SMELEC.2000.932447","DOIUrl":"https://doi.org/10.1109/SMELEC.2000.932447","url":null,"abstract":"The driving forces in developing a methodology to convert board-level designs to chip are design productivity and profit. The methodology gives significant productivity through reuse of existing designs. It must overcome on-chip system design bottlenecks; functional verification and timing convergence. Decisions must be made on components to be integrated on the same silicon, and hardware-software co-simulation strategy. This paper describes a system-on-a-chip design approach in developing a robotic controller for industrial applications.","PeriodicalId":359114,"journal":{"name":"ICSE 2000. 2000 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.00EX425)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131764566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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