Pub Date : 2000-07-14DOI: 10.1109/IWIPP.2000.885179
Zhenxian Liang, F. Lee, G. Lu, D. Borojevic
A packaging integration technology, embedded power, has been developed for fabrication of integrated power electronics modules (IPEMs) and power electronics building blocks (PEBBs). The bare power chips are buried in the ceramic frame and encapsulated with screen-printed dielectric. High-density interconnect metallization between power devices and surface mountable electronics circuitry was fabricated using sputtering and electroplating technologies. Prototype modules have demonstrated the feasibility of this packaging approach.
{"title":"Embedded power-a multilayer integration technology for packaging of IPEMs and PEBBs","authors":"Zhenxian Liang, F. Lee, G. Lu, D. Borojevic","doi":"10.1109/IWIPP.2000.885179","DOIUrl":"https://doi.org/10.1109/IWIPP.2000.885179","url":null,"abstract":"A packaging integration technology, embedded power, has been developed for fabrication of integrated power electronics modules (IPEMs) and power electronics building blocks (PEBBs). The bare power chips are buried in the ceramic frame and encapsulated with screen-printed dielectric. High-density interconnect metallization between power devices and surface mountable electronics circuitry was fabricated using sputtering and electroplating technologies. Prototype modules have demonstrated the feasibility of this packaging approach.","PeriodicalId":359131,"journal":{"name":"IWIPP 2000. International Workshop on Integrated Power Packaging (Cat. No.00EX426)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125645190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-07-14DOI: 10.1109/IWIPP.2000.885183
T. McMillan
There are many electromagnetic compatibility (EMC) requirements that must be met for information technology equipment (ITE). These requirements must be met by any power assemblies that are part of the final product. EMC bench testing of these power assemblies can be performed prior to integration into final products so that problems can be identified and engineering changes made early in the design cycle. The test configurations and procedures needed to perform the EMC bench testing have many elements that take into consideration where the assemblies will be used, the number of assemblies, and the EMC requirements to be met.
{"title":"Electromagnetic compatibility: bench testing for power assemblies","authors":"T. McMillan","doi":"10.1109/IWIPP.2000.885183","DOIUrl":"https://doi.org/10.1109/IWIPP.2000.885183","url":null,"abstract":"There are many electromagnetic compatibility (EMC) requirements that must be met for information technology equipment (ITE). These requirements must be met by any power assemblies that are part of the final product. EMC bench testing of these power assemblies can be performed prior to integration into final products so that problems can be identified and engineering changes made early in the design cycle. The test configurations and procedures needed to perform the EMC bench testing have many elements that take into consideration where the assemblies will be used, the number of assemblies, and the EMC requirements to be met.","PeriodicalId":359131,"journal":{"name":"IWIPP 2000. International Workshop on Integrated Power Packaging (Cat. No.00EX426)","volume":"1541 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129121729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-07-14DOI: 10.1109/IWIPP.2000.885178
A. B. Lostetter, Fred Barlow, A. Elshabini, K. Olejniczak, S. Ang
Electronic power converters have been designed, produced, and disseminated in mass quantities using a number of fabrication techniques, from standard PCB technologies for low cost applications, to thick film on ceramic, to direct bond copper (DBC) for high power, higher cost applications. Each approach holds a share of the power packaging market, but they all restrict, for the most part, circuit and package designs to 2D boards. One potential pathway into the third dimension is by the use of multilayers, an approach which becomes increasingly difficult with each additional layer added beyond the first, and with the exception of high performance solutions is typically cost prohibitive for the majority of applications. This paper demonstrates the feasibility and viability of an alternative low cost power packaging option which uses familiar industry technologies in a unique manner: flexible polymer substrates. Flex technology uses industry standard PCB and/or thick film processes, offers the lower cost, higher performance solutions inherent with the majority of polymer plastics, and as a final bonus, frees the designer to more efficiently use all three dimensions. The researchers have shown the feasibility of this low cost alternative solution through the fabrication and testing of integrated power modules (IPMs) which use flex polymer substrates in conjunction with both surface mount and bare dice. These DC/DC power converters transform 120 V/240 V inputs to 9V, 7 W outputs, and illustrate the miniaturization advantages of fully utilizing the 3D space offered by flex circuitry.
{"title":"Polymer thick film (PTF) and flex technologies for low cost power electronics packaging","authors":"A. B. Lostetter, Fred Barlow, A. Elshabini, K. Olejniczak, S. Ang","doi":"10.1109/IWIPP.2000.885178","DOIUrl":"https://doi.org/10.1109/IWIPP.2000.885178","url":null,"abstract":"Electronic power converters have been designed, produced, and disseminated in mass quantities using a number of fabrication techniques, from standard PCB technologies for low cost applications, to thick film on ceramic, to direct bond copper (DBC) for high power, higher cost applications. Each approach holds a share of the power packaging market, but they all restrict, for the most part, circuit and package designs to 2D boards. One potential pathway into the third dimension is by the use of multilayers, an approach which becomes increasingly difficult with each additional layer added beyond the first, and with the exception of high performance solutions is typically cost prohibitive for the majority of applications. This paper demonstrates the feasibility and viability of an alternative low cost power packaging option which uses familiar industry technologies in a unique manner: flexible polymer substrates. Flex technology uses industry standard PCB and/or thick film processes, offers the lower cost, higher performance solutions inherent with the majority of polymer plastics, and as a final bonus, frees the designer to more efficiently use all three dimensions. The researchers have shown the feasibility of this low cost alternative solution through the fabrication and testing of integrated power modules (IPMs) which use flex polymer substrates in conjunction with both surface mount and bare dice. These DC/DC power converters transform 120 V/240 V inputs to 9V, 7 W outputs, and illustrate the miniaturization advantages of fully utilizing the 3D space offered by flex circuitry.","PeriodicalId":359131,"journal":{"name":"IWIPP 2000. International Workshop on Integrated Power Packaging (Cat. No.00EX426)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117301401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-07-14DOI: 10.1109/IWIPP.2000.885169
G. Venkataramanan
Advances in electric power conversion systems have generally lagged far behind the pace of advances in the field of digital signal electronic systems. This has been a result of the rich and complicated coupling that exists among various design variables and manufacturing processes used in power electronics. There are significant obstacles that defy scaling which hold back the progress of power electronic systems. This paper presents an integrated architectural framework capable of systematically overcoming these obstacles using a top-down conceptual approach. General principles of the proposed framework based on "bricks and buses" are presented along with a discussion of the details that constitute the framework.
{"title":"An integrated architectural framework for power conversion systems","authors":"G. Venkataramanan","doi":"10.1109/IWIPP.2000.885169","DOIUrl":"https://doi.org/10.1109/IWIPP.2000.885169","url":null,"abstract":"Advances in electric power conversion systems have generally lagged far behind the pace of advances in the field of digital signal electronic systems. This has been a result of the rich and complicated coupling that exists among various design variables and manufacturing processes used in power electronics. There are significant obstacles that defy scaling which hold back the progress of power electronic systems. This paper presents an integrated architectural framework capable of systematically overcoming these obstacles using a top-down conceptual approach. General principles of the proposed framework based on \"bricks and buses\" are presented along with a discussion of the details that constitute the framework.","PeriodicalId":359131,"journal":{"name":"IWIPP 2000. International Workshop on Integrated Power Packaging (Cat. No.00EX426)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122394884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-07-14DOI: 10.1109/IWIPP.2000.885186
J.-M. Thebaud, E. Woirgard, C. Zardini, K. Sommer
Extensive accelerated aging tests have been carried out with representative test structures in order to evaluate the thermal fatigue resistance of five solder alloys intended for high power IGBT modules. With regard to the chip-to-substrate samples, Pb-free preforms have given excellent results since the thermal impedance of these hybrid assemblies has hardly changed during thermal cycling, even after 2000 shocks between +125/spl deg/C and -55/spl deg/C (less than 5%). The best results have been clearly obtained with the finest solder microstructures. In addition, the analysis of the results has led to an evaluation of the acceleration factor of the thermal fatigue tests. Finally, SEM observations of cross-sectioned samples have shown crack propagation during thermal cycling which is responsible for the increased thermal impedance. However, with regard to substrate-to-baseplate samples, the best results have been obtained with a Pb-bearing solder alloy strongly subject to coarsening during thermal cycling. Moreover, it has been demonstrated that fast cooling can cut crack growth rate in the solder joints by half. In addition, EDX analyses have shown copper diffusion all over the solder joint when the DBC (direct bonded copper) substrate is not nickel-plated, which seems to slightly improve its fatigue resistance. Finally, these experiments have shown that fine solder microstructures do not necessarily lead to good fatigue performances at high levels of stress or strain.
{"title":"High power IGBT modules: thermal fatigue resistance evaluation of the solder joints","authors":"J.-M. Thebaud, E. Woirgard, C. Zardini, K. Sommer","doi":"10.1109/IWIPP.2000.885186","DOIUrl":"https://doi.org/10.1109/IWIPP.2000.885186","url":null,"abstract":"Extensive accelerated aging tests have been carried out with representative test structures in order to evaluate the thermal fatigue resistance of five solder alloys intended for high power IGBT modules. With regard to the chip-to-substrate samples, Pb-free preforms have given excellent results since the thermal impedance of these hybrid assemblies has hardly changed during thermal cycling, even after 2000 shocks between +125/spl deg/C and -55/spl deg/C (less than 5%). The best results have been clearly obtained with the finest solder microstructures. In addition, the analysis of the results has led to an evaluation of the acceleration factor of the thermal fatigue tests. Finally, SEM observations of cross-sectioned samples have shown crack propagation during thermal cycling which is responsible for the increased thermal impedance. However, with regard to substrate-to-baseplate samples, the best results have been obtained with a Pb-bearing solder alloy strongly subject to coarsening during thermal cycling. Moreover, it has been demonstrated that fast cooling can cut crack growth rate in the solder joints by half. In addition, EDX analyses have shown copper diffusion all over the solder joint when the DBC (direct bonded copper) substrate is not nickel-plated, which seems to slightly improve its fatigue resistance. Finally, these experiments have shown that fine solder microstructures do not necessarily lead to good fatigue performances at high levels of stress or strain.","PeriodicalId":359131,"journal":{"name":"IWIPP 2000. International Workshop on Integrated Power Packaging (Cat. No.00EX426)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127851553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-07-14DOI: 10.1109/IWIPP.2000.885188
S. Haque, G. Lu
This paper presents processing issues of solderable metallization on two different IGBTs (insulated gate bipolar transistors) for three-dimensional packaging. Identical metallization processes via sputtering have resulted in different contact resistances due to the different passivation materials (Si/sub 3/N/sub 4/ and polyimide) of the two devices. XPS and SEM characterization of surface compositions of device contact pads resulting in different electrical contact resistances are analyzed.
{"title":"Characterization of solderable metallization on power devices for 3-D packaging","authors":"S. Haque, G. Lu","doi":"10.1109/IWIPP.2000.885188","DOIUrl":"https://doi.org/10.1109/IWIPP.2000.885188","url":null,"abstract":"This paper presents processing issues of solderable metallization on two different IGBTs (insulated gate bipolar transistors) for three-dimensional packaging. Identical metallization processes via sputtering have resulted in different contact resistances due to the different passivation materials (Si/sub 3/N/sub 4/ and polyimide) of the two devices. XPS and SEM characterization of surface compositions of device contact pads resulting in different electrical contact resistances are analyzed.","PeriodicalId":359131,"journal":{"name":"IWIPP 2000. International Workshop on Integrated Power Packaging (Cat. No.00EX426)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125820871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-07-14DOI: 10.1109/IWIPP.2000.885187
P. Procter, T. R. Miles
Anhydride cured epoxy molding compounds offer inherently high glass transition temperature (T/sub g/), high adhesion and low dielectric constant at a moderate cost. However, historical drawbacks of anhydride-cured compounds (poor moldability and moisture resistance, high coefficient of thermal expansion, shrinkage and brittleness) have limited their use for surface mount applications. This paper details the development of new anhydride compounds designed specifically for surface mount power applications.
{"title":"Low stress anhydride molding compound for RF applications","authors":"P. Procter, T. R. Miles","doi":"10.1109/IWIPP.2000.885187","DOIUrl":"https://doi.org/10.1109/IWIPP.2000.885187","url":null,"abstract":"Anhydride cured epoxy molding compounds offer inherently high glass transition temperature (T/sub g/), high adhesion and low dielectric constant at a moderate cost. However, historical drawbacks of anhydride-cured compounds (poor moldability and moisture resistance, high coefficient of thermal expansion, shrinkage and brittleness) have limited their use for surface mount applications. This paper details the development of new anhydride compounds designed specifically for surface mount power applications.","PeriodicalId":359131,"journal":{"name":"IWIPP 2000. International Workshop on Integrated Power Packaging (Cat. No.00EX426)","volume":"306 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120984449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-07-14DOI: 10.1109/IWIPP.2000.885184
A. Collado, X. Jordà, E. Cabruja, P. Godignon
The aim of this work is the development of a new intelligent power module, called IPMCM (intelligent power multichip module). This module combines the fabrication technology of multichip modules on silicon substrates with that of power transistors. The fabricated IPMCM includes a VDMOSFET at the substrate level and a gate driver at the flip-chip level, in addition to two temperature sensor chips for thermal assessment of the module. A DC-DC converter, an H-bridge circuit, has been implemented by using four of these IPMCMs mounted onto an IMS substrate with some other SMD components for a motor control application.
{"title":"MCM-D package for power applications","authors":"A. Collado, X. Jordà, E. Cabruja, P. Godignon","doi":"10.1109/IWIPP.2000.885184","DOIUrl":"https://doi.org/10.1109/IWIPP.2000.885184","url":null,"abstract":"The aim of this work is the development of a new intelligent power module, called IPMCM (intelligent power multichip module). This module combines the fabrication technology of multichip modules on silicon substrates with that of power transistors. The fabricated IPMCM includes a VDMOSFET at the substrate level and a gate driver at the flip-chip level, in addition to two temperature sensor chips for thermal assessment of the module. A DC-DC converter, an H-bridge circuit, has been implemented by using four of these IPMCMs mounted onto an IMS substrate with some other SMD components for a motor control application.","PeriodicalId":359131,"journal":{"name":"IWIPP 2000. International Workshop on Integrated Power Packaging (Cat. No.00EX426)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131977495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-07-14DOI: 10.1109/IWIPP.2000.885167
B. Ozmat, C. Korman, R. Fillion
Chip-on-flex power overlay technology, the advanced power electronic packaging technology developed at GE CRD, eliminates the need for wire bonds, offers low inductance strip-lined power electrodes, and low parasitic impedance. In addition, the planarity of the top layer structure and the thermal base provide double-sided cooling capability and improve the size, weight, cost, and thermal and electrical performance of the package.
GE CRD开发的先进电力电子封装技术芯片柔性电源覆盖技术消除了对线键的需求，提供了低电感带衬里功率电极和低寄生阻抗。此外，顶层结构和热基的平面性提供了双面冷却能力，并改善了封装的尺寸、重量、成本和热电性能。
{"title":"An advanced approach to power module packaging","authors":"B. Ozmat, C. Korman, R. Fillion","doi":"10.1109/IWIPP.2000.885167","DOIUrl":"https://doi.org/10.1109/IWIPP.2000.885167","url":null,"abstract":"Chip-on-flex power overlay technology, the advanced power electronic packaging technology developed at GE CRD, eliminates the need for wire bonds, offers low inductance strip-lined power electrodes, and low parasitic impedance. In addition, the planarity of the top layer structure and the thermal base provide double-sided cooling capability and improve the size, weight, cost, and thermal and electrical performance of the package.","PeriodicalId":359131,"journal":{"name":"IWIPP 2000. International Workshop on Integrated Power Packaging (Cat. No.00EX426)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125512407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-07-14DOI: 10.1109/IWIPP.2000.885191
S. Prabhakaran, D.E. Kreider, Yu Lin, C. Sullivan, C. Levey
A new fabrication process is described for high performance embedded or integrated inductors for power converters. The process includes etching V-grooves in a silicon substrate, depositing granular composite magnetic materials, and electroplating the copper conductors.
{"title":"Fabrication of thin-film V-groove inductors using composite magnetic materials","authors":"S. Prabhakaran, D.E. Kreider, Yu Lin, C. Sullivan, C. Levey","doi":"10.1109/IWIPP.2000.885191","DOIUrl":"https://doi.org/10.1109/IWIPP.2000.885191","url":null,"abstract":"A new fabrication process is described for high performance embedded or integrated inductors for power converters. The process includes etching V-grooves in a silicon substrate, depositing granular composite magnetic materials, and electroplating the copper conductors.","PeriodicalId":359131,"journal":{"name":"IWIPP 2000. International Workshop on Integrated Power Packaging (Cat. No.00EX426)","volume":"173 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113973032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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